Finite State Machines

ECSE 323 Digital System Design

Finite State Machines

Prof. Warren Gross

Material used in this set of slides was based on “Fundamentals of Digital Logic with VHDL Design” by S. Brown and Z. Vranesic

1

Textbook Reading

•  Chapter 8 – 8.13 has solved problems

2

Up unGl now…

•  CombinaGonal circuits – Outputs depend only on the present value of inputs

•  Memory elements (flip-‐flops) – Output of flip-‐flop depends on its state –  Inputs causes changes in the state

•  Simple sequenGal circuits –  Registers and counters

3

Synchronous SequenGal Circuits

•  SequenGal à outputs depend on the past behaviour of the circuit and also on the present value of the inputs

•  Synchronous à clock

•  In this chapter we will study a design methodology for synchronous sequenGal circuits

4

The Basics

•  The past behavior of the circuit is encapsulated by the “state” of the circuit

•  We need memory elements to store the state – Flip flops – Only one state / clock cycle à edge-‐triggered FFs

5

The general form of a sequenGal circuit.

CombinaGonal circuit

Flip-‐flops

Clock

Q

W Z


6

Finite-‐State Machine Design •  Flip-‐flops –  Store the state –  This is the only circuit that depends on the clock – On the clock edge, the current state is updated

•  CombinaGonal circuits will do the rest – Next state logic: Compute the next state

•  fn(current state, inputs) – Output logic

“Moore” machine: fn(current state), or “Mealy” machine: fn(current state, inputs)

7

Step 1. SpecificaGon •  Example: Sequence detector

–  Design a circuit that detects if two or more consecuGve 1s appear on its input

•  One input, w, and one output z •  All changes in the circuit occur on the posiGve edge of a clock signal

•  The output z is equal to 1 if during two immediately preceding clock cycles the input was equal to 1. Otherwise, the value of z is equal to 0.

8

Sequences of input and output signals.

Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0

9

Step 2. State Diagram •  How many states are needed?

–  No set procedure for determining

•  Good way to begin: choose a star=ng state –  The state the circuit enters when a reset signal is applied –  Call this state “A” – Move between states only on clock edge: state diagram shows sequence of states in response to inputs

– We consider “Reset” and “Clock” as special inputs •  Implemented by clock and clear/preset inputs on flip-‐flops

10

State diagram of a simple sequenGal circuit.

C z 1 = ⁄

Reset

B z 0 = ⁄ A z 0 = ⁄ w 0 =

w 1 =

w 1 =

w 0 =

w 0 = w 1 =

11

Present Next state Output state w = 0 w = 1 z

A A B 0 B A C 0 C A C 1

Step 3. State Table

12

Implicit assumpGon that the first state is the starGng state

Moore machine

Step 5. State Assignment

•  Assign numerical values to the state labels.

•  Define state variables –  In this case, need 2 state variables y1 and y2

– Each state variable is implemented with a flip-‐flop

13

Combinational circuit


Clock

y 2

z

w y 1 Y 1

Y 2

14

Present state variables Next state variables

State Assignment •  Choose a mapping from state label to state variables

– Many such mappings –  The choice of mapping determines the resulGng circuit complexity

•  For now, choose any mapping, say

A à y2y1 = 00, Bà y2y1 = 01, C à y2y1 = 10

•  The fourth value y2y1 = 11 is not needed

15

Present Next state

state w = 0 w = 1 Output

y 2 y 1 Y 2 Y 1 Y 2 Y 1 z

A 00 00 01 0

B 01 00 10 0

C 10 00 10 1 11 dd dd d

State-‐Assigned Table

16

Step 6. Next-‐State and Output Logic

•  First, choose flip-‐flop type – Most straighiorward is to choose D flip-‐flops •  Apply the next state variables to the D inputs of the FFs •  Next state variables (Y1,Y2) are clocked into the flip flops on the next rising clock edge to become the new values of the present state (y1,y2)

– Most common design technique and ojen CAD tools assume rising-‐edge-‐triggered D flip-‐flops

– We will look at examples of design with other FF types later in this chapter

17

Next-‐State and Output Logic

•  Derive the next-‐state and output expressions

•  Don’t cares for y1y2 = 11 can help simplify the expressions

18

w 00 01 11 10

0

1

0

1 0

y 2 y 1

Y 1 wy 1 y 2 =

w 00 01 11 10

0

1

0 d

1 d

y 2 y 1

Y 2 wy 1 y 2 wy 1 y 2 + =

d

d

0

0

0

0

0

0

1

0 1

0

1

0

d

y 1

z y 1 y 2 =

0

1

y 2

Y 1 wy 1 y 2 =

Y 2 wy 1 wy 2 + =

z y 2 =

w y 1 y 2 + ( ) =

Ignoring don't cares Using don't cares

19

D Q

Q

D Q

Q

Y 2

Y 1 w

Clock

z

y 1

y 2

Resetn

Step 7. ImplementaGon

20

Timing diagram

t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 1 0

1

0

1 0

1

0

Clock

w

y 1

y 2

1

0 z

21

Signal changes occur shortly ajer posiGve edge of clock

Changes on input occur ajer posiGve clock edge

Summary of Design Steps 1.  Obtain specificaGons of desired circuit 2.  Choose starGng state and derive state diagram 3.  Create a state table from the state diagram 4.  Minimize the number of states

–  It is hard to come up with a state table with the minimum number of required states. We will cover state minimizaGon later in this chapter.

5.  Assign state variables –  Some assignments are beoer than others. Will come back to

this. 6.  Choose flip-‐flop type and derive next-‐state and output

expressions 7.  Implement the circuit

22

Example: Bus Design •  Example is taken from SecGon 7.14.1 •  k n-‐bit registers R1…Rk •  A bus is a common set of n wires that are used to transfer data into and out of the registers

•  It is essenGal that only one register aoempts to place data onto the bus wires at any given Gme –  Use tri-‐state buffers

•  The circuit design is divided into two parts: –  Datapath –  Control

23

24

Details of connecGng two 2-‐bit registers to a bus

25

Bus Control Circuit

•  Many possible control specificaGons possible – Depends on the desired funcGonality

•  Many ways to design the control circuit – 7.14.1 gives some examples – We will apply the FSM design procedure to design the control circuit

•  We will design a control mechanism that swaps the contents of two registers R1 and R2

26

SpecificaGon

•  Use a temporary register R3

•  Transfer contents of R2 into R3 (R2out = 1, R3in = 1) •  Transfer contents of R1 into R2 (R1out = 1, R2in = 1) •  Transfer contents of R3 into R1 (R3out = 1, R1in = 1) •  Set Done = 1

•  Assume the start of the swap is signaled by a pulse of duraGon one clock cycle on an input signal w

27

Control circuit

w

Clock

Done

R 1 out

R 2 out

R 1 in

R 2 in R 3 out R 3 in

28

State diagram. Output signals only indicated if equal to 1, in all other cases set to 0.

D R 3 out 1 = R 1 in 1 = Done 1 = , , ⁄

w 0 = w 1 =

C R 1 out 1 = R 2 in 1 = , ⁄

B R 2 out 1 = R 3 in 1 = , ⁄

w 1 =

A No ⁄

w 0 = w 1 =

transfer

w 0 = w 1 =

Reset

w 0 =

29

Contents will be placed in R3 on the next acGve clock edge

State table.

Present Next state Outputs state

A A B 0 0 0 0 0 0 0 B C C 0 0 1 0 0 1 0 C D D 1 0 0 1 0 0 0 D A A 0 1 0 0 1 0 1

w = 0 w = 1

30

State-‐assigned table.

Present Next state state Outputs

A 00 00 0 1 0 0 0 0 0 0 0 B 01 10 1 0 0 0 1 0 0 1 0 C 10 11 1 1 1 0 0 1 0 0 0 D 11 00 0 0 0 1 0 0 1 0 1

31

DerivaGon of next-‐state expressions.

w 0 0 0 1 1 1 1 0

0

1

1

1 1

y 2 y 1

Y 1 wy1 y 1 y 2 + =

w 00 01 11 10

0

1

1 1

1 1

y 2 y 1

Y 2 y 1 y 2 y 1 y 2 + =

32

33

R1out = R2in = y1’y2 R1in = R3out = Done = y1y2 R2out = R3in = y1y2’

Output expressions.

D Q

Q

D Q

Q

Done

w

Clock

Y 2

Y 1

y 2

y 1

y 2

y 1

R 1 in

R 3 out

R 1 out

R 2 in

R 2 out

R 3 in

34

State Assignment

•  Some state assignments may be beoer than others

•  Let’s revisit the sequence detector example and see what happens if we make a different state assignment – Can an even simpler circuit be derived?

– Let’s try A,B,C à y2y1 = 00,01,11 – y2y1 = 10 is not needed

35

Improved state assignment.

Present Next state


y 2 y 1 Y 2 Y 1 Y 2 Y 1 z

A 00 00 01 0 B 01 00 11 0 C 11 00 11 1

10 dd dd d

36

Y1 = D1 = w Y2 = D2 = wy1 z = y2

D Q

Q

D Q

Q

Y 2

Y 1 w

Clock

z

y 1

y 2

Resetn

37

Example: Bus

•  Revisit the bus controller design and switch the state assignments for states C and D

38

Present Nextstate state Outputs

A 00 0 0 01 0 0 0 0 0 0 0 B 01 1 1 11 0 0 1 0 0 1 0 C 11 1 0 10 1 0 0 1 0 0 0 D 10 0 0 00 0 1 0 0 1 0 1

w 00 01 11 10

0

1

1

1 1

y 2 y 1

Y 1 wy 2 y 1 y 2 + =

w 00 01 11 10

0

1

1 1

1 1

y 2 y 1

Y 2 y 1 =

39

R1out = R2in = y1y2 R1in = R3out = Done = y1’y2 R2out = R3in = y1y2’

The resulGng circuit is slightly simpler than the previous one.

The State Assignment Problem •  In general, when designing circuits with large numbers of states, the state assignment will have a substanGal effect on the cost of the final implementaGon

•  ExhausGve approach of trying all possible state assignments is not pracGcal

•  In pracGce, you design the state diagram with state labels and let the CAD tool do the state assignment –  CAD tools typically use heurisGcs to get a good-‐enough soluGon

40

One-‐Hot Encoding •  Use as many state variables as there are states

–  Only one of them is ‘1’ or hot at once –  Revisit sequence detector

41


A A B 0 B A C 0 C A C 1

Present Nextstate


y 3 y 2 y 1 Y 3 Y 2 Y 1 Y 3 Y 2 Y 1 z

A 001 001 010 0 B 010 001 100 0 C 100 001 100 1

•  Treat remaining 5 state valuaGons as don’t cares

•  None of the next-‐state variables depend on y2

•  The second flip-‐flop and expression for Y2 is not needed –  CAD tools can detect and eliminate such redundancies

•  Even so, the derived expressions are not simpler than those derived using the original state assignment in this case

•  In other designs, it may be advantageous to use one-‐hot encoding

42

Y1 = w’ Y2 = wy1 Y3 = wy1’ z = y3

Bus Controller Example using One-‐Hot State Assignment

43

Present Nextstate state Outputs

A 0 001 0001 0010 0 0 0 0 0 0 0 B 0 010 0100 0100 0 0 1 0 0 1 0 C 0 100 1000 1000 1 0 0 1 0 0 0 D 1 000 0001 0001 0 1 0 0 1 0 1

Treat the remaining 12 state valuaGons as don’t cares

Y1 = w ‘y1 + y4 Y2 = w y1 Y3 = y2 Y4 = y3

R1out = R2in = y3 R1in = R3out = Done = y4 R2out = R3in = y2

Can see this from inspecGon of the state diagram

Bus Example

•  Output expressions are simpler using one-‐hot encoding

•  4 Flip-‐Flops are needed instead of 2 •  One-‐hot state encoding ojen leads to simpler output expressions à may lead to a faster circuit –  i.e. if outputs are just outputs of FF’s, don’t need to wait for the propagaGon delay of gates in an output circuit

44

Mealy State Model

•  There are many ways to design finite state machines as a synchronous sequenGal circuit – each results in a different cost and Gming

•  Mealy machines offer another set of possibiliGes – Output generated based on both the state of the circuit and the present values of its inputs

45

Clock cycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0

Example •  Sequence detector •  Slightly different specificaGons – Original: z = 1 in the clock cycle that follows the second occurrence of w = 1

–  New: z = 1 in the same clock cycle when the second occurrence of w = 1 is detected

46

A

w 0 = z 0 = ⁄

w 1 = z 1 = ⁄ B w 0 = z 0 = ⁄

Reset w 1 = z 0 = ⁄

47

During the present clock cycle the output value corresponds to the label on the arc emanaGng from the present-‐state node.

State table.

Present Next state Output z

state w = 0 w = 1 w = 0 w = 1

A A B 0 0 B A B 0 1

48 State-‐assigned table.

Present Next state Output state w = 0 w = 1 w = 0 w = 1

y Y Y z z

A 0 0 1 0 0 B 1 0 1 0 1

Y = D = w z = wy

Clock

Resetn

D Q

Q

w

z

(a) Circuit

t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 1 0 1 0 1 0 1 0

Clock

y

w

z

y

(b) Timing diagram

49

Circuit that implements the original specificaGons

Clock Resetn

D Q

Q

w

z

(a) Circuit

t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 101 0 1 0

1 0 1 0

Clock

y

w

z

y

(b) Timing diagram

D Q

Q

Z

1 0

Z

50

R 3 out 1 = R 1 in 1 = Done 1 = , , w 0 = w 1 =

R 1 out 1 = R 2 in 1 = ,

w 1 = R ⁄ 2 out 1 = R 3 in 1 = ,

A

w 0 = w 1 =

Reset

w 0 =

B

C

Mealy Machine for Bus Controller

•  Requires 3 instead of 4 states –  SGll requires 2 flip-‐flops

•  Timing is different –  Generates output control

signals one clock cycle sooner –  EnGre process takes 3 instead

of 4 cycles for the Moore machine

•  Figure 7.58 in the text is derived using an ad-‐hoc approach –  Can be derived from this state

diagram by using a one-‐hot state assignment

51

Design of FSMs using VHDL

•  Rudimentary method: – Use the design technique previously described to design the next state logic, output logic and flip-‐flop circuits

– Use schemaGc diagrams or structural VHDL to describe these circuits. E.g. use components for the flip flops, etc…

– Use CAD tools to simulate the behavior – Use CAD tools to automaGcally implement the circuit in a chip, such as a PLD

52

Behavioral DescripGon

•  Design the state diagram and let the CAD tools synthesize a FSM from it. – CAD tools take care of synthesis and opGmizaGons (state assignment, logic/state minimizaGon).

•  Enter the state diagram into CAD tools – Draw using a graphical editor – Use behavioral VHDL (more common)

53

But first… •  Let’s recall the VHDL process block.

•  What circuit is described by this process block?

PROCESS(Sel,x1,x2) BEGIN IF Sel = ‘0’ THEN f <= x1; ELSE f <= x2; END IF;

END PROCESS;

54

Process Blocks •  The process block allows you to use sequenGal statements such as if-

then, case, for-loop, and while-loop. –  The sequenGal part means that the order of the statements in a process

block determines how the VHDL compiler interprets your circuit descripGon. –  It DOES NOT mean that it generates a sequenGal circuit.

•  The if-‐then code on the last slide synthesizes to a combina=onal mulGplexer –  It DOES NOT generate a sequenGal circuit that tests Sel in one Gme instant

(clock cycle) and then assigns a memory locaGon f either the value stored in x1 or x2

•  VHDL descripEons ARE NOT PROGRAMS !!!! •  VHDL IS NOT LIKE C PROGRAMMING !!!!

55

Another Example PROCESS(Sel,x1,x2) BEGIN CASE Sel IS WHEN ‘0’ => f <= x1; WHEN OTHERS => f <= x2; END CASE; END PROCESS;

56

SequenGal Circuits

•  OK, now let’s finally add a clock and synthesize a synchronous sequenGal circuit

•  The process block is required to synthesize a behavioral VHDL descripGon of a synchronous sequenGal circuit – You can alternaGvely use structural VHDL (FF components) and purely concurrent statements

57

VHDL for D Flip-‐Flop

58

VHDL for Moore-‐Type FSMs •  There are many ways to describe a FSM in VHDL

– We will describe 2 ways •  Line numbers shown are for convenience and are not part of VHDL

•  Example: Moore-‐type sequence detector

59

1 LIBRARY ieee ; 2 USE ieee.std_logic_1164.all ; 3 ENTITY simple IS 4 PORT ( Clock, Resetn, w : IN STD_LOGIC ;

z : OUT STD_LOGIC ) ; 5 END simple ;

60

7 ARCHITECTURE Behavior OF simple IS 8 TYPE State_type IS (A, B, C) ; 9 SIGNAL y : State_type ; 10 BEGIN 11 PROCESS ( Resetn, Clock ) 12 BEGIN 13 IF Resetn = '0' THEN 14 y <= A ; 15 ELSIF (Clock'EVENT AND Clock = '1') THEN 16 CASE y IS 17 WHEN A => 18 IF w = '0' THEN 19 y <= A ; 20 ELSE 21 y <= B ; 22 END IF ; 23 WHEN B => 24 IF w = '0' THEN 25 y <= A ; 26 ELSE 27 y <= C ; 28 END IF ; 29 WHEN C => 30 IF w = '0' THEN 31 y <= A ; 32 ELSE 33 y <= C ; 34 END IF ; 35 END CASE ; 36 END IF ; 37 END PROCESS ; 38 z <= '1' WHEN y = C ELSE '0' ; 39 END Behavior ;

C z 1 = ⁄

Resetn

B z 0 = ⁄ A z 0 = ⁄ w 0 =

w 1 =

w 1 =

w 0 =

w 0 = w 1 =

•  The VHDL synthesizer will automaGcally do the state assignment. i.e. it chooses the number of flip-‐flops to use and the assignment of state variable values to the state symbolic labels A, B, and C

•  Quartus II assumes the first state listed is the reset state and assigns it so that all FF outputs are equal to 0

Synthesis in a CPLD

61

Y 2 wy 1 wy 2 + =

z y 2 =

Y 1 wy 1 y 2 =

y 1 D Q

D Q

Clock

1

1 1

PAL-like block

Interconnection wires

(Other macrocells are not shown)

1

0

0

z

w

Resetn

y 2

EPM7032

z

Rese

tnw

Cloc

k

Gnd

V

DD

1 4 7

10

13

1619 22 25 28

44 39

36

62

SimulaGon and TesGng •  Assume a 100 ns clock period •  For this simple circuit, it is quite straighiorward

to verify the behavior is what we expect •  For more complex sequenGal circuits it becomes

very difficult to test –  Must carefully chose input paoerns to test circuit

with. We will study this later in the course

63

Remember ! If you don’t draw it … it won’t work If you don’t simulate it … it won’t work If you don’t test it … it won’t work

•  You should be able to draw at the register-‐transfer level (RTL)

what your circuit will look like –  Don’t need to worry about the gate-‐level details…this is what the synthesis tool is good at

–  You should be able to predict how many flip-‐flops your circuit will have (check the report from the CAD tool)

–  If there are more than you expect, maybe there is some implied memory

–  WriGng spaghe{ FSM code is guaranteed to cause headaches

64

Preferred FSM Style in VHDL

65


Flip-‐flops

Clock

Q

W Z


66

ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ;

BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ;

PROCESS (Clock, Resetn) BEGIN IF Resetn = '0' THEN y_present <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ;

z <= '1' WHEN y_present = C ELSE '0' ;

END Behavior ;

Manual State Assignment

•  State assignment is done automaGcally by the CAD tool to opGmize a cost func=on –  The cost funcGon could be the number of gates and flip-‐flops

–  It could also be the number of a limited resource on the chip. For example, AND terms in a CPLD

•  Manual state assignment –  Can use VHDL constants (will work with any CAD tool) –  or, some tools such as Quartus II have their own recommended method

67

Manual State Assignment using Constants

68

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY simple IS PORT ( Clock, Resetn, w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ;

END simple ;

69

ARCHITECTURE Behavior OF simple IS SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0); CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ; CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ; CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11" ;

BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; WHEN OTHERS => y_next <= A ; END CASE ; END PROCESS ; PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN y_present <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ;

END Behavior ;

Need when using std_logic instead of a type

Quartus II method: A user-‐defined aoribute for manual state assignment.

ARCHITECTURE Behavior OF simple IS

TYPE State_TYPE IS (A, B, C) ; ATTRIBUTE ENUM_ENCODING : STRING ; ATTRIBUTE ENUM_ENCODING OF State_type : TYPE IS "00 01 11" ; SIGNAL y_present, y_next : State_type ;

BEGIN . . .

70

Mealy FSMs using VHDL

71

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mealy IS

PORT ( Clock, Resetn, w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ;

END mealy ; ARCHITECTURE Behavior OF mealy IS

TYPE State_type IS (A, B) ; SIGNAL y : State_type ;

BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ; END IF ; END PROCESS ;

PROCESS ( y, w ) BEGIN CASE y IS WHEN A => z <= '0' ; WHEN B => z <= w ; END CASE ; END PROCESS ;

END Behavior ;

SimulaGon results for the Mealy machine.

72

PotenGal Problems •  The output of a Mealy machine changes as soon as the input changes (and ajer a propagaGon delay) –  This is not a problem if the inputs are synchronized to the clock

•  What happens if the input is not synchronized to the clock? –  Erroneous pulses on the output can result – will be ignored by the circuit that uses the output as its input if it is synchronized to the same clock

–  However, if the following circuit uses a different clock this will cause big problems.

73

PotenGal problem with asynchronous inputs to a Mealy FSM. 74

Assume w changes ajer the nega=ve clock edge

A

w 0 = z 0 = ⁄

w 1 = z 1 = ⁄ B w 0 = z 0 = ⁄

Reset w 1 = z 0 = ⁄ Erroneous 50 ns pulse

Example

•  We will do an example of the complete design process

•  AddiGon of binary numbers:

75

A = an−1an−2 · · · a0B = bn−1bn−2 · · · b0

A+B

Sum = sn−1sn−2 · · · s0

Serial Adder

•  We saw parallel adder circuits – Ripple-‐carry adder – Carry-‐lookahead adder

•  These adders are fast but expensive •  If speed is not criGcal, a more area-‐efficient scheme is to add the bits a pair at a Gme

76

Mealy FSM for Serial Adder •  Add a pair of bits (one from A and one from B) in each

clock cycle –  Add a0 and b0 –  In the next clock cycle, add a1 and b1 and any carry in

from bit posiGon 0 –  ...

77

Sum A B + =

Shij register

Shij register

Adder FSM Shij register

B

a

b

s

Clock

A

State diagram for the serial adder FSM

G

00 1 ⁄

11 1 ⁄ 10 0 ⁄ 01 0 ⁄

H 10 1 ⁄ 01 1 ⁄ 00 0 ⁄

carry-in 0 = carry-in 1 =

G:H:

Reset 11 0 ⁄ ab s ⁄ ( )

78

Present Next state Output s state ab =00 01 10 11 00 01 10 11

G G G G H 0 1 1 0 H G H H H 1 0 0 1

79

Present Next state Output

state ab =00 01 10 11 00 01 10 11

y Y s

0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 1

Y = ab+ ay + by

s = a⊕ b⊕ y

Carry-‐out

Carry-‐in

Full adder

a b

s

D Q

Q

carry-out

Clock

Reset

Y y

80

Moore FSM

•  In states G and H of the Mealy machine it is possible to produce two different output depending on the valuaGon of the inputs a and b – The Moore machine must have more than 2 states

•  Split each state into two states – G à G0 and G1 (carry is 0, sum is 0/1) – H à H0 and H1 (carry is 1, sum is 0/1)

81

State diagram for the Moore-‐type serial adder FSM.

H 1 s 1 = ⁄

Reset

H 0 s 0 = ⁄

01 10 11

11

01 10

G 1 s 1 = ⁄

G 0 s 0 = ⁄

01 10 00

01

00

10

11 00

00

11

82

Present Nextstate Output state ab =00 01 10 11 s

G 0 G 0 G 1 G 1 H 0 0 G 1 G 0 G 1 G 1 H 0 1 H 0 G 1 H 0 H 0 H 1 0 H 1 G 1 H 0 H 0 H 1 1

83

Present Nextstate

state ab =00 01 10 11 Output y 2 y 1 Y 2 Y 1

s

00 0 0 01 0 1 10 0 01 0 0 01 0 1 10 1 10 0 1 10 1 0 11 0 11 0 1 10 1 0 11 1

Circuit for the Moore-‐type serial adder FSM.

Full adder

a b

D Q

Q Carry-out

Clock

Reset

D Q

Q

s

Y 2

Y 1 Sum bit

y 2

y 1

84

85

LIBRARY ieee ; USE ieee.std_logic_1164.all ; -- left-to-right shift register with parallel load and enable ENTITY shiftrne IS

GENERIC ( N : INTEGER := 4 ) ; PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; L, E, w : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END shiftrne ; ARCHITECTURE Behavior OF shiftrne IS BEGIN

PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF E = '1' THEN IF L = '1' THEN Q <= R ; ELSE Genbits: FOR i IN 0 TO N-2 LOOP Q(i) <= Q(i+1) ; END LOOP ; Q(N-1) <= w ; END IF ; END IF ; END PROCESS ;

END Behavior ;

86

1 LIBRARY ieee ; 2 USE ieee.std_logic_1164.all ; 3 ENTITY serial IS 4 GENERIC ( length : INTEGER := 8 ) ; 5 PORT ( Clock : IN STD_LOGIC ; 6 Reset : IN STD_LOGIC ; 7 A, B : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; 8 Sum : BUFFER STD_LOGIC_VECTOR(length-1 DOWNTO 0) ); 9 END serial ; 10 ARCHITECTURE Behavior OF serial IS 11 COMPONENT shiftrne 12 GENERIC ( N : INTEGER := 4 ) ; 13 PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; 14 L, E, w : IN STD_LOGIC ; 15 Clock : IN STD_LOGIC ; 16 Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; 17 END COMPONENT ;

18 SIGNAL QA, QB, Null_in : STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; 19 SIGNAL s, Low, High, Run : STD_LOGIC ; 20 SIGNAL Count : INTEGER RANGE 0 TO length ; 21 TYPE State_type IS (G, H) ; 22  SIGNAL y : State_type ;

46 WITH y SELECT 47 s <= QA(0) XOR QB(0) WHEN G, 48 NOT ( QA(0) XOR QB(0) ) WHEN H ; 49 Null_in <= (OTHERS => '0') ; 50 ShiftSum: shiftrne GENERIC MAP ( N => length ) 51 PORT MAP ( Null_in, Reset, Run, s, Clock, Sum ) ; 52 Stop: PROCESS 53 BEGIN 54 WAIT UNTIL (Clock'EVENT AND Clock = '1') ; 55 IF Reset = '1' THEN 56 Count <= length ; 57 ELSIF Run = '1' THEN 58 Count <= Count -1 ; 59 END IF ; 60 END PROCESS ; 61 Run <= '0' WHEN Count = 0 ELSE '1' ; -- stops counter and ShiftSum 62 END Behavior ;

23 BEGIN 24 Low <= '0' ; High <= '1' ; 25 ShiftA: shiftrne GENERIC MAP (N => length) 26 PORT MAP ( A, Reset, High, Low, Clock, QA ) ; 27 ShiftB: shiftrne GENERIC MAP (N => length) 28 PORT MAP ( B, Reset, High, Low, Clock, QB ) ; 29 AdderFSM: PROCESS ( Reset, Clock ) 30 BEGIN 31 IF Reset = '1' THEN 32 y <= G ; 33 ELSIF Clock'EVENT AND Clock = '1' THEN 34 CASE y IS 35 WHEN G => 36 IF QA(0) = '1' AND QB(0) = '1' THEN y <= H ; 37 ELSE y <= G ; 38 END IF ; 39 WHEN H => 40 IF QA(0) = '0' AND QB(0) = '0' THEN y <= G ; 41 ELSE y <= H ; 42 END IF ; 43 END CASE ; 44 END IF ; 45  END PROCESS AdderFSM ;

87

Adder FSM

Clock

E w L

E w L b 7 b 0

a 7 a 0

E w L

E L Q 3 Q 2 Q 1 Q 0

D 3 D 2 D 1 D 0 1 0 0 0

Counter

0 0

Reset Sum 7 Sum 0

0 1

0 1

Run

88

State MinimizaGon •  For more complex FSMs the iniGal state diagram will usually have more states than actually required –  Fewer states use fewer FFs and the combinaGonal circuits may be simpler

•  If an FSM has more than the minimum required number of states then some of the states must be equivalent to other states

•  In general, it is quite tedious to check for equivalent states –  An easier approach is to show that some states are definitely not equivalent

89

DefiniGon: Successor States •  Assume an FSM with single input w.

•  If w=0 is applied to the machine in state Si and the result is that the machine moves to state Su , then Su is a 0-‐successor of Si.

•  If w=1 is applied in the state Si and it causes the machine to move to state Sv , then Sv is a 1-‐successor of Si.

•  In general, for more than one input we refer to the successors of Si as the k-‐successors of Si , where k represents the set of all possible combinaGons (valuaGons) of the inputs

90

•  DefiniGon: Two states Si and Sj are said to be equivalent if and only if for every possible input sequence, the same output sequence will be produced regardless of whether Si or Sj is the iniGal state

•  From this definiGon, if Si and Sj are equivalent, then their corresponding k-‐successors (for all k) are also equivalent.

•  A par==on consists of one or more blocks, where each block comprises a subset of states that may be equivalent, but the states in a given block are definitely not equivalent to the states in other blocks.

91

MinimizaGon Procedure •  Start with all the states in a parGGon P1

–  assume all states are equivalent •  Form parGGon P2 by parGGoning P1 into blocks such that

the states in each block generate the same output values. –  States that generate different outputs cannot be equivalent

•  Form new parGGons by tesGng whether the k-‐successors of the states in each block are contained in one block –  Those states with k-‐successors in different blocks cannot be in one block

•  Process ends when a new parGGon is the same as the previous parGGon –  All states in one block are equivalent

92

Example P1 = (ABCDEFG)

•  Separate states with different outputs

P2 = (ABD)(CEFG)

•  Consider all 0-‐ and 1-‐successors of the states in each block. –  (ABD): 0-‐successors are (BDB) which are in the same block

in P2 . à(ABD) may be equivalent –  (ABD): 1-‐successors are (CFG) which are also in the same

block in P2 and so (ABD) should remain in one block in P3 –  (CEFG): 0-‐successors are (FFEF) which are in the same

block in P2 . –  (CEFG): 1-‐successors are (ECDG). These are not in the same

block in P2 à at least one of the states in (CEFG) is not equivalent to the others. State F must be different from C, E, and G because its 1-‐successor is D, which is in a different block than C, E, and G

P3 = (ABD)(CEG)(F)

93


A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0

Example P3 = (ABD)(CEG)(F)

•  The 0-‐successors of (ABD) are (BDB) which are all in

the same block of P3 •  The 1-‐successors of (ABD) are (CFG) which are not all

in the same block à state B cannot be equivalent to states A and D.

•  The 0-‐successors and 1-‐successors of (CEG) are (FFF) and (ECG) respecGvely. Therefore

P4 = (AD)(B)(CEG)(F)

•  Checking the 0-‐ and 1-‐successors of (AD) and (CEG) we find

P5 = (AD)(B)(CEG)(F)

•  We are done. It follows that the states in each block are equivalent.

•  (AD) à A, (CEG) à C

94


A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0

Minimized state table

Present Nextstate Output state w = 0 w = 1 z

A B C 1 B A F 1 C F C 0 F C A 0

95

Example

•  Coin-‐operated vending machine – Machine accepts nickels and dimes – 15 cents releases a piece of candy –  If 20 cents is deposited the machine does not return the change, but gives 5 cents credit and waits for a second purchase

•  Design a controller for this vending machine – Assume all signals synchronized to posiGve edge of clock

96

•  Coin receptor mechanism generates two signals: senseD and senseN – Mechanism is very slow: the sense signals are high for a large number of clock cycles

– Assume two more signals D and N that are high for one clock period on the clock edge ajer senseD and senseN are asserted

– D and N cannot be set to 1 at once

97

Signals for the vending machine.

D Q Q

sense N D Q Q Clock

N

sense N sense D

Clock

N D

(a) Timing diagram

(b) Circuit that generates N

98

S1 0 ⁄

S7 1 ⁄

DN

D N

S3 0 ⁄

S6 0 ⁄

S9 1 ⁄ S8 1 ⁄

S2 0 ⁄

S5 1 ⁄

S4 1 ⁄

DN DN

DN DN DN

DN

DN

D

D N

D N

DN

N

Reset

99

Present Next state Output state DN =00 01 10 11 z

S1 S1 S3 S2 0 S2 S2 S4 S5 0 S3 S3 S6 S7 0 S4 S1 1 S5 S3 1 S6 S6 S8 S9 0 S7 S1 1 S8 S1 1 S9 S3 1

– –

– – –

– –

– – –

– – – – – – – – –

100

Don’t cares in S4,S5,S7,S8 and S9 correspond to cases where there is no need to check D and N because the machine changes state in an amount of Gme too short for a new coin to be inserted

P1 = (S1,S2,S3,S4,S5,S6,S7,S8,S9) P2 = (S1,S2,S3,S6) (S4,S5,S7,S8,S9) P3 = (S1)(S3)(S2,S6) (S4,S5,S7,S8,S9) P4 = (S1)(S3)(S2,S6) (S4,S7,S8) (S5,S9) P5 = (S1)(S3)(S2,S6) (S4,S7,S8) (S5,S9) 101


S1 S1 S3 S2 0 S2 S2 S4 S5 0 S3 S3 S6 S7 0 S4 S1 1 S5 S3 1 S6 S6 S8 S9 0 S7 S1 1 S8 S1 1 S9 S3 1

– –

– – –

– –

– – –

– – – – – – – – –

Minimized state table


S1 S1 S3 S2 0 S2 S2 S4 S5 0 S3 S3 S2 S4 0 S4 S1 1 S5 S3 1

– – –

– – – – – –

102

Minimized state diagram

S1 0 ⁄

S5 1 ⁄

DN DN

DN

DN

DN

D

D

D

N

N

N

S3 0 ⁄

S2 ⁄ 0

S4 1 ⁄

103

Mealy-‐type FSM

S3

S2

D 0 ⁄

S1

D 1 ⁄

D 1 ⁄

N 1 ⁄

N 0 ⁄

N 0 ⁄

DN 0 ⁄

DN 0 ⁄

DN 0 ⁄

104

Fewer states, but output funcGons become more complicated

Incompletely Specified FSMs •  Not all state transiGons, outputs are specified

•  States are in the same block in a parGGon of their outputs are equal for all corresponding input valuaGons –  Assume values for the unspecified outputs

105

Present Next state Output z state w = 0 w = 1 w = 0 w = 1

A B C 0 0 B D 0 C F E 0 1 D B G 0 0 E F C 0 1 F E D 0 1 G F 0

–

–

–

–

•  In this case, assuming both outputs equal to 0 leads to a minimized FSM with 6 states

•  Assuming both outputs equal to 1 leads to a minimized FSM with 4 states

•  Also be aware that minimizing states does not necessarily lead to a simpler implementaGon – State assignment may be more important

106

w 0 =

w 1 =

w 0 =

w 1 =

w 0 =

w 1 =

w 0 =

w 1 =

w 0 =

w 1 =

w 0 =

w 1 =

w 0 =

w 1 =

w 0 =

w 1 =

A/0 B/1 C/2 D/3

E/4 F/5 G/6 H/7

Example: Modulo-‐8 Counter

•  Enable: w

107

State table for the counter.

Present Next state Output state w = 0 w = 1

A A B 0 B B C 1 C C D 2 D D E 3 E E F 4 F F G 5 G G H 6 H H A 7

108

State-‐assigned table for the counter.

Present Next state

state w = 0 w = 1 Count

y 2 y 1 y 0 Y 2 Y 1 Y 0 Y 2 Y 1 Y 0 z 2 z 1 z 0

A 000 000 001 000 B 001 001 010 001 C 010 010 011 010 D 011 011 100 011 E 100 100 101 100 F 101 101 110 101 G 110 110 111 110 H 111 111 000 111

109

Karnaugh maps for D flip-‐flops for the counter.

00 01 11 10 00

01

1

0 1

1

1

0

0

0

0

1 0

0

0

1

1

1 11

10

y 1 y 0 wy 2 00 01 11 10

00

01

0

0 0

1

1

1

1

0

1

0 1

0

0

1

1

0 11

10

y 1 y 0 wy 2

00 01 11 10 00

01

0

1 1

0

1

0

1

0

1

0 0

0

1

1

0

1 11

10

y 1 y 0 wy 2

Y 2 wy 2 y 0 y 2 y 1 y 2 w + + + y 0 y 1 y 2 =

Y 0 wy 0 wy 0 + = Y 1 wy 1 y 1 y 0 wy 0 y 1 + + =

110

111

D Q

Q

D Q

Q

Clock

y 0 w

y 1

y 2

Y 0

Y 1

Y 2

Resetn

D Q

Q

•  How can this be extended to implement larger counters?

112

D0 = Y0 = wy0 + wy0

D1 = Y1 = wy1 + y1y0 + wy0y1

D2 = Y2 = wy2 + y0y2 + y1y2 + wy0y1y2

D0 = wy0 + wy0

= w ⊕ y0

D1 = wy1 + y1y0 + wy0y1

= (w + y0)y1 + wy0y1

= wy0y1 + wy0y1

= wy0 ⊕ y1

113 Clock

Enable D Q Q

D Q Q

D Q Q

D Q Q

Q 0

Q 1

Q 2

Q 3

Output carry

ImplementaGon with J-‐K FFs

•  If a FF in state 0 is to remain in state 0 –  J = 0 and K = d (i.e. K can be either 0 or 1)

•  If a FF in state 0 is to change to state 1 –  J = 1 and K = d

•  If a FF in state 1 is to remain in state 1 –  J = d and K = 0

•  If a FF in state 1 is to change to state 0 –  J = d and K = 1

114

ExcitaGon table for the counter with JK flip-‐flops.

Present Flip-‐flop inputs

state w = 0 w = 1 Count

y 2 y 1 y 0 Y 2 Y 1 Y 0 J 2 K 2 J 1 K 1 J 0 K 0 Y 2 Y 1 Y 0 J 2 K 2 J 1 K 1 J 0 K 0 z 2 z 1 z 0

A 000 000 0d 0d 0d 001 0d 0d 1d 000 B 001 001 0d 0d d0 010 0d 1d d1 001 C 010 010 0d d0 0d 011 0d d0 1d 010 D 011 011 0d d0 d0 100 1d d1 d1 011 E 100 100 d0 0d 0d 101 d0 0d 1d 100 F 101 101 d0 0d d0 110 d0 1d d1 101 G 110 110 d0 d0 0d 111 d0 d0 1d 110 H 111 111 d0 d0 d0 000 d1 d1 d1 111

115

Circuit diagram using JK flip-‐flops.

Clock Resetn

w J Q

Q K

y 0

y 1

y 2

J Q

Q K

J Q

Q K

116

See Figure 8.66 for Karnaugh maps

Factored-‐form implementaGon of the counter.

Clock Resetn

w y 0

y 1

y 2

J Q

Q K

J Q

Q K

J Q

Q K

117

Examples

•  SecGon 8.7.5 is an example of the design of a different counter 9=(0,4,2,6,1,5,3,7,0,4,…) –  Self-‐study

•  SecGon 8.8 gives a complete design example using CAD tools of an Arbiter circuit –  Self-‐study –  Shared access to a common resource – Only one device can have access at a Gme à Only one “grant” signal g(1), g(2), or g(3) can be high at once

118

Incorrect VHDL code for the grant signals

. . . PROCESS( y ) BEGIN IF y = gnt1 THEN g(1) <= '1' ; ELSIF y = gnt2 THEN g(2) <= '1' ; ELSIF y = gnt3 THEN g(3) <= '1' ; END IF ; END PROCESS ;

END Behavior ;

119

Correct VHDL code for the grant signals

. . . PROCESS( y ) BEGIN g(1) <= '0' ; g(2) <= '0' ; g(3) <= '0' ; IF y = gnt1 THEN g(1) <= '1' ; ELSIF y = gnt2 THEN g(2) <= '1' ; ELSIF y = gnt3 THEN g(3) <= '1' ; END IF ; END PROCESS ;

END Behavior ;

120

Analysis of Synchronous SequenGal Circuits

•  Reverse of synthesis process – Outputs of the FFs represent the present state variables

–  Inputs of FFs represent the next state variables – Construct a state-‐assigned table – This leads to the state table and state diagram

121

D Q

Q

D Q

Q

Clock

Resetn

y 2

y 1

Y 2

Y 1

w

z

122

Y1 = wy1 + wy2

Y2 = wy1 + wy2

z = y1y2

Present Next State state w = 0 w = 1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 0 0 0 0 01 0 0 1 0 0 10 0 1 0 0 0 11 0 1 1 0 0 11 1

(a) State-‐assigned table

Present Next state Output state w = 0 w = 1 z A A B 0 B A C 0 C A D 0 D A D 1

(b) State table

123

Y1 = wy1 + wy2

Y2 = wy1 + wy2

z = y1y2

Sequence detector: z =1 whenever three consecuGve 1s occur on the input w

J Q

Q

Clock

Resetn

y 2

y 1

J 2

J 1 w z

K

J Q

Q K K 2

K 1

Analysis with J-‐K FFs

124

J1 = w

K1 = w + y2

J2 = wy1

K2 = w

z = y1y2

ExcitaGon table

Present Flip-‐flop inputs


y 2 y 1 J 2 K 2 J 1 K 1 J 2 K 2 J 1 K 1 z

00 01 0 1 0 0 1 1 0 01 01 0 1 1 0 1 1 0 10 01 0 1 0 0 1 0 0 11 01 0 1 1 0 1 0 1

125

J1 = w

K1 = w + y2

J2 = wy1

K2 = w

z = y1y2

•  If a FF in state 0 is to remain in state 0 –  J = 0 and K = d (i.e. K can be either 0 or 1)

•  If a FF in state 0 is to change to state 1 –  J = 1 and K = d

•  If a FF in state 1 is to remain in state 1 –  J = d and K = 0

•  If a FF in state 1 is to change to state 0 –  J = d and K = 1

Present Next State state w = 0 w = 1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 0 0 0 0 01 0 0 1 0 0 10 0 1 0 0 0 11 0 1 1 0 0 11 1

State-‐assigned table e.g. y2y1 = 00 and w = 0 J2 = J1 = 0, K2 = K1 = 1 à both FFs remain in state 0 à Y2 = Y1 = 0

e.g. y2y1 = 00 and w = 1 J2 = 0, K2 = 0, J1 = 1, K1 = 1 à Y2 = 0 à Y1 = 1

Same state table as previous example

Algorithmic State Machine Charts

•  State diagrams and tables become inconvenient for more complex circuits – ASM charts are flowcharts used to represent state transiGons and outputs for an FSM

•  Unlike a tradiGonal flowchart, the ASM chart contains Gming informaGon –  Implicitly specifies that the FSM changes (flows) from one state to another only ajer each acGve clock edge

126

Figure 8.86. Elements used in ASM charts.

Output signals or acGons

(Moore type)

State name

CondiGon expression

0 (False) 1 (True)

CondiGonal outputs or acGons (Mealy type)

(a) State box (b) Decision box

(c) CondiGonal output box

127

Sufficient to only list the name of the signal to be asserted as 1

Can contain more complex expressions such as Count ß count + 1

128

w

w

w 0 1

0 1

0 1

A

B

C z

Reset

C z 1 = ⁄

Reset

B z 0 = ⁄ A z 0 = ⁄ w 0 =

w 1 =

w 1 =

w 0 =

w 0 = w 1 =

w

w 0 1

0

1

A

B

Reset

z

129

A

w 0 = z 0 = ⁄

w 1 = z 1 = ⁄ B w 0 = z 0 = ⁄

Reset w 1 = z 0 = ⁄


Y k

Y 1

y k

y 1

w 1

w n

z 1

z m Outputs

Next-state variables

Present-state variables

Inputs

General Model for a SequenGal Circuit

•  Synchronous circuits: delay elements are flip-‐flops which change their state on the acGve edge of a clock signal. The delay is determined by the clock period: must be long enough to allow for propagaGon delay in the combinaGonal circuit plus setup and hold Gmes of the flip-‐flops

•  Asynchronous circuits: the delays are due solely to the propagaGon delays through various gates 130

Finite State Machines

Documents

state fncurrent state

state w

state inputs

state diagram

state logic

state assignment

stargng state

state labels