02 LPD PowerConsumptionBasics (1)

7/26/2019 02 LPD PowerConsumptionBasics (1)

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ce

[email protected]

Universidad Politcnica de Madrid

ower m n gement for electronic

systems

low power design

Pedro Alou ([email protected] )

Teresa Riesgo ([email protected])
mailto:[email protected]:[email protected]:[email protected]:[email protected]


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2

Power management of electronic systems

Outline

of the

course

Introduction Structure of the subject

Evolution of power consumption in digital systems Power consumption basics

How an electronic system consumes power CMOS technology

Challenges in technology scaling and in (low) power supplies

Optimizing power in digital systems Low power design techniques at different levels (circuit, logic, RTL, system)

Optimizing power at run time

Power estimation Dynamic and static techniques

Different abstraction levels

Power sources Battery powered devices

Energy harvesting

Low power supplies and converters Voltage regulators

Dynamic Voltage Scaling


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3


Before

starting

metrics


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4


Is

power

consumption

so

important

?


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5


Why

CMOS?

Design and process experience

Availability of manufacturing places

Lowest Price per function

Low power consumption

Vdd scalability

High scalability with current lithographic processes

Easy layout

Capability of integrating analog/digital/memory/sensors in chip


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Why

CMOS


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CMOS Technologya review

pMOS

Se activa con un 0 en la G

Conduce bien los 1s

G

D

S

D S

G = 1

D S

G = 0

nMOS

G

D

S

Se activa con un 1 en la G

Conduce bien los 0s

D S

G = 0

D S

G = 1

1 = VDD

0 = GND

VDD

GND

A

A

B

B

S

NAND? NOR?

GND

A

A

B

B

S

NAND? NOR?

VDD

VDD

GND

A S

A S

nMOS

pMOS

Si A = 1 (A=VDD) nMOS conduce,

pMOS no conduce S = 0 (S=GND)

Si A = 0 (A=GND) nMOS no conduce,

pMOS conduce

S = 1 (S=VDD)


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TheMOS transistors

VGSVT

Ron

S D

A Switch!

|VGS |

A MOS Transistor


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Current-Voltage relations

Long channel device


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Current-Voltage relations(Deep submicronMOS)-4

VDS(V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

ID(A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Early Saturation

Linear

Relationship

ID

Long-channel device

Short-channel device

VDS

VDSAT

VGS

- VT

VGS

= VDD


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TheCMOS Inverter

VDD

GND

Vin Vout

nMOS

pMOS

GND

CL

VDD VDD

Vin =

VDD

Vin =

0

Vout

Vout

Rn

Rp

Vout

R p

V DD

Vin = 0

(a) Low-to-high

C L

V out

R n

V DD

V in = V DD

(b) High-to-low

C L

Transient analysis

DC analysis


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CMOS InverterLoad Characteristics

IDn

Vout

Vin= 2.5

Vin

= 2

Vin

= 1.5

Vin

= 0

Vin

= 0.5

Vin

= 1

NMOS

Vin= 0

Vin

= 0.5

Vin= 1Vin

= 1.5

Vin= 2

Vin

= 2.5

Vin= 1Vin= 1.5

PMOS

VDD

GND

Vin Vout

nMOS

pMOS

GND

CL


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CMOS Invertervoltagetransfer

Vout

Vin0.5 1 1.5 2 2.5

0.

5

1

1.

5

2

2.

5

NMOS res

PMOS off

NMOS sat

PMOS sat

NMOS off

PMOS res

NMOS satPMOS res

NMOS res

PMOS sat

VOH

VOLVin

Vout

VM

VIL VIH

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin

(V)

V

out(

V)

Good PMOS

Bad NMOS

Good NMOS

Bad PMOS

Nominal =0

=0

+

= dielectric constants= carrier mobility

W= Channel width

L= Channel Length


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CMOS Invertervoltagetransfer

=

_(e-)W_n/L_n

=0

+

= dielectric constants

= carrier mobility

W= Channel width

L= Channel Length

Inversion voltage = Vdd/2=

=+

/

/=

+ 2,5Electron mobility: e-=650 cm

2/V.seg

Hole mobility: h+=240 cm2/V.seg

pMOS transistor must be 2.5 times larger (wider) than nMOS


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Power consumption in CMOS circuits

Leakage consumption

Parasitic diodes and transistors

Dynamic consumption

Charge and discharge of capacitors

Pdyn = CLVDDVswf0110

Psc = VDDIsc

Pstat = VDDIleak

Short circuit consumption

Short circuit path between Vdd and

Gnd during the transitions

80% Ptotal

10-20% Ptotal

1-10% Ptotal

VDD

In Out

CL

ISC

Inverter

CMOS

Its importance increases in deep submicron technologies


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CMOS invertercurrents

Energy/transition = C L * V dd2

Power = Energy/transition * f = C L * V dd2 * f

Need to reduce C L , V dd, and f to reduce power.

Vin Vout

C L

Vdd

Not a function of transistor sizes!

The power consumption

depends on the

switching activity and,

therefore, on the

patterns and data

handled by the circuit

Estimation is

not easy!


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CMOS: DynamicPowerConsumption


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CMOS: DynamicPowerConsumption


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Short-circuitcurrents

Vin Vout

C L

Vdd

IVDD

(m

A)

0.15

0.10

0.05

Vin

(V)

5.04.03.02.01.00.0

pMOS

nMOS

Vin= 0V

pMOS

Idd = 0A

ON

nMOS OFF

Vin= 5V

pMOS

Idd = 0A

OFF

nMOS ON

Vin= 2,5VpMOS

Idd 0A

ON

nMOS ON


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Riseandfalltimes

Influence in the short-circuit current

VDD

Vout

CL

Vin

ISC 0

VDD

Vout

CL

Vin

ISCIMAX

Large Loads CL Small Loads CL


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Short-circuitpower


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Riseandfalltimes

Influence in the short-circuit current

0r

8

76

5

43

2

1

01 2 3 4 5

DE / E

VDD = 5 V

VDD = 3.3 V

W/L|P = 7.2mm/1.2mm

W/L|N = 2.4mm/1.2mm

The power consumption due to short circuit current is minimized by

choosing the aspect ratio between pMOS and nMOS transistors


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Vout

Vdd

Sub-ThresholdCurrent

Drain JunctionLeakage

Sub-Threshold Current Dominant Factor

Staticconsumption(leakage)


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Sub-thresholdleakage(anextra complication)


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Staticpower(leakage) mayruin Moores Law


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Projections


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PowerBudgetfordifferenttypeof SoCs


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SupplyVoltages: evolution

02 LPD PowerConsumptionBasics (1)

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