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Kwang-Ting (Tim) Cheng– PhD, 1988, Univ. of California, Berkeley– 1988-1993: AT&T Bell Labs– 1993-Present: Professor, Dept. of ECE, Univ. of California,
Santa Barbara– 1999-2002: Director, Computer Engineering Program, UCSB– 2005-2008: Chair, Dept. of ECE, UCSB– July-Dec. 2008: Visiting Professor, Univ. of Tokyo– Research areas: VLSI test, validation and verification;
multimedia computing (image and video content analysis)
UCSB’s SoC Design and Test LabResearch directions:– Test techniques for heterogeneous SOC– Functional and timing verification– Post-silicon debug and validation
Current projects:– Models and coverage metrics for effective post-silicon validation– Low-cost on-line checking for consumer electronics– Self-test and error resilience for high-speed IO and RF systems – Test, yield and reliability analysis for multi-core systems with
Verifies correctness of design.Performed by simulation, hardware emulation, or formal methods.Performed once prior to manufacturing.Responsible for quality of design.
Verifies correctness of manufactured hardware.Two-part process:– 1. Test generation: software
process executed once during design
– 2. Test application: electrical tests applied to hardware
Test application performed on every manufactured device.Responsible for quality of devices. *from M. Bushnell/V. Agrawal
Based on analyzable fault models, which may not map on real defects.Incomplete coverage of modeled faults due to high complexity.Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss.Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.
Types of TestingCharacterization testing, or design debug– Verifies correctness of design & of test procedure – data will be used for final spec.– data can be used to identify area in which
processing can be helped for increased yield– test time is not important
Manufacturing testing/Production testing– Factory testing of all manufactured chips for
parametric faults and for random defects
Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000
Characterization TestWorst-case test– Choose test that passes/fails chips– Select statistically significant sample of chips– Repeat test for every combination of 2+
environmental variables– Plot results in Shmoo plot– Diagnose and correct design errors
Continue throughout production life of chips to improve design and process to increase yield
Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000
Provides the primary electrical contact between the tester and each device-under-test (DUT) on the wafer“Needles” on the probe card contact the device I/O pads on the die (same pads are used for package interconnects; often called bond pads)There is usually a different, custom probe card for every circuit designThe cards are delicate and fragile
Correlations have been made between life span at room temperature & life span at elevated temperature.Charts of these correlations have been made for each technologyPut the device in a furnace for a certain length of time at an elevated temperature and voltage– By applying high voltage to the IC’s pins, burn-in accelerates
the time-to-failure of oxide defects (weak oxide, pin holes, uneven layer growth, etc) typically found in MOS devices
– High temperature accelerates these and other defects, such as ionic contamination and silicon defects
Tests are done by Parametric Measurement Unit (PMU)– Leakage test– Threshold ViL & ViH test– Output drive current test– Power consumption test– Output short current test
AC Parametric TestingTo ensure that value/state changes occur at the right time Some of AC parametric tests are mainly for characterization and may not be necessary for production test.– Test for rise and fall times of an output signal– Tests for setup and hold times– Tests for time to tri-state– Tests for measuring delay times
» E.g. tests for memory access time– Functional at-speed tests (speed sorting)
Final test in the manufacturing processChecking the right assembly of components such as boards, backplanes, cables and peripheralsIt also involves checking of component interactions and HW/SW functionalityVery long test times required
Field TestingNecessary for commissioning and fault-finding the system as a whole in a field-service environmentBoth analog and digital test equipment is needed, issues of– Portability– Ease of use– Range of functions
Testing Costs are Composed of:Test equipment costs– Analog & digital signal and measuring instrumentation– Test head (pin electronics, drivers and cables)– Test controller (computer & storage)
Test development costs– Test planning, test program development and
debuggingTesting-time costs– time using the equipment to support testing
Characterization testing vs. Production testingProduction testing: Wafer probe vs. Packaged device testingProduction testing for packaged devices:– Contact test– Burn-in– Functional testing– DC & AC parametric testing
Xbox:16.4% failure rateAdditional warranty and refund will cost Microsoft $1.15B ($86 per $300-item)More than financial cost: reputation and market lossNon-trivial failure rate– 15% in average