© H. Heck 2008Section 5.21 Module 5:Advanced Transmission Lines Topic 2: Intersymbol Interference OGI EE564 Howard Heck.

© H. Heck 2008 Section 5.2 1

Module 5: Advanced Transmission LinesTopic 2: Intersymbol Interference

OGI EE564

Howard Heck

© H. Heck 2008 Section 5.2 2

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64 Where Are We?

1. Introduction

2. Transmission Line Basics

3. Analysis Tools

4. Metrics & Methodology

5. Advanced Transmission Lines1. Losses

2. Intersymbol Interference (ISI)

3. Crosstalk

4. Frequency Domain Analysis

5. 2 Port Networks & S-Parameters

6. Multi-Gb/s Signaling

7. Special Topics

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64 Contents

Introduction How ISI impacts timings ISI Causes Minimization Techniques Summary References

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64 Introduction

The plot above is an “eye” diagram of a single interconnect net over multiple cycles. What is going on? The network is not perfectly matched. The line is not at a “steady” state when the next transition occurs. Residual wave component from the previous transition is present on

the line when the next transition launches a new wave. The residual affects the starting voltage for the next transition. So, the network behavior for a given transition is affected by it history.

-0.75

0.00

0.75

1.50

2.25

0 2 4 6

time [ns]

volt

age

[V]

ISI = cycle-cycle variationISI = cycle-cycle variation

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64 ISI Performance Impacts

ISI seems like it should be a small effect. However, at 266 MT/s the AGP 4X bus had an interconnect skew budget of 550 ps.

0.0 7.5 15.0 22.5

time [ns]

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0.0

0.5

1.0

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2.0

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]

3.55 3.63 3.71 3.77 3.77

Here’s a real example from AGP-4X that shows the effect of ISI for a simple case. The waveform shows 220 ps of uncertainty due to ISI. ISI took up about 300 ps of the AGP4X budget.

800 MT/s RDRAM had 125 ps for the entire interconnect budget.

Above 1 GHz, ISI dominates the interconnect response.

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64 ISI Causes

This AGP4X data accounts for the following: Data signals normalized to account for cycle-cycle strobe variation. Crosstalk for a 5 mil/15 mil space/trace in a microstrip PCB structure. 1 pF capacitance variation between different signals. The following data pattern:

Eye Diagram Created From QUAD Simulations

Setup Margin: Margin = TDVB - TSU_SKEW - TSU

Margin = T1 + TDVB - TSU - 1.875

T1 = 1.875 - TSU_SKEW T2 = 1.875 + TH_SKEW ( TH_SKEW is negative)

Hold Margin: Margin = TDVA - TH_SKEW - TH

Margin = T2 - TDVA - TH - 1.875

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1.01ns 1.135ns

0 0 01 000 0 0 01 1 1 1 1 11111111 1 00000000

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64 ISI Causes #2

Losses also cause ISI:

TransmittedTransmittedSignalSignal

ReceivedReceivedSignalSignal

Examining the effect at the receiver:

Losses causes the falling edge to occur at different voltage levels, depending on the data pattern. This adds jitter.

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64 ISI Minimization

Terminate the network. Design all elements for matched impedance.

PCB, packages, connectors, termination resistors Use controlled impedance PCBs.

±15% or better Design for minimized crosstalk.

We’ll cover this later, but crosstalk alters Z0, depending on the switching activity of neighboring lines.

Eliminate transmission line stubs. Point-point networks are fastest, though not always possible

(memory bus). Terminate on-die.

Reduce losses. Use “equalized” transmitters & receivers to compensate

for losses.

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64 Another Look – Sub 1 Gb/s Signaling

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time [ns]

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V]

In this case, ISI is dominated by impedance mismatch.

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64 Multi-Gb/s Signaling

At Multi-Gb/s speeds , ISI is often dominated by losses.

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64 Summary

Intersymbol interference is a cycle-cycle interaction that is caused by losses and/or imperfect matching of the transmission line network.

ISI effects are large relative to the shrinking budgets of contemporary high speed designs.

Anything that affects the matching of the line will increase the timing impact of ISI.

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64 References

S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience), 2000, 1st edition.

W. Dally and J. Poulton, Digital Systems Engineering, Chapters 4.3 & 11, Cambridge University Press, 1998.