شيت دمحمددسوقى

SUMMARY COMBINATIONAL LOGIC CIRCUITS LECT1

Q1-What are the three basic Binary Logic operatios , their truth

tables , and their logic diagrames

three basic logical operations called AND, OR, and NOT:

when (X,Y,Z are binary variables equal 1 or 0)

AND Z = X • Y is called Z equal X AND Y

OR. Z = X + Y is called Z equal X OR Y

NOT. Z = is called Z equal NOT X

The truth tables for the operations are shown in following Table

Logic Gat diagrames:

Q2- what is the Boolean algebra with example

1

The Boolean algebra is an algebra dealing with binary variables and logic

operations as example the function F is afunction in logic variables

X,Y,Z.

A Boolean function can be represented by a truth table.

The truth table for the logic operation is number of rows in a truth table is

2n, where n is the number of variables in the function. The binary

combinations for the truth table are the n-bit binary numbers that

correspond to counting in decimal from 0 through 2n – 1, the logic

diagrame for the function as following.

SUMMARY COMBINATIONAL LOGIC CIRCUITS LECT2

Q3- what are Basic Identities of Boolean algebra

2

Basic Identities of Boolean algebra are:

Examples:

1. X+XY=X(1+Y)=X

2.

3.

more examples:

4.

5.

6.

Q4- what are meant by Dual, and its dual Boolean expressions?

The dual expression is change the OR to AND and AND to OR

XY to X+Y

X+Y to XY

The consensus theorem

3

The theorem shows that the third terrm, YZ, is redundant and can be eliminated. Note that Y and Z are associated with X and in the first two terms and appear together in the term that is eliminated. The dual of the consensus theorem is

Q5- draw the logic diagram for the following function , and using the

Boolean algebra to simplify it , then draw the simplified logic

diagram for the simplified function with truth table check for

two function

The three terms in the expression are implemented with three AND gates,

,one OR, and two NOT.

Now consider a simplification of the expression for F by

applying Boolean algebra:

Truth table for function check a, and b:

4

Q6- what is the Demorgan’s theorem, using it to complement the Functions:

The the Demorgan’s theorem for complement the expressions are:

Q7- Find the complements of thru function in example 1-1 by taking the duals of the equations and complementing each literal.

5

SUMMARY COMBINATIONAL LOGIC CIRCUITS LECT3Q8- what are the Minterms and Maxterms

a- Minterms: A product term in which all the variables appear exactly once,

either complemented or uncomplemented, is called a minterm.

b- Maxterms: A sum term that contains all the variables in

complemented or uncomplemented form is called a maxterm.

6

Note from Tables a minterm and maxterm with the same subscript are the

complements of each other; that is, Mi = .

Q9- represents the following logic function with minterm and maxterm from

a given truth table:

By examining the truth tables for these minterms it is evident that the function F

can be expressed algebraically as the logical sum of the stated minterms:

Boolean Function of Three Variables can be further abbreviated by listing only

the decimal subscripts of the minterms:

7

Note that if the function contains all minterms, it is equal to 1.

F by maxterm:

This shows the procedure for expressing a Boolean function as a product of maxterms. The abbreviated form for this product is

Q10- draw the logic diagram for the following functions using Sum of Products, and Product of sum:

a-Sum of Products An example of logical a Boolean function expressed as a sum of products is

The AND gates followed by the OR gate form a circuit configuration referred to as a two-level implementation .

If the expression not in the standard form of sum of product, the expression can be converted to a sum of products by applying the appropriate distributive law as follows:F = AB + C(D + E) = AB + CD +CEThe function F is implemented in a nonstandard form in Figure 1-6(a).

This requires two AND gates and two OR gates. There are three levels of

gating in the circuit. F is implemented in sum-of-products form in Figure

1-6(b).

8

b- Product of Sums

This expression has sum terms of one, two, and three literals. The sum terms

perform an OR operation, and the product is an AND operation.

SUMMARY COMBINATIONAL LOGIC CIRCUITS LECT4,5

Q11-draw the Karnaug map (K-map) for two, three, and four variables for Simplifying a Boolean Function :

a-Two-Variable Map

There are four minterms

9

Figure 1-9(b) shows the map for the logical sum of three minterms:

The optimized expression X + Y is determined from the two-square area

for the variable X in the second row and the two-square area for Y in the

second column.

b- Three-Variable Map

The characteristic of the listed sequence is that only one bit changes in

value from one adjacent column to the next, which corresponds to the

Gray code.

In general, Three-variable maps exhibit the following characteristics:

One square represents a minterm of three literals.

A rectangle of two squares represents a product term of two literals.

A rectangle of four squares represents a product term of one literal.

10

A rectangle of eight squares produces a function that is always equal to

logic 1 as in the following figures:

c- Four-Variable Map

There are 16 minterms for four binary variables, and therefore, a four-variable map consists of 16 squares, as shown :

The combinations of squares that can be chosen during the optimization

process in the four-variable map are as follows:

One square represents a minterm of four literals.

A rectangle of 2 squares represents a product term of three literals.

A rectangle of 4 squares represents a product term of two literals.

A rectangle of 8 squares represents a product term of one literal.

A rectangle of 16 squares produces a function that is always equal to logic 1.

Q12- Simplifying a Boolean Function Using a K-Map

1-Fill K- map with minterms

11

2- The optimized expression for F:

Q13- Simplifying a Boolean Function Using a K-Map

F1(X,Y.Z) = Sm(3.4,6,7)

F2 (X,Y,Z) = Sw(0,2,4,5.6)

The map for F1 is shown in Figure 1-13(a). There are four squares marked

with 1's, one for each minterm of the function. Two adjacent squares are

combined in the third column to give a two-literal term YZ. The

remaining two squares with 1's are also adjacent by the cylinder-based

definition and are shown in the diagram with their values enclosed in half

rectangles. When combined, these two squares give the two-literal term

.The optimized function thus becomes

12

And with the same procedures

Q14- Simplify the following two Boolean functions

F1(X,Y.Z) = m(1,3.4,5,6)

F2 (X,Y,Z) = m(1,2,3,5.7)

As in the fig1.14a the minterms 1, and 3 give the term , minterms 4, and 6 give term . The minterm 5 can be combined with the minterm 4 to give or minterm 1 to give so :

F1(X,Y.Z) = m(1,3.4,5,6) = + +

For the F2 as in fig.2.14b the minterms 1,3,4,7 combined and give the term Z, the minterm 2 combined with minterm 3 to give the term

F2 (X,Y,Z) = m(1,2,3,5.7) = Z +

Q15- Simplifying a 4-Variable Function with a Map

F(W,X,Y,Z) = m(0,l,2,4,5,6,8,9,10,12,13)

13

As in the fig. minterms 0, 1,4, 5, 8, 9, 12, 13 the eight minterms

combined to give the term .The remaining term 2,6,14. The 6, 14,

combined with 4, 12 to give X , and 2,6 combined with 0,4 to give term

so F simplified as:

F= + X +

Q16- Simplifying a 4- Variable Function with a Map

As in the fig. minterms 0, 1,8,9 the four minterms combined to give the term .The remaining term 2,6,10. The 2,10 combined with 0,8 to give

, and 6 combined with 2 to give term so F simplified as:

F= + +

Q17- Simplifying a 4- Variable Function with a Map using

don’t care condition:

14

Consider the following incompletely specified function F that has three

don't-care minterms d:

F(A,B,C,D) = m(l,3,7,11,15)

d(A,B,C,D) = m(0,2,5)

As in the next fig.a the don't care is signed by x sign. The minterms 3, 7,

11, 15 are combined to give term CD the remaining minterm 1, 2 is

combined with don't care minterm 0,3 to give term

So the simplified F function is as:

F= CD+

As in fig.b minterms 3, 7, 11, 15 combine to give CD, minterms 1,3,7

combined with don't care minterm 5 to give

Q18- explain exclusive-or, and exclusive-NOR with gates

The exclusive-OR (XOR), denoted by , is a logical operation that

performs the function

It is equal to 1 if exactly one input variable is equal to l.

The exclusive-NOR, also known as the equivalence, is the complement of

the exclusive-OR and is expressed by the function

15

It is equal to 1 if both X and Y are equal to 1 or if both are equal to 0.

for more than two vari ables

The exclusive-OR is replaced by the odd function; there is no symbol for

exclusive-OR for more than two inputs.

By duality, the exclu sive-NOR is replaced by the even function and has

no symbol for more than two inputs.

Q18- explain Odd Function, and even function

Odd Function

The exclusive-OR operation with three or more variables can be

converted into an ordinary Boolean function by replacing the symbol

with its equivalent Boolean expression as follows:

The Boolean expression clearly indicates that the three-variable

exclusive-OR is equal to 1 if only one variable is equal to 1 or if all three

variables are equal to 1. Hence, whereas in the two-variable function

only one variable need be equal to 1, with three or more variables an odd

number of variables must be equal to 1.

16

Next Figure(a) shows the map for the three-variable odd function. The

four-variable case is shown in Figure (b).

The odd function is implemented by means of two-input exclusive-OR

gates, as shown in the next fig.

b-even function

It should be mentioned that the minterms not marked with 1's in the map

have an even number of 1's and constitute the complement of the odd

function, called the even function.

The even function is obtained by replacing the output gate with an

exclusive-NOR gate.

17

Q19-draw The symbols, truth tables, and function for different types of gates

First year computer science

Introduction to Computer Organization

CHAPTER TWO

18

ARITHMETIC FUNCTIONS AND CIRCUITS

LEC. 6,7

2-1 Binary adders

An arithmetic circuit is a combinational circuit that performs arithmetic

operation? Such as addition, subtraction, multiplication, and division with

binary numbers or with decimal numbers in a binary code. We will

develop arithmetic circuits by means of hierarchical, iterative design. We

begin at the lowest level by finding a circuit that performs the addition of

two binary digits. This simple addition consists of four possible

elementary 0 +0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1 + 1 = 10. The first three

operations produce a sum requiring only one bit to represent it, but

when both the augend and addend are equal to 1, the binary sum

requires two bits. Because of this case, the result is always

represented by two bits, the carry and the sum. The carry

obtained from the addition of two bits is added to the next

higher order pair of significant bits.

A combinational circuit that performs the addition of two bits is

called a half adder.

One that performs the addition of three bits (two significant bits

and a previous carry) is called a full adder.

The names of the circuits stem from the fact that two half

adders can be employed to implement a full adder. The half

adder and the full adder are basic arithmetic blocks with which

other arithmetic circuits are designed.

Half Adder

19

A half adder is an arithmetic circuit that generates the sum of two

binary digits. The circuit has two inputs and two outputs. The input

variables are the augend and addend bits to be added, and the

output variables produce the sum and carry. We assign the symbols

X and Y to the two inputs and S(for "sum") and C (for "carry") to

the outputs. The truth table for the half adder is listed in Table 3-1.

The C output is 1 only when both inputs are l. The S output

represents the least significant bit of the sum.

table 2.1

The Boolean functions for the two outputs, easily obtained from

the truth table, are:

20

The half adder can be implemented with one exclusive-OR gate

and one AND gate, as shown in fig.2.1

Figure 2-1 Logic Diagram of Half Adder

Full Adder

A full adder is a combinational circuit that forms arithmetic sum

off three input bits. Besides the three inputs it has two ouputs.

Two of the inputs are denoted by X and Y, represent the two

significant bits to be added . the third input Z represents the

carry from the previous lower significant position.the two output

are designated by symbols S for sum, and C for carry as in table

3.2.the S is equal to 1 when only one input equal to one or when

all three inputs are equal to one.the carry is 1 if two input equal

1 or three inputs equal 1.

Truth table 2.2

21

The simplified sum of of product functions for the two output are:

The Boolean function for full adder in terms of exlusive OR

operation can be expressed as:

The maps as in fig.2.2 , and the logic diagram as in fig.2.3.

22

Fig. 2.2 maps for full adder

Fig. 2.3 logic diagram full adder

Binary Ripple Carry Adder

A parallel binary adder is a digital circuit that produces the arithmetic

sum of two binary numbers using only combinational logic. The parallel

adder uses n full adders in parallel, with all input bits applied

simultaneously to produce the sum. The full adders are connected in

cascade, with the carry output from one full adder connected to the carry

input of the next full adder Since a 1 carry may appear near the least

significant bit of the adder and yet propagate through many full adders to

the most significant bit, just as a wave ripples outward from a pebble

dropped in a pond, the parallel adder is referred to as a ripple carry adder

23

Figure 2-4 shows the interconnection of four full-adder blocks to form a

4-bit ripple carry adder. The augend bits of A and the addend bits of B are

designated by subscripts in increasing order from right to left, with

subscript 0 denoting the least significant bit. The carries are connected in

a chain through the full adders. The input carry to the parallel adder is C0,

and the output carry is C4. An n-bit ripple carry adder requires n full

adders, with each output carry connected to the input carry of the next-

higher-order full adder.

FIGURF 2-4 4bit Ripple carry Adder

For example, consider the two binary numbers A = 1011 and B = 0011.

Their sum, S = 1110, is formed with a 4-bit ripple carry adder as follows:

24

2-2 Binary subtraction

2-2-1 binary adder-subtractors

The circuit for subtracting A - B consists of a parallel adder as

shown in Figure 2-4, with inverters placed between each B

terminal and the corresponding full-adder input. The input carry

C0 must be equal to l.The operation that is performed becomes A

plus the 1's complement of B plus 1. This is equal to A plus the

2's complement of B. For unsigned numbers, it gives A - B if A

>B or the 2's complement of (B – A) if A< B.

The addition and subtraction operations can be combined into

one circuit with one common binary adder. This is done by

including an exclusive-OR gate with each full adder. A 4-bit

adder-subtractor circuit is shown in Figure 2-5. Input S controls

the operation. When S=0 the circuit is an adder, and when S = 1

the circuit becomes a subtracter. Each exclusive-OR gate

receives input S and one of the inputs of B, Bi . When S = 0, we

have Bi 0. If the full adders receive the value of B. and the input

25

carry is 0, the circuit performs A plus B. When S = 1, we have Bi

1 = and C0 = 1. In this case, the circuit performs the

operation A plus the 2's complement of B.

Fig.2.5 adder subtractor circuit

Signed Binary Numbers

The convention is to make the sign bit 0 for positive numbers, 1

for negative numbers. If the binary number is signed, then the

leftmost represents the sign and the rest of the bits represent the

number. If the binary number is assumed to be unsigned, then

the leftmost bit is the most significant bit of number. Table 2.3

show the signed binary numbers

26

Table 2-3

Signed Binary Addition and Subtraction

If tne number is negative we replaced by the 2's complement,

and then add, if the most significant bit is zero the result value is

positive valu. If the most significant bit is 1 the result is negative

ant is in the 2's complement form, to get the exact value we get

its complement.

Example:

Note that in the case of unsigned number the negative number replaced

by its complement, and then add, if there is carry it's ignored and the

27

result is positive. if there is no carry the result is negative , and the result

is in complemt value , if we need the exact value replace the result by its

complement valus.

Overflow

To obtain a correct answer when adding and subtracting, we must ensure

that the result has a sufficient number of bits to accommodate the sum. If

we start with two n-bit numbers, and the sum occupies n + 1 bits, we say

that an overflow occurs.

Example:

Note that the 8-bit result that should have been positive has a

negative sign bit and that the 8-bit result that should have been

negative has a positive sign bit. If, however, the carry out of the

sign bit position is taken as the sign bit of the result, then the 9-

bit answer so obtained will be correct. But since there is no

position in ilic result for the 9th bit, we say that an overflow has

occurred.

2-3 BINARY MULTIPLICATION

Multiplication of binary numbers is performed in the same way

as with decimal numbers. The multiplicand is multiplied by each

bit of the multiplier, starting from the least significant bit. Each

28

such multiplication forms a partial product. Successive partial

products are shifted one bit to the left. The final product is

obtained from the sum of the partial products.

To see how a binary multiplier can be implemented with a

combinational circuit, consider the multiplication of two 2-bit

numbers, as shown in Figure 2-6. The multiplicand bits are B0

and B1, the multiplier bits are A1 and A0, and the product is

C3C2C1C0 as in figure 2-6.

Fig.2.6 2 bit binary multiplierExample Multiply binary number 1 0 1, and 010

01 x 10 0 0 0 1 0 0 0 0 1 0

29

CHAPTER Three

SEQUENTIAL

CIRCUITS

LEC. 8,9

3.1 sequential circuits

To this point, we have studied only combinational logic.

In order to perform useful or flexible sequences of

operations, we need to be able to construct circuits that

can store information between the operations. Such

circuits are called sequential circuits.

A block diagram of a sequential circuit is shown in

Figure 3-1. A combinational circuit and storage elements

are interconnected to form the sequential circuit. The

sequential circuit receives binary information from its

environment via the inputs. These inputs, together with

the present state of the storage elements to determine

the binary value of the outputs and the storage element

next state.

The storage elements used in clocked sequential circuits

that called flip –flops. A flip –flop is a binary storage device

30

Figure 3.1 block diagram of a sequential circuit

Figure 3.2 synchronous clocked circuit

capable of storing one bit of information and having timing

characteristics. The block diagram of a synchronous

clocked sequential circuit is shown in Figure 3-2.

The flip – flops receive their inputs from the combinational

circuit and also from a clock signal with pulses that occur

at fixed intervals of time.

3.2 Latches

A storage element can maintain a binary state indefinitely

until directed by an input signal to switch states .

3.2.1 SR Latches The latch has two inputs, labeled S for set and R for reset,

and two useful states When output Q=1 =1and Q =0, the

latch is said to be in the set state. When =0 and Q=1, it

is in the reset state. Outputs Q and are normally the

complements of each other. When both inputs are equal to

1 at the same time, an undefined state with both outputs

equal to 0 occurs as in figure 3.3.

31

Figure 3.3 SR Latch with NOR gates

In normal operation these problems area avoided by

making sure that 1's are not applied to both inputs

simultaneously. The behavior of the SR latch described in

the preceding paragraph is illustrated by the logic

simulator waveforms shown in Figure 3.4 Initially.

Figure 3-4 logic simulation of SR latch behaviour

32

Figure 3.5 Latch with nand gates

Figure 3.6 SR Latch with control

The SR latch with two cross –coupled NAND gates is shown in Figure

3.5. It operates with both inputs normally at 1, unless the state of the latch

has to be changed. The application of a 0 to the S input causes output Q

to go to1.putting the latch in the set state. When the S input goes back to

1, the circuit remains in the set state with both inputs at 1. The state if the

latch is changed by placing a 0 on the R input. This causes the circuit to

go to the reset state and stay there even after both inputs return to 1. The

condition that is undefined for this NAND latch is when both inputs are

equal to 0 at the same time, an input combination that should be avoided.

The operation of the basic NOR and NAND latches can be modified

by providing an additional control input that determines when the state of

the latch can be changed. An SR latch with a control input is shown in

Figure 3.6. It consists of the

33

Figure 1.8D latch with transmition gates

Figure 3.8D latch with transmition gates

The D latch in VLSI circuits is often constructed with transmission gates

(TGs). As shown in Figure -3.8. The C input controls two TGs. When

C=1, the TG connected to input D conducts, and the TG connected to

output Q disconnects .this produces a path from input D through two

Inverters to output Q, thus, the output follows the data input as long as c

remains active (1). When C changes to 0, the first TG disconnects input D

from the circuit and the second TG connects the two inverters at the

output into a loop. Hence, the value that was present at input D at the

time that C went from 1 to 0 is retained at the Q output by the loop.

3-3 Flip –Flops

Any changes in the data input will change the state of the

latch. In this sense the latch is transparent , since its

input value can be seen from the outputs. The key to the

proper operation is to prevent them from being

transparent. In a flip-flop, before an output can

34

Figure 3.9 SR master slaves Flip-Flop

change, the path from its inputs to its outputs is

broken.

There are two ways that latches are combined to form

a flip-flop. One way is to combine two latches such that (1)

the inputs presented to the flip-flop when a clock pulse is

present control its state and (2) the state of the flip-flop

changes only when a clock pulse is not present. Such a

circuit is called a master-slave flip-flop. Another way is to

produce a flip-flop that triggers only during a signal

transition from 0 to 1 (or from 1 to 0) on the clock pulse.

Such a circuit is said to be an edge triggered flip-flop.

3.3.1 Master-slave Flip-Flops

The master-slave SR flip-flop, consisting of two latches

and an inverter, is shown in Figure 3.9. When the clock

input C is 0, the output of the inverter is 1. The slave latch

is then enabled, and its output Q is equal to the master

output Y. the master latch is disabled, because C is 0.

When logic 1 clock pulse is applied, the values on S and R

control the value stored in the master latch Y. The slave,

however, is disabled as long as the pulse remains at the 1 level, because

its C input is

equal to 0. Any

changes in the

external S and R

inputs change

the master

output Y,

35

Figure 3.10 Negative edge-triggered D Flip-Flop

Figure 3.11 positive edge-triggered D Flip-Flop

but cannot affect the slave output 0. When the pulse returns to 0, the

master is disabled and is isolated from the S and R inputs. At the same

time, the slave is enabled, and the current value of Y is transferred to the

output of the flip-flop at Q.

3.3.2D flip-flop A master-slave D flip-flop can be constructed

from the SR master-slave flip-flop by simply replacing the master SR

latch with a master D latch. The resulting circuit is shown in Figure 3.10.

The resulting circuit changes its value on the negative edge of the clock

36

For the clock input equal to 0, the master latch is enabled and transparent

and follows the D input value. The slave latch is disabled and holds the

state of the flip-flop fixed. When the positive edge occurs, the clock

input changes to 1. This disables the master latch so that its value is fixed

and enables the slave latch so that it copies the state of the master latch.

The state of the master latch to be copied is the state that is present at the

positive edge of the clock. Thus .the behavior appears to be edge

triggered with the clock input equal to 1.the master latch is disabled and

cannot change so the state of both the master and the slave remain

unchanged finally. When the clock input changes from 1 to O. the master

is enabled before any change in the master can reach it. Thus the value

stored in the slave remains unchanged during this transition.

3.3.3 JK and T filp-flop

The JK flip-flop was a modified version of the master-slave SR. when SR

produces undefined output for S=1, R=1, the JK cause the output to

complement its current value.

The T (toggle) flip-flop is equivalent to JK with J and K tied together so that J=K=1are applied. If we take the characteristic equation for the JK and make this connection the equation becomes: T exclusive-ORQ

Standard graphics symbols

The stander graphics symbols for the different types of latches and flip-

flops are shown in Figure 3-12.Aflip –flop or latch is designated by a

rectangular block with inputs on the left and outputs on the right. One

output designates the normal state of the flip-flop, and the other, with a

bubble, designates the complement output.

37

Figure 3.12 standard graphics symbols for latches and flip-flops38

39

Figure 3.13 flip-flop logic characteristic tables

, Characteristic equations, and excitation table

See fig.9

See fig.11

Characteristic table: the table defines the next state Q(t+1) as a function

of the present state Q(t) , and inputs of D, or S,R, or J,K, or T. note that

the pulse at C is not listed, it is assumed to occur between time t, and t+1.

Characteristic equation: it defines the next state after the clock pulse as

a function of present state, and Flip-flop inputs.

Excitation table: these tables define the Flip-flops input value as a

function of next state value after the clock pulse, given the present state

values.

Sequential circuit analysis: we are given the flip-flop inputs, and asked

to give the corresponding output. To do that we must knew the

characteristic table of the given flip-flop.

Sequential circuit design: the inverse of analysis, given present state,

and next state, required designing the input of the flip-flop; we must

know the excitation table of the given flip-flop.

e.g for D type

Q(t), Q(t+1) D

40