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Purpose: This course provides an overview of the SH-2 32-bit RISC CPU core
used in the popular SH-2 series of microcontrollers.
Objectives: Gain a basic knowledge of the SH-2 CPU Understand key features of this 32-bit RISC architecture Learn about the CPU’s addressing modes Explore the SH-2 instruction set Get the details about subroutine calls
Arithmetic instructions have operands in the register A generous register set is required and provided Operands must be loaded from memory Execution time is very fast and
predictable. Local arithmetic execution time is
independent of data path
Standard data length is 32 bits (longword)
Any 8- or 16-bit data is sign-extended for arithmetic operations, or zero-extended for logic operations
Word or longword immediate data is located in memory tables (literal pools) accessed via a PC-relative addressing mode MOV instruction
Classification SH-2 CPU Example of another CPU
PROPERTIESOn passing, 'Finish' button: Goes to Next SlideOn failing, 'Finish' button: Goes to SlideAllow user to leave quiz: At any timeUser may view slides after quiz: After passing quizUser may attempt quiz: Unlimited times
Addressing modes define how/where to find operandsAddressing modes define how/where to find operands
Single-Address Machine
Because the SH-2 is a SINGLE-ADDRESS machine . . . At least one operand is always stored in a register The other operand is defined by the addressing mode The addressing mode defines the Effective Address (EffA) calculation.
Exception: MAC @Rm+,@Rn+
Example: Store contents of register R1 in memory; address of memory is in R2
• MOV.L R1,@R2
- Source operand is general register R1- Destination is memory; address is in R2 (Addressing mode: Register indirect)
Used for array handling & popping values from stack
Great for accessing C/C++ structure contents
Used to access 16-bit and 32-bit constant data from
memory tables/literal poolsFacilitates far branching to anywhere in address space
8-bit data can be held in 16-bit instructions
PROPERTIESOn passing, 'Finish' button: Goes to Next SlideOn failing, 'Finish' button: Goes to SlideAllow user to leave quiz: At any timeUser may view slides after quiz: After passing quizUser may attempt quiz: Unlimited times
Conditional branch coding and handling sequence: T-bit handling with COMPARE instruction Result of condition is tested in T-bit Then branch conditional
Unconditional branch
A subroutine call instruction causes the hardware to: Copy PC contents in PR Put new value into PC Go to next instruction
A return from subroutine instruction causes the hardware to: Copy PR contents in PC Go to next instruction
Boosts program execution speed and reduces code size!
Subroutine Calls
Instructions: BSR, JSR, RTS
Hardware support for single-level subroutine calls
Multiple-level calls require support: "PUSH" and "POP" of previous PC under software control
Sequence: Enter subroutine (BSR/JSR): Hardware: Copy PC to PR Load new value to PC (Software: Push PR to stack)
Execute next instruction ...code... Exit subroutine:
(Software: Pop PR from stack) Hardware: RTS instruction Copy PR to PC Continue
PR
Procedure Register
Program Counter = One-level-deep buffer!
PC
PROPERTIESOn passing, 'Finish' button: Goes to Next SlideOn failing, 'Finish' button: Goes to SlideAllow user to leave quiz: At any timeUser may view slides after quiz: After passing quizUser may attempt quiz: Unlimited times