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Purpose: This course provides an overview of the SH-2A 32-bit RISC CPU core built into
newer microcontrollers in the popular SH-2 series
Objectives: Gain a basic overview of the SH-2A CPU architecture Understand key features of this powerful 32-bit RISC CPU Learn about the internal CPU registers Acquire knowledge about the CPU’s addressing modes Explore the SH-2A instruction set, including the new instructions added to those
GeneralSH-2A: The 32-bit RISC CPU for newer SH-2 series Renesas microcontrollers that . . .
Is a member of the SuperH® family Powers the SH7206 device and others Operates at clock speeds up to 200MHz Executes up to two instructions per cycle
– Delivers up to 360 MIPS performance
Software Has RISC-type instruction set and addressing modes
– Is based on “C”
– Includes delayed branch instructions
Includes 16-bit fixed-length basic instructions for high code density Is upwardly software compatible with SH-1/SH-2 CPUs at object-code level. Adds 32-bit instructions for high performance Incorporates new bit-manipulation instructions
Hardware Has a superscalar and Harvard architecture Executes two instructions/cycle Is a load-store design Has a five-stage pipeline Includes 16 general-purpose 32-bit registers Uses register banks for fast interrupt response Has built-in hardware multiplier-accumulate
unit (MAC) for DSP-type operations Provides a 4GB address space Offers an optional FPU: SH2A-FPU core
5-stage Pipeline(*Two instructions are fetched and executed
simultaneously)
SystemRegisters
Clock
HardwareMultiplier
GeneralRegisters
ControlRegisters
RegisterBanks
SH-2A CPUSuperscalar* RISC Design
CPU Instruction Fetch Bus
CPU Data Fetch Bus
On-chipCache
FPU(SH2A-FPU only)
Support Is supported by a comprehensive set of Renesas software and hardware tools Is also supported by many products and services from a large
Arithmetic instructions have operands in the register A generous register set is required and provided Operands must be loaded from memory Execution time is very fast and
predictable. Local arithmetic execution time is
independent of data path
Standard data length is 32 bits (longword)
Any 8- or 16-bit data is sign-extended for arithmetic operations, or zero-extended for logic operations
OperatedUpon
Memory
Register
PROPERTIESOn passing, 'Finish' button: Goes to Next SlideOn failing, 'Finish' button: Goes to Next SlideAllow user to leave quiz: At any timeUser may view slides after quiz: After passing quizUser may attempt quiz: Unlimited times
Addressing modes define how/where to find operands
SH-2A: A Single-Address Machine
Because the SH-2A is a SINGLE-ADDRESS machine . . . At least one operand is always stored in a register The other operand is defined by the addressing mode The addressing mode defines the Effective Address (EffA) calculation
Exception: MAC @Rm+,@Rn+
Example: Store contents of register R1 in memory; address of memory is in R2
• MOV.L R1,@R2
- Source operand is general register R1- Destination is memory; address is in R2 (Addressing mode: Register indirect)
Reverse stack transfer instructions MOV.B/W/L R0, @Rn+ MOV.B/W/L @-Rn, R0
Unconditional branch instructions with no delay slot JSR/N, RTS/N
Cache prefetch instruction PREF
PROPERTIESOn passing, 'Finish' button: Goes to Next SlideOn failing, 'Finish' button: Goes to Next SlideAllow user to leave quiz: At any timeUser may view slides after quiz: After passing quizUser may attempt quiz: Unlimited times
Conditional & unconditional delayed branches (same as SH-2 CPU)
Conditional branch coding and handling sequence: T-bit handling with COMPARE instruction Result of condition is tested in T-bit Then branch conditional
Unconditional branch with no delay slot (added instruction)
A subroutine call instruction causes the hardware to: Copy PC contents in PR Put new value into PC Go to next instruction
A return from subroutine instruction causes the hardware to: Copy PR contents in PC Go to next instruction
Boosts program execution speed and reduces code size!
Subroutine Calls
Instructions: BSR, JSR, RTS
Hardware support for single-level subroutine calls
Multiple-level calls require support: "PUSH" and "POP" of previous PC under software control
Sequence: Enter subroutine (BSR/JSR): Hardware: Copy PC to PR Load new value to PC (Software: Push PR to stack)
Execute next instruction ...code... Exit subroutine:
(Software: Pop PR from stack) Hardware: RTS instruction Copy PR to PC Continue
PR
Procedure Register
Program Counter = One-level-deep buffer!
PC
PROPERTIESOn passing, 'Finish' button: Goes to Next SlideOn failing, 'Finish' button: Goes to Next SlideAllow user to leave quiz: After user has completed quizUser may view slides after quiz: At any timeUser may attempt quiz: Unlimited times