Tutorial for Quartus II’s SignalTap II Logic Analyzer

Tutorial for Quartus II’s SignalTap II Logic Analyzer

Compiler and Microarchitecture Lab.Korea University

Joon Goo Lee11/27, 2013

Purpose

• To analyze post-layout signals for de-bugging without an actual logic ana-lyzer.

• To capture meaningful signals for a report, a paper, or further analysis.

Tested Environment

• FPGA Board– DE0-Nano: Cyclone IV EP4CE22F17C6N

• IDE– Quartus II 64-Bit 13.1 Web Edition (This

is free version)

• JTAG programmer– USB-Blaster

Prerequisite for Web edition

• Turn on TalkBack Option

Compile a completed project

• Compile your project.– Set pin assignments.– Should have no error.

Select SignalTap II Logic Analyzer

• After compilation– Ensure the JTAG programmer (USB-Blaster) is con-

nected between the board and your PC.– Your board should be powered.

• With DE0-Nano, connected USB cable for JTAG gives power as well.

– Open SignalTap II Logic Analyzer by selecting “Tools | SignalTap II Logic Analyzer”• You can open pre-existing SignalTap II Logic Analyzer file

(*.stp) from “File | Open”.• You can also open the SignalTap II Logic Analyzer by se-

lecting “File | New | Other Files | SignalTap II Logic Ana-lyzer File”.

Select Hardware

• Select Hardware– If not appear USB-Blaster, click Setup

to select the programmer

Add nodes to be analyzed (1/2)

• Double click to add necessary nodes.• Click List to view nodes. (You can use Fil-

ter)

Add nodes to be analyzed (2/2)

• Select nodes.• Click OK– You may see warn-

ing message when you add netlist type nodes or unassigned nodes).

–Whenever you see the message, sim-ply click Yes.

Select proper clock

• Basically, the clock need to be set to FPGA clock.

• If you want to see signals based on other clock, choose the clock.– However, signals may be

distorted.

• Quartus II may remove duplicated signal if you added the same node. Just click OK.

Choose Sample depth and Set trigger(s)

• Sample depth depends on RAM attached to FPGA and the number of nodes (or the frequency of transition) you added.

• You can set multiple triggers.– Select node you want by

using Node Finder.– Set Pattern.

Compile your project

• After setting for SignalTap II Logic Analyzer, you need to compile your project again.– If you see the warning message, click Yes.– If you want to save all the configurations, save

‘stp’ file.– Enable SignalTap II file for the current project.

(You’ll see the related message. Click Yes.)

• Rest until compilation done.– When you see error messages, halve the sam-

ple depth until compilation done without error.

Select ‘sof’ file and program your code

• Select ‘sof’ file to be downloaded first.

• Program your project on the board. 2. Program

your code

1. Click to choose sof file

Run analysis

• Run analysis to view signals.– Note: Clock will not be viewed.

Run analysis to view signal transitions. It only shows transitions until buffer is full.

Autorun analysis to view signals continually.

Limitations and tips• If you add nodes that have high-frequency transition, the time duration will

be shorten.– As I mentioned before, ‘Sample depth’ depends on RAM and the nodes you

added.– If you add small number of nodes, you may increase the ‘Sample depth’.

• Tips.– Select proper clock to see more transitions.– Remove unnecessary nodes.– Set trigger(s) carefully.– For bus signals

• Add individual nodes for a bus, and then group the nodes in the signal view window.• Grouped signals can choose “Bus Display Format”.

You can see more transitions by choosing proper clock and reduced number of nodes.

References

• Mike Pridgen, “Tutorial for Quartus’ SignalTap II Logic Analyzer”, http://www.mil.ufl.edu/4712/docs/SignalTap_Tutorial.pdf

• Altera homepage. http://quartushelp.altera.com/13.1/master.htm