Semiconductor Memories Mohammad Sharifkhani. Outline Introduction Non-volatile memories.

Semiconductor Memories

Mohammad Sharifkhani

Outline

• Introduction

• Non-volatile memories

Semiconductor Memory Classification

Read-Write MemoryNon-VolatileRead-Write

Memory

Read-Only Memory

E2PROM

RandomAccess

Non-RandomAccess

Mask-Programmed

Programmable (PROM)

Shift Register

Memory Timing: Definitions

Write cycleRead access Read access

Read cycle

Write access

Data written

Data valid

Memory Architecture: Decoders

Word 0

Word 1

Word 2

WordN22

WordN21

Storagecell

M bits M bits

SN - 2

K = log2N

Word 0

Word 1

Word 2

WordN22

WordN21

Storagecell

Input-Output(M bits)

Intuitive architecture for N x M memoryToo many select signals:

N words == N select signals K = log2NDecoder reduces the number of select signals

Array-Structured Memory ArchitectureProblem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing torail-to-rail amplitude

Selects appropriateword

Bit line2m

Word line

An - 1Column decoder

Storage cell in the accessed

Hierarchical Memory Architecture

Advantages:Advantages:1. Shorter wires within blocks1. Shorter wires within blocks2. Block address activates only 1 block => power savings2. Block address activates only 1 block => power savings

Globalamplifier/driver

Controlcircuitry

Global data bus

Block selector

Block 0

Rowaddress

Columnaddress

Blockaddress

Blocki BlockP 2 1

Block Diagram of 4 Mbit SRAM

Clockgenerator

CS, WEbuffer

I/Obuffer

Y-addressbuffer

X-addressbuffer

x1/x4controller

Z-addressbuffer

X-addressbuffer

Predecoder and block selectorBit line load

Transfer gateColumn decoder

Sense amplifier and write driver

[Hirose90]

Contents-Addressable Memory

Data (64 bits)

Comparand

CAM Array29 words3 64 bits

Control LogicR/W Address (9 bits)

Memory Timing: Approaches

DRAM TimingMultiplexed Adressing

SRAM TimingSelf-timed

Addressbus

RAS-CAS timing

Row Address

AddressBus

Address transitioninitiates memory operation

Address

Column Address

• Introduction

• Non volatile memories

Non-Volatile MemoriesThe Floating-gate transistor

(FAMOS)

Floating gate

Source

Substrate

n+ n+_p

Device cross-section Schematic symbol

Floating-Gate Transistor Programming

- 5 V 0 V

Removing programming voltage leaves charge trapped

- 2.5 V 5 V

Programming results in higher VT.

10 V 5 V 20 V

Avalanche injection

A “Programmable-Threshold” Transistor

“0”-state “1”-state

VWL VGS

“ON”

“OFF”

FLOTOX EEPROM

Floating gate

Source

Substratep

FLOTOX transistorFowler-Nordheim I-V characteristic

20–30 nm

EEPROM Cell

Absolute threshold controlis hardUnprogrammed transistor might be depletion always on 2 transistor cell

Flash EEPROM

Control gate

erasure

p-substrate

Floating gate

Thin tunneling oxide

n1source n1drainprogramming

Many other options …

Cross-sections of NVM cells

EPROMFlashCourtesy Intel

Basic Operations in a NOR Flash Memory―

cell arrayBL0 BL1

open open

BL0 BL1

6 V 0 V

Read5 V

BL0 BL1

1 V 0 V

NAND Flash Memory

Unit Cell

Word line(poly)

Courtesy Toshiba

FGGateOxide

Select line

Source line(Diff. Layer)

NAND Flash Memory

Word linesSelect transistor

Bit line contact Source line contact

Active area

Courtesy Toshiba

Characteristics of State-of-the-art NVM

Outline

• Introduction

• RAM

Read-Write Memories (RAM) STATIC (SRAM)

DYNAMIC (DRAM)

Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential

Periodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle Ended

6-transistor CMOS SRAM Cell

CMOS SRAM Analysis (Read)WL

M1VDDVDD VDD

Q = 1Q = 0

Cbit Cbit

CMOS SRAM Analysis (Read)

0.5 1 1.2 1.5 2Cell Ratio (CR)

CMOS SRAM Analysis (Write)

BL = 1 BL = 0

CMOS SRAM Analysis (Write)

6T-SRAM — Layout

Decreasing Word Line Delay

Metal bypass

Polysilicon word lineK cells

Polysilicon word lineWL

Driver

(b) Using a metal bypass

(a) Driving the word line from both sides

Metal word line

(c) Use silicides

Resistance-load SRAM Cell

Static power dissipation -- Want RL largeBit lines precharged to VDD to address tp problem

SRAM Characteristics

• Introduction

• RAM– SRAM– DRAM

3-Transistor DRAM Cell

No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn

VDD 2VT

DVVDD 2VTBL2

3T-DRAM — Layout

BL2 BL1 GND

1-Transistor DRAM Cell

Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

VDD2 VT

sensing

Write 1 Read 1

VDD /2 V

V BL VPRE– VBIT VPRE–CS

CS CBL+------------= =V

DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells.The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD

Sense Amp Operation

Sense amp activatedWord line activated

1-T DRAM Cell

Uses Polysilicon-Diffusion Capacitance

Expensive in Area

M1 wordline

Diffusedbit line

Polysilicongate

Polysiliconplate

Capacitor

Cross-section Layout

Metal word line

Field Oxiden+ n+

Inversion layerinduced byplate bias

SEM of poly-diffusion capacitor 1T-DRAM

Advanced 1T DRAM Cells

Cell Plate Si

Capacitor Insulator

Storage Node Poly

2nd Field Oxide

Refilling Poly

Si Substrate

Trench Cell Stacked-capacitor Cell

Capacitor dielectric layerCell plateWord line

Insulating Layer

IsolationTransfer gate

Storage electrode

Static CAM Memory Cell

••• CAM

Bit Bit

Wired-NOR Match Line

Match M1

M4 M5M8 M9

••• CAM

Bit Bit

CAM in Cache Memory

Input Drivers

Tag HitAddress

Sense Amps / Input Drivers

DataR/W

• Introduction

• RAM

• Periphery circuits

Periphery

Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry

Row DecodersCollection of 2M complex logic gatesOrganized in regular and dense fashion

(N)AND Decoder

NOR Decoder

Hierarchical Decoders

• • •

A2A3A2A 3A2A3

A3 A3A 0A0

A0A 1A 0A1A0A1A0A1

A 1 A1

Multi-stage implementation improves performance

NAND decoder usingNAND decoder using2-input pre-decoders2-input pre-decoders

Dynamic Decoders

Precharge devices

A0A0 A1A1

2-input NOR decoder 2-input NAND decoder

Active low inputs (all are high except for the selected WL which is low)

4-input pass-transistor based column decoder

Advantages: speed (tpd does not add to overall memory access time) Only one extra transistor in signal pathDisadvantage: Large transistor count

BL 0 BL 1 BL 2 BL 3

4-to-1 tree based column decoder

Number of devices drastically reducedDelay increases quadratically with # of sections; prohibitive for large decoders

buffersprogressive sizingcombination of tree and pass transistor approaches

Solutions:

BL 0 BL 1 BL 2 BL 3

Decoder for circular shift-register

f• • •

Sense Amplifiers

Iav----------------=

make V as smallas possible

smalllarge

Idea: Use Sense Amplifer

outputinput

s.a.smalltransition

Differential Sense Amplifier

Directly applicable toSRAMs

bitbit

Differential Sensing ― SRAMVDD

Diff.SenseAmp

(a) SRAM sensing scheme (b) two stage differential amplifier

SRAM cell i

Output

x2x 2x

Latch-Based Sense Amplifier (DRAM)

Initialized in its meta-stable point with EQOnce adequate voltage gap created, sense amp enabled with SEPositive feedback quickly forces output to a stable operating point.

Charge-Redistribution Amplifier

0.0 1.00 2.00time (nsec)

Vref5 3V

(b) Transient response

Concept

M1VL VS

CsmallClarge

Transient Response

Charge-Redistribution Amplifier―EPROM

Cascodedevice

Columndecoder

EPROMarray

Single-to-Differential Conversion

How to make a good Vref?

Diff.S.A.Cell

Output

Open bitline architecture with dummy cells

CS CS CS CS

L L1 L0 R0

… …

Dummy cell Dummy cell

DRAM Read Process with Dummy Cell

00 1 2 3

t (ns)

reading 03

00 1 2 3

t (ns)

control signals

00 1 2 3

t (ns)

reading 1

Voltage Regulator

Mdrive

Equivalent Model

Charge Pump

M2Vload

2VDD 2 VT

VDD 2 VT

Q=Cpump (VDD-Vt)

DRAM Timing

SDRAM Timing

A chunk of data is processed at the same time effective when data is written in large sequential blocks

RDRAM Architecture

memoryarray

Databus

Clocks

Column

Rowdemux packet dec.

packet dec.

k kx l

Rambus DRAM to reduce the access time

Synch. DRAM

Operates at uP clock speed

up to 1.6 GB/sec bandwidth

Highly parallel: A large number of bits can be read/write at the same time interface ; fast and synch

Address Transition Detection

DELAYtdA0

DELAYtdA1

DELAYtdAN2 1

ATD ATD

• Introduction

• RAM

• Periphery

• Reliability

Reliability and Yield

Sensing Parameters in DRAM

From [Itoh01]

64K 1M 16M256M 4G 64GMemory Capacity (bits/chip)

CD(1F)

CS(1F)

QS(1C)

Vsmax(mv)

VDD(V)

QS= CS VDD/2Vsmax= QS/(CS 1 CD)

Noise Sources in 1T DRam

Ccross

electrode

a-particles

leakage CS

BL substrate Adjacent BL

Open Bit-line Architecture —Cross Coupling

SenseAmplifierC

CWBL CWBL

WLD WLD WL0 WL1

Folded-Bitline Architecture

SenseAmplifier

WL0 WL0 WLD

BL CBL

Transposed-Bitline Architecture

Ccross

(a) Straightforward bit-line routing

(b) Transposed bit-line architecture

Ccross

Alpha-particles (or Neutrons)

1 Particle ~ 1 Million Carriers

a-particle

Yield curves at different stages of process maturity(from [Veendrick92])

Redundancy

MemoryArray

Column Decoder

Redundantrows

Redundantcolumns

RowAddress

ColumnAddress

FuseBank:

Error-Correcting Codes

Example: Hamming Codes

e.g. B3 Wrong

Redundancy and Error Correction

Sources of Power Dissipation in Memories

PERIPHERY

ROWDEC

selected

non-selected

COLUMN DEC

nCDEV INTf

mCDEV INTf

CPTV INTf

m(n- 1)ihld

IDD = ΣCiΔV if+Σ IDCP

From [Itoh00]

Data Retention in SRAM1.30u

0.00 .600 1.20 1.80

Factor 7

0.13 m CMOSm

0.18 m CMOSm

SRAM leakage increases with technology scaling

Suppressing Leakage in SRAM

SRAMcell

VDD,int

VDD VDDL

VSS,int

SRAMcell

VDD,int

low-threshold transistor

Reducing the supply voltageReducing the supply voltageInserting Extra ResistanceInserting Extra Resistance

Data Retention in DRAM101

15M 64M 255M 1G 4G 15G 64G

Capacity (bit)

3.3 2.5 2.0 1.5 1.2 1.0 0.8

Operating voltage (V)

0.53 0.40 0.32 0.24 0.19 0.16 0.13

Extrapolated threshold voltage at 25 C (V)

Cycle time : 150 nsT 5 75 C,S

From [Itoh00]

Case Studies

• SRAM

• Flash Memory

4 Mbit SRAMHierarchical Word-line Architecture

Global word line

Sub-global word line

Block groupselect

Blockselect

Memory cell

Localword line

Block 0

•••

Localword line

Block 1

•••

Block 2...

•••

Bit-line Circuitry

Bit-lineload

Blockselect ATD

Local WL

Memory cell

I/O lineI/O

Sense amplifier

Sense Amplifier (and Waveforms)

I /O I /O

Blockselect ATD

BSSA SA

SEQSEQ

I/O Lines

Address

Data-cut

SA, SA

1 Gbit Flash Memory

Sense Latches(10241 32)3 8

Data Caches(10241 32)3 8

Sense Latches(10241 32)3 8

Data Caches(10241 32)3 8

512Mb Memory Array 512Mb Memory Array

BL0 BL1 ····· BL16895 BL16996 BL16897··· BL33791

SGDWL31

WL0SGS

Block0

Block1023

Block0

Block1023

Bit Line Control CircuitBLT1

From [Nakamura02]

Writing Flash MemoryN

0V 1V 2V

Vt of memory cells

Verify level5 0.8 V Word-line level5 4.5 V

Result of 4 timesprogram

0V 1V 2V

Vt of memory cells

Evolution of thresholds Final Distribution

From [Nakamura02]

125mm2 1Gbit NAND Flash Memory

11.7mm

16896 bit lines

32 word lines x 1024 blocks

From [Nakamura02]

125mm2 1Gbit NAND Flash Memory

• Technology 0.13m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al• Cell size 0.077m2• Chip size 125.2mm2• Organization 2112 x 8b x 64 page x 1k block• Power supply 2.7V-3.6V• Cycle time 50ns• Read time 　 25s• Program time 200s / page• Erase time 2ms / block

From [Nakamura02]

Semiconductor Memory Trends(up to the 90’s)

Memory Size as a function of time: x 4 every three years

Semiconductor Memory Trends(updated)

From [Itoh01]

Trends in Memory Cell Area

From [Itoh01]

Future generations

• Very specialized technologies for stand alone memories expensive

• Reliability is going to be a very important issue (SER) particularly for SRAMs and DRAMs

• Power is going to be the limiting factor particularly when it comes to standby currents

• Embedded memories is the prominent market thrust driven by all mobile/SoC applications

Semiconductor Memories Mohammad Sharifkhani. Outline Introduction Non-volatile memories.

t dram

dram memor

dram cell observations

array block

block address

cell ratio cr2

voltage rise v11

charge redistribution

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