S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources:

S. Reda EN160 SP’07

Design and Implementation of VLSI Systems(EN0160)

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2007

[sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07

SPICE introduction

• SPICE, a Simulation Program with Integrated Circuit Emphasis

SPICE deck

SPICE card

• We will use SmartSPICE by SimuCAD (http://www.engin.brown.edu/vpn)

S. Reda EN160 SP’07

SPICE Intro

• SPICE is case insensitive • Cards beginning with a dot (.) are control cards• Cards beginning with a * are comment cards• The last card must be .end• Each card in the netlist must begin with a letter

indicating its type

S. Reda EN160 SP’07

SPICE circuit elements

Letter Circuit ElementR ResistorC CapacitorL InductorK Mutual InductorV Independent voltage sourceI Independent current sourceM MOSFETD DiodeQ Bipolar transistorW Lossy transmission lineX SubcircuitE Voltage-controlled voltage sourceG Voltage-controlled current sourceH Current-controlled voltage sourceF Current-controlled current source

S. Reda EN160 SP’07

Units

Letter Unit Magnitude

a atto 10-18

f femto 10-15

p pico 10-12

n nano 10-9

u micro 10-6

m mili 10-3

k kilo 103

x mega 106

g giga 109

S. Reda EN160 SP’07

Voltage sources

• DC Source– Vdd vdd gnd 2.5

• Piecewise Linear Source– Vin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8

• Pulsed Source– Vck clk gnd PULSE 0 1.8 0ps 100ps 100ps 300ps 800ps

PULSE v1 v2 td tr tf pw per

v1

v2

td tr tfpw

per

(time, voltage) pairs

S. Reda EN160 SP’07

RC response*rc.sp.option postVin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8R1 in out 2kC1 out gnd 100f.tran 20ps 800ps.plot v(in) v(out).end

Tutorial movie at http://ic.engin.brown.edu/classes/EN160S07/spice.avi

S. Reda EN160 SP’07

NMOS I-V characteristics

.option post

.include 'tsmc-180.txt'

.temp 70

.option scale=90n

Vgs g gnd 0Vds d gnd 0M1 d g gnd gnd NMOS W=2 L=2.dc Vds 0 1.8 0.05 sweep vgs 0 1.8 0.3.plot i(m1).end

Mname drain gate source body type W=<width> L=<length>

S. Reda EN160 SP’07

NMOS I-V characteristics

S. Reda EN160 SP’07

Inverter transient analysis

.option post

.include 'tsmc-180.txt'

.temp 70

.option scale=90n

Vdd vdd gnd 1.8M1 d g gnd gnd NMOS W=4 L=2 AS=20 PS=18 AD=20 PD=18M2 d g vdd vdd PMOS W=8 L=2 AS=40 PS=26 AD=40 PD=26Vgs g gnd PULSE 0 1.8 0ps 10ps 10ps 100ps 220ps.tran 20ps 440ps.end

for diffusion capacitance calculations

S. Reda EN160 SP’07

Inverter transient analysisbootstrapping

S. Reda EN160 SP’07

Measuring propagation delay

a* delay measurement.param SUPPLY=1.8.param H=4.option scale=90nm.include 'tsmc-180.txt'.temp 70.option post.global vdd gnd.subckt inv a y N=4 P=8M1 y a gnd gnd NMOS W='N' L=2M2 y a vdd vdd PMOS W='P' L=2.endsVdd vdd gnd 'SUPPLY'Vin a gnd PULSE 0 'SUPPLY' 0ps 100ps 100ps 500ps 1000psX1 a b inv N=4 P=8X2 b gnd inv N=16 P=32.tran 1ps 1000ps.measure tpdr TRIG v(a) VAL='SUPPLY/2' FALL=1 TARG v(b) VAL='SUPPLY/2' rise=1.end

Ignoring diffusion

capacitance!!

S. Reda EN160 SP’07

Measuring propagation delay

83.7ps

S. Reda EN160 SP’07

Leakage current/threshold voltage

.option post

.include 'tsmc-180.txt'

.temp 70

.option scale=90n

Vgs g gnd 0Vds d gnd 1.8M1 d g gnd gnd NMOS W=2 L=2.dc Vgs 0 1.8 0.05 s.plot i(m1).end

S. Reda EN160 SP’07

Leakage current/threshold voltage

Vgs

S. Reda EN160 SP’07

Summary

This lecture:– SPICE tutorial. (you can find more in chapter 5)– We finished chapters 1 and 2 and parts of chapter

3 (CMOS fabrication)

Next time:– Relevant parts from chapter 3 and Tanner L-Edit

tutorial– Please starting working on assignment 2 ASAP