Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley.

Design and Implementation of VLSI Systems(EN0160)

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2007

[sources: Weste/Addison Wesley – Rabaey/Pearson]

pn-junction reminder

• Depletion region has associated capacitance

• When the diode is reversed biased (supposedly cutoff), tiny current based on the minority carries still flows

• Transistor has two p-n diodes

n

p

A

B

Al

One-dimensionalrepresentation

fixed ionsdepletion region(almost no mobile carriers)

Gate Capacitance

• Approximate channel as connected to source

• Cgs = oxWL/tox = CoxWL = CpermicronW

• Cpermicron is typically about 2 fF/m

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, ox = 3.90)

polysilicongate

Source/Drain diffusion capacitance

• Csb, Cdb

• Undesirable, called parasitic capacitance

• Capacitance depends on area and perimeter– Use small diffusion nodes

– Comparable to Cg

– Varies with process

Bottom

Side wall

Side wallChannel

SourceND

Channel-stop implant NA1

SubstrateNA

W

xj

LS

Transistor resistance

In the linear region

• Not accurate, but at least shows that the resistance is proportional to L/W and decreases with Vgs

• If R/C are for a unit size transistor then a transistor of K unit width has KC capacitance and R/K resistance

• The resistance of a PMOS transistor = 2× resistance of NMOS transistor of the same size

Switch-level RC models

• Use equivalent circuits for MOS transistors– Ideal switch + capacitance and ON resistance– Unit nMOS has resistance R, capacitance C– Unit pMOS has resistance 2R, capacitance C

• Capacitance proportional to width• Resistance inversely proportional to width

kg

s

d

g

s

d

kCkC

kCR/k

kg

s

d

g

s

d

kC

kC

kC

2R/k

Inverter RC delay estimate

• Estimate the delay of a fanout-of-1 inverter

C

CR

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1

d = 6RC

Fallacies

1. Increasing Vds does not increase the saturation current

2. The transistor does not conduct in cutoff 3. The saturation current increases

quadratically for linear increases in Vgs

4. Transistor temperature can be ignored

Channel length modulation

• The reverse-bias p-n junction between drain and body forms a depletion region with a width Ld that increases with Vdb

• Increasing Vds increases depletion width decreases channel length increases current

Channel length modulation factor (empirical factor)

n+

p

GateSource Drain

bulk Si

n+

VDDGND VDD

GND

LLeff

Depletion RegionWidth: Ld

Leakage current

n+ n+

p-type body

W

L

tox

polysilicon

gate

Subthreshold conduction

Tunnel current

Junction leakage

Subthreshold leakage is the biggest source in modern transistors 180nm process

0e 1 egs t ds

T T

V V V

nv vds dsI I

2 1.80 eds TI v n = 1.4-15

Velocity saturation

(V/µm)c = 1.5

n

(m

/s)

sat = 105

Constant mobility (slope = µ)

Constant velocity

At high electric field, drift velocity rolls of due to carrier scattering

Empirically:

With channel length modulation

Temperature dependence

Summary

• Today:– Transistor RC delay models– Nonideal transistor operation

• Next time:– SPICE tutorial