Radiation Tests on IHP’s SiGe Technologies for the Front-End Detector Readout in the S-LHC

Radiation Tests on IHP’s SiGe Technologies for the Front-End Detector Readout in the S-LHC

M. Ullán,

S. Díez, F. Campabadal, G. Pellegrini, M. Lozano

CNM (CSIC), Barcelona

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

FrameworkIncreased luminosity at S-LHC 2 main challenges on Electronics: Instantaneous High occupancy pile up

Higher segmentation More channels Power, Services Increased shaping time Speed, Power

Integrated Radiation Degradation Charge Collection Efficiency ↓ Signal ↓ Gain, Power Gain degradation Current ↑ Power Noise degradation S/N ↓ Noise, Power

Need to find a proper technology that deals with these challenges High speed, high gain with Low power consumption Radiation degradation Cost, availability (prototyping, long term production)

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

General Aims

Evaluation of SiGe BiCMOS technologies for the readout of the

upgraded ATLAS ID Evaluate radiation hardness

Prove power saving with speed and gain

Proposal of one SiGe BiCMOS technology for the IC-FE design

Design of a prototype Front End IC.

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

IHP’s SiGe Technologies

Main200 GHz

0.13 m

Alternative

Low cost

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Experiments

2 general experiments:

Exp 1: “first approximation” 2 technologies

Gamma irradiations up to 10 and 50 Mrads(Si)

Neutron irradiations

Exp 2: Final total dose results 3 technologies

Gamma irradiations up to 10 and 50 Mrads(Si)

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Exp 1: Samples

2 Test chip wafer pieces with ~20 chips

2 Technologies: SGC25C (bip. module equivalent to SG25H1)

SG25H3 (Alternative technology)

Edge effects: Solved in next samples

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Irradiation Setup

4 chips per board, 2 of each technology

2 different transistor sizes:

0.21 x 0.84 μm2

0.42 x 0.84 μm2

Biased

Pb(2 mm) – Al(2 mm) shielding box

NAYADE: “Water Well” Co60

source at Madrid (CIEMAT)

~300 rad(Si)/s up to 10 Mrad(Si)

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

IHP’s SGC25C Technology

Bip. tr. equivalent to SG25H1 technology (fT = 200 GHz)

No Annealing !

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

IHP’s SG25H3 Technology

fT = 120 GHz, Higher breakdown voltages

Annealing after 50 Mrads: 48 hours, very good recovery

Very low gains before irrad (edge wafer transistors)

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Results Exp 1

Excess Base Current @ 0.7 V [10 Mrad(Si)]

0.E+00

5.E-01

1.E+00

2.E+00

2.E+00

3.E+00

3.E+00

4.E+00

4.E+00

5.E+00

5.E+00

C1N1

C1X1

C2N1

C2X1

C3N1

C3X1

C4N1

C4X1

C3A61

C4A61

C3A21

C3A41

C4A21

C4A41

Exc

ess

Bas

e C

urr

ent (

DIB/D

I B0)

SGC25C

SG25H3

unbiased

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Results Exp 1

Bias Current for beta > 50 after 10 Mrad(Si)Collector Current for beta > 50 after 10 Mrad(Si)

0.0E+00

1.0E-06

2.0E-06

3.0E-06

4.0E-06

5.0E-06

6.0E-06

7.0E-06

8.0E-06

9.0E-06

1.0E-05

1.1E-05

1.2E-05

C1N1

C1X1

C2N1

C2X1

C3N1

C3X1

C4N1

C4X1

C3A61

C4A61

C3A21

C3A41

C4A21

C4A41

IC(B

eta>

50)

(A

)

SGC25C SG25H3

unbiased

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Exp 2: Samples

3 Test chip wafer center pieces with > 20 chips

3 Technologies: SG25H1 (“Wafer D”)

SG25H3 (“Wafer I”)

SGC25VD (“Wafer V”)

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Exp 2: Samples

target = 190

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Exp 2: Samples

target = 190

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Exp 2: Samples

No edge effect in the area of interestS462b (Z2)S461c (Y3)

-3 -2 -1 0 1 2 3

8

7

6

5

4

3

2

1

0105

125

145

165

185

205

185-205

165-185

145-165

125-145

105-125

-3 -2 -1 0 1 2 3

8

7

6

5

4

3

2

1

0

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Exp 2: Samples

target = 200

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Exp 2: Samples

target = 150

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Heavy rad damage Transistors heavily damaged but still functional Possible damage saturation Significant beneficial annealing

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Results Exp 2

Normalized gain f/0 @VBE = 0.7 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

FJ1

N

FJ2

N

FJ3

N

FJ4

N

FL

1N

FL

2N

FL

3N

FL

4N

FL

1X

FL

2X

FL

3X

FL

4X

FM

1Y

3

FM

2Y

3

FM

3Y

3

FM

4Y

4

FM

1Z

2

FM

2Z

2

FM

3Z

2

FM

4Z

2

FM

1Z

3

FM

2Z

3

FM

3Z

3

FM

4Z

3

Transistor

Be

ta N

10Mrad

10Mrad+ANN

50Mrad

50Mrad+ANN

SG25H1 SG25H3 SGB25VD

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Results Exp 2

Normalized base current density JBf/JB0 @VBE = 0.7 V

0

2

4

6

8

10

12

14

FJ1

N

FJ2

N

FJ3

N

FJ4

N

FL

1N

FL

2N

FL

3N

FL

4N

FL

1X

FL

2X

FL

3X

FL

4X

FM

1Y

3

FM

2Y

3

FM

3Y

3

FM

4Y

4

FM

1Z

2

FM

2Z

2

FM

3Z

2

FM

4Z

2

FM

1Z

3

FM

2Z

3

FM

3Z

3

FM

4Z

3

tr

Jb N

10Mrad

10Mrad+ANN

50Mrad

50Mrad+ANN

SG25H1 SG25H3 SGB25VD

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Results Exp 2

Collector current needed for = 50

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04F

J1N

FJ2

N

FJ3

N

FJ4

N

FL

1N

FL

2N

FL

3N

FL

4N

FL

1X

FL

2X

FL

3X

FL

4X

FM

1Y

3

FM

2Y

3

FM

3Y

3

FM

4Y

4

FM

1Z

2

FM

2Z

2

FM

3Z

2

FM

4Z

2

FM

1Z

3

FM

2Z

3

FM

3Z

3

FM

4Z

3

tr

Ic(5

0)

[A]

10Mrad

10Mrad+ANN

50Mrad

50Mrad+ANN

SG25H1 SG25H3 SGB25VD

~ 3 μA

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Exp 2: Tech. comparison

Current Gain Degradation

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 10 20 30 40 50 60

Gamma Dose [Mrad(Si)]

No

rmal

ized

Gai

n

SG25H1

SG25H3

SGB25VD

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Exp 2: Tech. comparison

Collector current for = 50

1.E-07

1.E-06

1.E-05

1.E-04

10 50

Gamma Dose [Mrad(Si)]

Ic (

Bet

a =

50)

SG25H1

SG25H3

SGB25VD

No annealing

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Other results

Annealing:Annealing Jb N

0

1

2

3

4

5

6

7

8

9

0 5 10 15 20 25Days

Jb N

FM1Y3

FM2Y3

FM1Z2

FM2Z2

FM3Z2

FM4Z2

FM1Z3

FM2Z3

FM3Z3

FM4Z3

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Other results

Biasing:

0.00

1.00

2.00

3.00

4.00

5.00

6.00

7.00

8.00

9.00

10.00

BIASED GROUNDED FLOATING

Nor

m.

Exc

ess

J B

10 Mrad(Si)

50 Mrad(Si)

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Conclusions

Evaluation of three different IHP’s SiGe BiCMOS technologies Results indicate that IHP’s technologies would remain functional

after S-LHC life span Not large differences in degradation among technologies,

although one can see: Higher damages in SG25H1 technology,

lower damages in SG25H3 technology

Annealing behavior studied, saturation is observed. It has been proven that device irradiations with floating terminals

produce an over-damage on the devices. Small damage differences between biasing or grounding the devices during irradiations.

Prague, June 20068th RD50 Workshop Miguel Ullán – CNM, Barcelona

Future work

100 Mrads(Si) total dose

LDRE – damage vs. dose mapping

Measure more devices/components of technologies

More statistics needed for a finer data analysis

Study emitter geometry influence

Specific TEST CHIP for irradiations is being designed

Investigate damage under n and p irradiation

Temperature influence

Compare with other SiGe technologies Choose DESIGN FE CHIP