Magnetic core memory (1951) - unirc.it...Magnetic core memory (1951) 16 16 cm2 (128 128 bit) Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only

Magnetic core memory (1951)

1616 cm2 (128128 bit)

Semiconductor Memory Classification

Read-Write MemoryNon-VolatileRead-Write

MemoryRead-Only Memory

EPROM

E2PROM

FLASH

RandomAccess

Non-RandomAccess

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

LIFO

Memory Timing: Definitions

Write cycleRead access Read access

Read cycle

Write access

Data written

Data valid

DATA

WRITE

READ

Memory Architecture: Decoders

Word 0

Word 1

Word 2

WordN2 2

WordN2 1

Storagecell

M bits M bits

Nwords

S0

S1

S2

SN2 2

A0

A1

AK2 1

K = log2N

SN2 1

Word 0

Word 1

Word 2

WordN2 2

WordN2 1

Storagecell

S0

Input-Output(M bits)

Intuitive architecture for N x M memoryToo many select signals:

N words == N select signals K = log2NDecoder reduces the number of select signals

Input-Output(M bits)

Decoder

Row

Dec

oder

Bit line2L 2 K

Word line

AK

AK1 1

AL 2 1

A0

M.2K

AK2 1

Sense amplifiers / Drivers

Column decoder

Input-Output(M bits)

Storage cell

Array-Structured Memory ArchitectureProblem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing torail-to-rail amplitude

Selects appropriateword

Memory Timing: Approaches

DRAM TimingMultiplexed Adressing

SRAM TimingSelf-timed

Addressbus

RAS

RAS-CAS timing

Row Address

AddressBus

Address transitioninitiates memory operation

Address

Column Address

CAS

Read-Only Memory Cells

WL

BL

WL

BL

1WL

BL

WL

BL

WL

BL

0

VDD

WL

BL

GND

Diode ROM MOS ROM 1 MOS ROM 2

MOS NOR ROM

MOS NAND ROM

All word lines high by default with exception of selected row

Cross-sections of NVM cells

EPROMFlashCourtesy Intel

Read-Write Memories (RAM) STATIC (SRAM)

DYNAMIC (DRAM)

Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential

Periodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle Ended

6-transistor CMOS SRAM Cell WL

BL

VDD

M5M6

M4

M1

M2

M3

BL

QQ

SRAM Characteristics

Esempio di organizzazione di una cella di memoria statica

S Q

R

abilitazione scrittura

abilitazione lettura

dato in

selezione riga

selezione colonna

dato out

pass-gate

(three state)

Esempio di organizzazione di una cella di memoria statica

abilitazione scrittura

abilitazione lettura

dato in

selezione riga

dato out

dato in

dato in

dato out

dato out

selezione colonna

WWL

BL1

M 1 X

M3

M2

CS

BL2

RWL

VDD

VDD - VT

VVDD - VTBL2

BL1

X

RWL

WWL

1-Transistor DRAM Cell

Write: CS is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

M1

CS

WL

BL

CBL

VDD 2 VT

WL

X

sensing

BL

GND

Write 1 Read 1

VDD

VDD /2 VDD /2

DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells.The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.When writing a “1” into a DRAM cell, a threshold voltage is lost.

1-T DRAM Cell

Expensive in Area

Cross-section

Metal word line

Poly

SiO 2

Field Oxiden+ n+

Inversion layerinduced byplate bias

Poly

Advanced 1T DRAM Cells

Cell Plate Si

Capacitor Insulator

Storage Node Poly

2nd Field Oxide

Refilling Poly

Si Substrate

Trench Cell Stacked-capacitor Cell

Capacitor dielectric layerCell plateWord line

Insulating Layer

IsolationTransfer gateStorage electrode

Periphery

Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry

DRAM Timing

Reliability and Yield

Redundancy

MemoryArray

Column Decoder

Row Decoder

Redundantrows

Redundantcolumns

RowAddress

ColumnAddress

FuseBank:

Error-Correcting Codes

with

e.g. B3 Wrong

1

1

0

= 3

Redundancy and Error Correction

125mm2 1Gbit NAND Flash Memory

10.7

mm

11.7mm

2kB

Page

buf

fer &

cac

heC

harg

e pu

mp

16896 bit lines

32 word lines x 1024 blocks

From [Nakamura02]

125mm2 1Gbit NAND Flash Memory

• Technology 0.13m p-sub CMOS triple-well• Technology 0.13m p-sub CMOS triple-well1poly, 1polycide, 1W, 2Al

• Cell size 0.077m2• Chip size 125.2mm2• Organization 2112 x 8b x 64 page x 1k block• Power supply 2.7V-3.6V• Cycle time 50ns• Read time 25s• Program time 200s / page• Erase time 2ms / block

From [Nakamura02]