Chapter 5 Memory and Programmable Logic 5.1. Introduction 5.2. Random Access Memory 5.3. Memory Encoding 5.4. Read Only Memory 5.5. Programmable Logic Array 5.6. Examples By Dr. Ridha Jemal Electrical Engineering Department College of Engineering King Saud University 1 EE208 Logic Design 1430-1431 Dr. Ridha Jemal
Chapter 5 Memory and Programmable Logic 5.1. Introduction 5.2. Random Access Memory 5.3. Memory Encoding 5.4. Read Only Memory 5.5. Programmable Logic.
Dec 28, 2015
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Chapter 5 Memory and Programmable Logic
5.1. Introduction5.2. Random Access Memory5.3. Memory Encoding5.4. Read Only Memory5.5. Programmable Logic Array5.6. Examples
By Dr. Ridha JemalElectrical Engineering Department
College of EngineeringKing Saud University
1EE208 Logic Design 1430-1431Dr. Ridha Jemal
5.1. IntroductionThe design procedure follows the following steps:
• From the specification of the circuit, determine the required number of inputs and outputs and assign a symbol to each•Derive the truth table that defines the required relationship between inputs and outputs•Obtain the simplified Boolean functions for each outputs as a function of the input variables•Draw the logic diagram and verify the correctness of the design.
Chapter 5 - page: 2EE208 Logic Design 1430-1431Dr. Ridha Jemal
Why we use Programmable Logic ?• Many designs required only small volumes of Ics• Handle many designs required in small volumes
• programmed to implement large numbers of different low-volume designs
4.2. Rondom Access Memory (RAM)
Chapter 5 - page :3EE208 Logic Design 1430-1431Dr. Ridha Jemal
4.3. Memory Decoding
Chapter 5 - page :4EE208 Logic Design 1430-1431Dr. Ridha Jemal
• In addition to the storage component, in the memory unit, there is a need for decoding circuit to select the memory word specified by the unit address.
• Let us consider a decoder with 4 inputs and enable signal and Basic Cell (BC) of the storage component within the memory device.
Decoder and Basic Cell in the RAM memory
4x16Decoder
I0
I1
I2
I3
EN
word0
word1
word2
word15
….
BC
Select
OutputInput
Read/Write
4.3. Memory Decoding
Chapter 5 - page :5EE208 Logic Design 1430-1431Dr. Ridha Jemal
• Let us consider a RAM of four words of four bits each and has a total of 16 binary cells.Decoder and Basic Cell in the RAM memory
Input data
Output data
BC
….
BCBC BC
BCBC BC BC
…. …. ….2x4Decoder
I0
I1
I2
I3
EN
Word 0
Word 1
Word 2
Word 3
Addressinputs
MemoryEnable
Read/Write
4.4. Read Only Memory
Chapter 5 - page :6EE208 Logic Design 1430-1431Dr. Ridha Jemal
• Let us consider a ROM of 32 words of 8 bits each.
Output data
5x32Decoder
I0
I1
I2
I3
EN
Word 0
Word 1Word 2
Word 29
Addressinputs
MemoryEnable
Word 3
Word 30
Word 31
I4
A7 A6 A5A4 A3 A2
A1 A0
4.4. ROM Implementation
Chapter 5 - page :7EE208 Logic Design 1430-1431Dr. Ridha Jemal Output data
5x32Decoder
I0
I1
I2
I3
EN
Word 0Word 1
Word 2
Word 29
Addressinputs
MemoryEnable
Word 3
Word 30Word 31
I4
A7 A6 A5 A4 A3 A2A1 A0
Example
4.4. ROM Implementation
Chapter 5 - page :8EE208 Logic Design 1430-1431Dr. Ridha Jemal
Example of ROM (k=3 address lines, N = 4 output lines)
• Read Example: For input (A2,A1,A0) = 011, output is (F3,F2,F1,F0 ) = 0011.
• What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?
D7D6D5D4D3D2D1D0
A2
A1A0
A
B
C
F0F1F2F3
X XX
XX
X
XX
XX
4.4. ROM Implementation
Chapter 5 - page :9EE208 Logic Design 1430-1431Dr. Ridha Jemal
Example
Inputs OutputsA2 A1 A0 B5 B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 00 0 1 0 0 0 0 0 10 1 0 0 0 0 1 0 00 1 1 0 0 1 0 0 11 0 0 0 1 0 0 0 01 0 1 0 1 1 0 0 11 1 0 1 0 0 1 0 01 1 1 1 1 0 0 0 1
• Consider the truth table for the combinational circuit
8x4ROM
A0
A1
A2
B0
B1
B2
B5
B4
B3
0
4.5. Programmable Logic Array
Chapter 5 - page :10EE208 Logic Design 1430-1431Dr. Ridha Jemal
Example
Fuse intact
Fuse blown
1
F1
F2
X
A
B
C
C C B B A A 0
1
2
3
4X
XX
X X
X
X
X
X
X
X
X
X
X A B
A C
B C
A B
X
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