Introduction to VLSI Testing and Design For Testability(DFT) TESTING...• Design for testability (DFT) – Chip area overhead, i.e., yield loss – Performance overhead, i.e., degradation
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「DIP概論」-IP Testing
淡江大學電機工程學系
饒建奇
jcraucsccuedutw教育部顧問室
「超大型積體電路與系統設計」教育改進計畫 DIP聯盟
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 2
「DIP概論」- IP Testing
Text Books
bull M L Bushnell and V D Agrawal Essentials of Electronic Testing for Digital Memory amp Mixed-Signal VLSI CircuitsKluwer Academic Publishers 2000
bull M Abramovici M A Breuer and A D Friedman Digital Systems Testing and Testable Design Computer Science Press New York 1990
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 3
「DIP概論」- IP Testing
Outline (12)
bull Introductionbull Fault Modelsbull Fault Simulationbull Test Generation (TG)bull Design for Testability (DFT) bull Advanced Scan Concepts
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 4
「DIP概論」- IP Testing
Outline (22)
bull Compression Techniquesbull Built-In Self-Test (BIST)bull Boundary-Scan Testingbull Memory Testingbull SOC Testing
Chapter 1
Introduction
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 6
「DIP概論」- IP Testing
VLSI Development FlowDetermine specification
Design the circuit
Verify the design
Develop the test procedure
Manufacture the circuit
Test the manufactured circuit
Deliver to customers
Design Errors
TestPlans
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 7
「DIP概論」- IP Testing
Why Do Circuits Fail
bull Human design errorsbull Manufacturing defects bull Package defectsbull Field (Environment) failures
ndash Temperature humidity power etc
verifytest
testtest
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 8
「DIP概論」- IP Testing
Verification vs Testingbull Verification
ndash Check for the correctness of a designbull Simulation
ndash Performed oncebull Testing
ndash Check the correctness of the manufactured circuitndash Performed repeatedly
Verification Testinglogicsoft faults realhard faults
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 9
「DIP概論」- IP Testing
Why Testing
bull Detect and eliminate (hard-)faulty circuits
Vdd
10
00
0
0
fault-free circuit faulty circuit
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 10
「DIP概論」- IP Testing
How to Do Testing
Circuit Under Test
(CUT)
Test Pattern Generator
(TPG)
Output Response Analyzer(ORA)
test patterns T
outputresponses R
GoodBad
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 11
「DIP概論」- IP Testing
Related Terminologies in Testing
bull Diagnosisndash Depict the faulty sites
bull Reliabilityndash Tell whether a ldquogoodrdquo circuit will work after
some time
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 12
「DIP概論」- IP Testing
Importance of Testing
N the number of transistors in a circuit (chip)p the probability that a transistor is faultyPf the probability that the chip is faulty
Pf = 1-(1-p)N
If p = 10-6 and N= 106
Pf = 632
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 13
「DIP概論」- IP Testing
Key Issues in Testing
Circuit Under Test
(CUT)
Test Pattern Generator
(TPG)
Output Response Analyzer(ORA)
test patterns T
outputresponses R
Fault Modeling Design for Testability
Test GenerationProblem
Good if R = RrsquoBad if R ne Rrsquoexpected
responses Rrsquo
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「DIP概論」- IP Testing
Circuit Modeling
bull Describe the behavior of circuitsndash Behavior modelndash RTL modelndash Gate level modelndash helliphellip
clocks (edgelevel-sensitive)delaytiming
algorithms
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 15
「DIP概論」- IP Testing
Fault Modeling
bull Describe the effects of physical faultsbull Fault model requirements
ndash Adequately represent actual faultsndash High coverage against physical faultsndash Well-behavedndash Simple enough to use in practice
bull Eg Fault simulation test generation
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 16
「DIP概論」- IP Testing
Fault Modelsbull Single stuck-at fault model
ndash Any single line x is stuck at 0 or 1bull Multiple stuck-at fault model
ndash Several lines x are stuck at 0 or 1bull Delay fault model
ndash Delay of a single path is changedbull Bridging fault model
ndash Signals x and y become AND(x y) or OR(x y)bull helliphellip
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 17
「DIP概論」- IP Testing
Single Stuck-at Fault Model (12)
bull Depict that ldquoone single linerdquo is permanently stuck at 1 or 0
EA
B
C
D F
G
A s-a-1A s-a-0E s-a-1E s-a-0
B s-a-1B s-a-0F s-a-1F s-a-0
C s-a-1C s-a-0G s-a-1G s-a-0
D s-a-1D s-a-0
14 faults
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 18
「DIP概論」- IP Testing
Single Stuck-at Fault Model (22)bull Advantages
ndash Match the gate level and are well-behavedndash The number of possible faults is relatively smallndash Tests for single stuck-at faults give good coverage of
permanent faultsbull Disadvantages
ndash Dose not account for some physical fault effectsndash Few physical faults behave exactly like single-at faults
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 19
「DIP概論」- IP Testing
Detectability of Faults
bull A fault f is said to be detectable if there exists a test vector x such that Cf(x) ne C(x) ie f is ldquodetectedrdquo by x
Vdd
10
00
0
0
fault-free circuit C fault f is detected by (00)
xf s-a-1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 20
「DIP概論」- IP Testing
Fault Coverage (FC)FC =
the size of fault listnumber of detected faults
CA
B
6 faultsA0 A1 B0 B1 C0 C1
test vector set detected faults FC(0 0)(0 1)(1 1)(0 0) (1 1)(1 0) (0 1) (1 1)
C1A1 C1A0 B0 C0A0 B0 C0 C1ALL
1667333350006667
10000
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 21
「DIP概論」- IP Testing
Testing QualityIC
FabricationYield(Y)
Rejected Parts
Shipped PartsDefect Level(DL)
bull Yield (Y) fraction of good partsbull Defect Level (DL) fraction of shipped parts that are defectivebull Quality of shipped parts is a function of Y and FC
DL = 1 ndash Y (1 - FC)
Testing
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「DIP概論」- IP Testing
Circuit Simulationbull Determine how a good circuit should work
ndash Given input vectors determine the normal circuit output responses
EA
B
C
D F
G
1
10
0
01
1
Simulation under the input 1 0 0 0
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「DIP概論」- IP Testing
Fault Simulation (12)
bull Determine the behavior of faulty circuitsE s-a-0 A
B
C
D F
G
1
100
0
01
10
x
Simulation under the input 1 0 0 0 with fault E s-a-0
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「DIP概論」- IP Testing
Fault Simulation (22)
bull Given a test vector determine all faults that are detected by this test vector
CA
B 1
10
Test vector (1 1) detects A0 B0 C1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 25
「DIP概論」- IP Testing
Test Generation (12)
bull Given a fault identify a test vector to detect this fault
A
B
C
D s-a-0
E
F
x
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 26
「DIP概論」- IP Testing
Test Generation (22)
bull Sensitizationndash To detect D s-a-0 D must be set to 1
ie A = B = 1bull Propagation
ndash To propagate the fault effect to the output F Emust be set to 1 ie C = 0
Test vector for D s-a-0 is 1 1 0
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 27
「DIP概論」- IP Testing
Automatic Test Pattern Generation (ATPG) (12)
bull Given a circuit identify a set of test vectors to detect all the detectable faults under the considered fault models
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 28
「DIP概論」- IP Testing
Automatic Test Pattern Generation (ATPG) (22)a circuit and the fault list
more fulats
select a fault
test generation
fault simulation
fault dropping
exit
Yes
No
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「DIP概論」- IP Testing
Difficulties in Test Generation (12)
bull Reconvergent fanout
A
B
C
D s-a-1
E
F
x
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 30
「DIP概論」- IP Testing
Difficulties in Test Generation (22)bull Sequential test generation
combinational circuit
D
clk
Q
x The fault effect cannot be observed at POs
PIs POs
The test patterns cannotbe generated at PIs
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 31
「DIP概論」- IP Testing
Advanced Test GenerationFC
100
of test patterns
Pseudorandom Test Pattern Generation
Deterministic Test Pattern Generation
Design for Testability (DFT)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 32
「DIP概論」- IP Testing
Testing Costs
bull Test software developmentndash Automatic test pattern generator (ATPG)ndash Fault simulation and other debugging policies
bull Design for testability (DFT)ndash Chip area overhead ie yield lossndash Performance overhead ie degradation
bull Automatic test equipments (ATEs)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 33
「DIP概論」- IP Testing
Difficulties in Testing
bull Some real faults are too complex to modelbull Most testing problems are NP-completebull IO access is limitedbull ATEs are expensive
Testing is rarely complete (FC lt 100)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 34
「DIP概論」- IP Testing
The Goals of Testingbull Detect all expected faults (high fault coverage)bull Diagnose to the smallest replaceablerepairable
component (high fault resolution)bull Fast and low-cost test generationbull Fast and low-cost test applicationbull Efficient response comparisonbull High degree of automationbull Low penalties in hardware overheadperformance
Chapter 2
Fault Models
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 36
「DIP概論」- IP Testing
Faults and Errors
bull Faultsndash Physical defects within a circuit or a systemndash May or may not cause the circuit to fail
bull Errorsndash Manifestation of faults that results in incorrect
circuit or system outputs or statesndash Caused by faults
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 37
「DIP概論」- IP Testing
Failures
bull Deviation of a circuit or a system from its specified behaviorndash Fails to do what it should do ndash Caused by errors
bull Faults Errors and Failures
Faults rArr Errors rArr Failures
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「DIP概論」- IP Testing
Why Model Faultsbull Identify target faults and describe their
effectsbull Limit the scope of test generation
ndash Create test patterns only for the modeled faultsbull Make analysis possible
ndash Compute the fault coverage for specific test patterns
ndash Associate specific faults with specific test patterns
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 39
「DIP概論」- IP Testing
Fault Modelsbull Stuck-at faultsbull Bridging faultsbull PLA faultsbull Transistor stuck-onopen faultsbull Delay faultsbull Functional faultsbull State transition faultsbull Memory faults
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「DIP概論」- IP Testing
Stuck-at Faultsbull Single stuck-at fault model
ndash Only a single line is permanently set to either 0 or 1
bull Multiple stuck-at fault modelndash Several stuck-at faults occur at the same time
bull For a circuit with k linesndash There are 2k single stuck-at faultsndash There are 3k-1 multiple stuck-at faults
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 41
「DIP概論」- IP Testing
Why Single Stuck-at Fault Model (12)
bull Complexity is greatly reducedndash Many different physical defects may be
modeled by the same logical stuck-at faultsbull Technology independent
ndash Can be applied to TTL ECL CMOS etcbull Design style independent
ndash Can be applied to gate arrays standard cells full-custom description
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 42
「DIP概論」- IP Testing
Why Single Stuck-at Fault Model (22)
bull The test patterns derived for single stuck-at faults are still valid for most defects even not accurately model some other physical defects
bull Single stuck-at tests cover a large percentage of multiple stuck-at faults
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 43
「DIP概論」- IP Testing
Bridging Faults (12)
bull Two or more normally distinct points(lines) are shorted togetherndash Logic effect depends on technology
bull Wired-AND for TTLbull Wired-OR for ECL
TTL Transistor-Transistor Logic
ECL Emitter-Coupled Logic
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 44
「DIP概論」- IP Testing
Bridging Faults (22)bull Wired-AND for TTL bull Wired-OR for ECL
A
B
f
g
A
B
f
g
A
B
f
g
A
B
f
g
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 45
「DIP概論」- IP Testing
PLA Faults
bull Stuck-at faults on inputs and outputsbull Crosspoint faults
ndash MissingExtrabull Bridging faults
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 46
「DIP概論」- IP Testing
Missing Crosspoint Faults in PLAbull Missing crosspoint in the AND plane
ndash Growth faultbull Missing crosspoint in the OR plane
ndash Disapperance fault
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 47
「DIP概論」- IP Testing
Extra Crosspoint Faults in PLAbull Extra crosspoint in the AND plane
ndash Shrinkage faultbull Extra crosspoint in the OR plane
ndash Appearance fault
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 48
「DIP概論」- IP Testing
Transistor Stuck-On Faults (12)
bull Also referred as stuck-short faults
stuck-on
0
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 49
「DIP概論」- IP Testing
Transistor Stuck-On Faults (22)
bull May cause ambiguous logic levelsndash Depend on the relative impedances of the pull-
up and pull-down networksbull Quiescent current may be increased called
IDDQ fault
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 50
「DIP概論」- IP Testing
Transistor Stuck-Open Faults (12)
bull May cause output floating(high impedance)
stuck-open
0 Z
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 51
「DIP概論」- IP Testing
Transistor Stuck-Open Faults (22)
bull Turn the circuit into a sequential circuitndash Stuck-open faults require two-vector test
patterns
stuck-open
10 0100
two-vector test pattern
fault-free response
fault response
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 52
「DIP概論」- IP Testing
Gate Delay Faults (12)bull Slow to rise or fall
X X
R
X is slow to rise when channel resistance R is abnormally high
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 53
「DIP概論」- IP Testing
Gate Delay Faults (22)bull Detectability of gate delay faults
ndash May not be detected
slow
critical path
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 54
「DIP概論」- IP Testing
Path Delay Faultsbull Propagation delay of a path exceeds the
clock intervalbull The number of paths grows exponentially
with the number of gates
XY
XY
the clock interval
propagation delay
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 55
「DIP概論」- IP Testing
Functional Faultsbull Behavioral faults
ndash Fault effects are modeled at a higher level for modules such as
bull Decodersbull Multiplexersbull Addersbull Countersbull RAMsbull ROMs
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 56
「DIP概論」- IP Testing
An Example of Functional Faultsbull Decoder
ndash f(LiLj) instead of line Li line Lj is selectedndash f(LiLi+Lj) in addition to Li Lj is selectedndash f(Li0) none of the lines are selected
DecoderLi
Lj
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 57
「DIP概論」- IP Testing
State Transition Graph(STG)bull Each state transition is associated with a 4-
tuple (source input output destination state)
S1
S3S2
I1O1 I2O2
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 58
「DIP概論」- IP Testing
Single State Transition Faults
bull A fault causes a single state transition to a wrong destination state
S1
S3S2
IO IO
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 59
「DIP概論」- IP Testing
Memory Faults (12)
bull Parametric faultsndash Change the values of electrical parameters of
active or passive devices from their normal or expected values
bull Output levelsbull Power Consumptionbull Noise marginbull Data retention time
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 60
「DIP概論」- IP Testing
Memory Faults (22)
bull Functional faultsndash Stuck faults in address register data register
and address decoderndash Cell stuck faultsndash Cell coupling faultsndash Pattern sensitive faults
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 61
「DIP概論」- IP Testing
Coupling Faults
bull A transition in memory bit i causes an unwanted change in memory bit j
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 62
「DIP概論」- IP Testing
Pattern Sensitive Faultsbull The presence of a faulty signal depends on
the signal values of the nearby pointsndash Most common in DRAM
0 0 00 d b0 a 0
a = b = 0 rArr d = 0 prevent writing a 1 into da = b = 1 rArr d = 1 prevent writing a 0 into d
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 63
「DIP概論」- IP Testing
Fault Detectionbull Let z BnrarrB A test pattern t detects a fault f
iff z(t)opluszf(t) = 1x1
x2
x3
z1
z2
f s-a-1 z1 = x1 x2
z2 = x2 x3
z1f = x1
z2 f= x2 x3
The test pattern 100 detects f because z1(100) = 0while z1f(100) = 1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 64
「DIP概論」- IP Testing
Sensitization
bull Given a test pattern t a line is said to ldquobe sensitized to a fault f by trdquo if its normal value is changed in the presence of f
bull A path composed of sensitized lines is called ldquoa sensitized pathrdquo
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 65
「DIP概論」- IP Testing
Detectability
bull A fault f is said to be detectable if there exists a test pattern t that detects f otherwise f is a redundant fault
bull For a redundant fault f z(t) = zf(t)ndash No test pattern can simultaneously
sensitize(activate) f and create a sensitized path to a primary output(PO)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 66
「DIP概論」- IP Testing
Redundant Faultsbull G1 stuck-at-0 fault is redundant
ndash Redundant faults do not change the function of the circuit
ndash The related circuit can be removed to simplify the circuit
1
s-a-0G1
1
1
00
0
10a
b
c
z
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 67
「DIP概論」- IP Testing
Fault Collapsing
bull The process to reduce the number of the faults under consideration is known as fault collapsing
bull Why fault collapsingndash Save memory space and CPU time for fault
simulation and test generation
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 68
「DIP概論」- IP Testing
Fault Equivalencebull A test pattern t distinguishes between faults α and β iff zα(t) ne zβ(t)
bull Two faults α and β are said to be equivalent in a circuit iff zα(t) = zβ(t) for all tndash Denoted by αharr βndash No test patterns can distinguish between α and β
ndash Any test pattern which detects one of them detects all of them
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 69
「DIP概論」- IP Testing
Fault Equivalence of Primitive Gates (12)
bull NOTndash Input s-a-1 and output s-a-0 are equivalentndash Input s-a-0 and output s-a-1 are equivalent
bull ANDndash All s-a-0 are equivalent
bull ORndash All s-a-1 are equivalent
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 70
「DIP概論」- IP Testing
bull NANDndash All input s-a-0 and output s-a-1 are equivalent
bull NORndash All input s-a-1 and output s-a-0 are equivalent
Fault Equivalence of Primitive Gates (22)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 71
「DIP概論」- IP Testing
Equivalent Fault Collapsing (12)[Theorem 2-1] Under the single stuck-at faultmodel for an n-input primitive gate n+2instead of 2n+2 faults need to be considered
2n+2
n+1 n+1
equivalence
n+2cup
[Proof]
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 72
「DIP概論」- IP Testing
Equivalent Fault Collapsing (22)
s-a-0
s-a-1s-a-1
s-a-1
s-a-1s-a-1
s-a-1 s-a-0
s-a-0
s-a-0
s-a-0
s-a-0 s-a-0
s-a-1
s-a-1
s-a-0
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 73
「DIP概論」- IP Testing
Fault Dominancebull Let Tα be the set of all test patterns that
detect fault α We say that a fault βdominates fault α iff zα(t) = zβ(t) for all tisinTα
ndash Denoted by β rarr αndash No need to consider fault β for fault detection
Tα
Tβ
Tβ supeTα
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 74
「DIP概論」- IP Testing
Fault Dominance of Primitive Gatesbull AND
ndash Output s-a-1 dominates any input s-a-1bull OR
ndash Output s-a-0 dominates any input s-a-0bull NAND
ndash Output s-a-0 dominates any input s-a-1bull NOR
ndash Output s-a-1 dominates any input s-a-0
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 75
「DIP概論」- IP Testing
Dominated Fault Collapsing (12)[Theorem 2-2] Under the single stuck-at fault model for an n-input primitive gate only n+1faults need to be considered
2n+2
n+1 n+1
equivalencen+1
cup
[Proof]
n 1dominance
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 76
「DIP概論」- IP Testing
Dominated Fault Collapsing (22)
s-a-0
s-a-1s-a-1
s-a-1
s-a-1s-a-1
s-a-1 s-a-0
s-a-0
s-a-0
s-a-0
s-a-0 s-a-0
s-a-1
s-a-1
s-a-0
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 77
「DIP概論」- IP Testing
Prime Faultsbull α is a prime fault if every fault dominated
by α is also equivalent to αbull Representative set of prime faults(RSPF)
ndash A set consisting of exactly one prime fault from each equivalence class of prime faults
bull Achieve 100 fault coverage ndash Only generate the test set for RSPF
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 78
「DIP概論」- IP Testing
Checkpoints (13)
bull Primary inputs and fanout branches
[Theorem 2-3] Any test set which detects all single stuck-at faults on every check point will detect all single stuck-at faults
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 79
「DIP概論」- IP Testing
Checkpoints (23)
a
b
c
d
e
s-a-1s-a-1
s-a-1
s-a-1s-a-1
s-a-1
s-a-1
s-a-1s-a-0
s-a-0
s-a-0s-a-0
s-a-0
s-a-0s-a-0
s-a-0
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 80
「DIP概論」- IP Testing
Checkpoints (33)bull The set of checkpoint faults can be further
collapsed by using equivalence and dominance relations
a
b
c
d
e
10 checkpoint faultsa s-a-0 harr d s-a-0c s-a-0 harr e s-a-0b s-a-0 rarr d s-a-0b s-a-1 rarr d s-a-16 test patterns are enough
Chapter 3
Fault Simulation
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 82
「DIP概論」- IP Testing
Simulationbull True-value simulation
ndash Compute the responses for given inputtest patterns without injecting any faults in the circuit
bull For verifying the correctness of the design
bull Fault simulationndash Compute the responses for given inputtest
patterns with injecting considered faults in the circuit
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 83
「DIP概論」- IP Testing
Why Fault Simulation
bull To evaluate the quality of a test setndash In terms of fault coverage(FC)
bull To incorporate into ATPGndash Decrease the time for test pattern generation
bull To construct fault dictionary ndash For post-test diagnosis
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 84
「DIP概論」- IP Testing
Simulation Mechanisms
bull Compiled-code simulationndash Circuit is translated into the program where
each gate is executed for each patternbull Event-driven simulation
ndash Circuit structure and gate status are stored in a table and only those gates which are needed to be updated with a new pattern are processed
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 85
「DIP概論」- IP Testing
Compiled-Code Simulation (13)levelize circuit and produce compiled-codeinitialize data variables(flip-flops and memory)for every input pattern begin
set the primary inputs to the input pattern repeat until (steady-state or maximum iteration-count are reached)begin
execute compiled-codeupdate the associated data variables(flip-flop or memory)
endend
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 86
「DIP概論」- IP Testing
Compiled-Code Simulation (23)
bull The use of compiled-code simulation is usually limited into high-level designndash Since detailed timing or delay is almost
impossible to be simulated in the translated compiled-code
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 87
「DIP概論」- IP Testing
Compiled-Code Simulation (33)
D-FF
abc
d
e
f
Compiled-Code
d = a amp b amp cf = d | ee = f
Q D
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 88
「DIP概論」- IP Testing
Event-Driven Simulation (12)initialize simulation time t to 0while (event list is not empty) begin
for every event (i t) begin gate i changes at time tupdate the value of gate i schedule fanout gates of i in the event list if the associated value changes are expected
endadvance simulation time t
end
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 89
「DIP概論」- IP Testing
Event-Driven Simulation (22)1a
c
bd
e
f
g2
2
2
41
1 rarr0
0 rarr1
1 rarr0
0 rarr1
1 rarr0 rarr1
simulation time t event fanout
0 c = 0 d e
1
2 d = 1 e =0 f g
3
4 g = 0
5
6 f = 1 g
7
8 g = 1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 90
「DIP概論」- IP Testing
Logic Value Based Fault Simulationbull For functional faults such as single stuck-at
faults helliphellipndash Logic simulation on both fault-free and faulty
circuitsTest Patterns
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 91
「DIP概論」- IP Testing
Complexity of Fault Simulation
bull Suitable for single stuck-at fault modelbull Higher than logic simulation but much
lower than test pattern generationbull In reality the complexity can be reduced by
fault collapsing and advanced techniques
patterns faults gates
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 92
「DIP概論」- IP Testing
Characteristics of Fault Simulationbull Fault activities with respect to fault-free
circuit are often sparse both in time and in spacendash For example f1 is not activated by the given
pattern(time) while f2 affects only the lower part of the circuit(space)
f1 s-a-0
f2 s-a-0
0
1
1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 93
「DIP概論」- IP Testing
Efficiency of a Fault Simulator
bull Depend on its ability to exploit the sparse characteristics both in time and in space
人生最大的成就是從失敗中站起來證嚴法師靜思語
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 94
「DIP概論」- IP Testing
Classical Fault Simulation Techniques
bull Serial fault simulationbull Parallel fault simulationbull Deductive fault simulationbull Concurrent fault simulation
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 95
「DIP概論」- IP Testing
Serial Fault Simulation
bull The simplest algorithm for fault simulationndash Simulate the fault-free circuit for all input
patterns and save the outputs in a file(table)ndash Simulate one faulty circuit at a time until the
target fault is detected by some one test pattern or proven to be undetectable
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 96
「DIP概論」- IP Testing
Parallel Fault Simulation
bull Simulate faulty circuits in parallel with fault-free circuit by taking advantage of inherent parallel operation of computer wordsndash The number of circuits being processed
concurrently is limited by the word length wbull Each pass at most w-1 faulty circuit are processed
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 97
「DIP概論」- IP Testing
Example of Parallel Fault Simulation
0 0 0 0 0 1 0 0 1 0 1 1
1 1 1 1 1 1 0 1
1 1 0 1 1 1 0 0
0 1 0 0
1 0 0 1
1 1 1 1a
b
f
c
de
g
h
is-a-1
s-a-0
s-a-0
for fault-free circuitfor circuit with fault b s-a-1for circuit with fault f s-a-0for circuit with fault i s-a-0
rArr Faults f s-a-0 and i s-a-0 are detected by test pattern (a b f) = (1 0 1)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 98
「DIP概論」- IP Testing
Deductive Fault Simulation
bull Only the fault-free circuit is simulated (true-value simulation) ndash All signal values in each faulty circuit are
deduced from the fault-free circuit values and the circuit structure
bull Each signal is associated a list of faults in the circuit which can change the state of that line
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 99
「DIP概論」- IP Testing
Basic Fault List Propagation RulesInputs Output
a b cOutput Fault list
Lc
0 0 0 [La cap Lb] cup c1
[La cap Lb] cup c1
[La cap Lb] cup c1
[La cup Lb] cup c0
[La cup Lb] cup c1
[La cap Lb] cup c0
[La cap Lb] cup c0
[La cap Lb] cup c0
La cup c0
La cup c1
(1)0 1 0 (2)1 0 0 (3)1 1 1 (4)0 0 0 (5)0 1 1 (6)1 0 1 (7)1 1 1 (8)0 - 1 (9)
1 - 0 (10)
NOT
OR
AND
Gate Type
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 100
「DIP概論」- IP Testing
Example of Deductive Fault Simulation (12)ab
c 1 b0 c0
d 1 b0 d0
1 a0
1 b0
e 1 a0 b0 c0 e0
f 0 b0 d0 f1
Initially La = a0 and Lb = b0For the fanouts of b c and d Lc = b0 c0 and Ld = b0 d0
Le = [La cup Lc] cup e0 = a0 b0 c0 e0 by Rule (4)Lf = Ld cup f1 = b0 d0 f1 by Rule (10)
g
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 101
「DIP概論」- IP Testing
ab
g
1 a0
1 b1
e 1 a0 b0 c0 e0
f 0 b0 d0 f1
1 a0 c0 e0 g0
Lg = [Le cap Lf] cup g0 = a0 c0 e0 g0 by Rule (7)
c 1 b0 c0
d 1 b0 d0
Example of Deductive Fault Simulation (22)
rArr Faults a0 c0 e0 and g0 are detected by test pattern (a b) = (1 1)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 102
「DIP概論」- IP Testing
Concurrent Fault Simulation
bull Each gate retains a list of fault copies each of which stores the status of a fault to exhibit difference form the fault-free values
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 103
「DIP概論」- IP Testing
Example of Concurrent Fault Simulation
ab c
d g
1
1
e
f
1
11 1
1 0
0 1 0 1 1 1
b0 d0 f1
01 1
00
a0
01
1
b0
00
0
c0
01
1
d0
1
00
e0
01
1
f1
10
0
g0
1
a001 0
10 0
10 0
11 0
b0 c0 e0
rArr Faults a0 c0 e0 and g0 are detected by test pattern (a b) = (1 1)
1
0
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 104
「DIP概論」- IP Testing
Modern Fault Simulation Techniques
bull Parallel-Pattern Single-Fault Propagation (PPSFP)
bull Critical Path Tracing
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 105
「DIP概論」- IP Testing
PPSFP
bull Based on the serial fault simulation many patterns are simulated in parallel for fault-free and faulty circuits respectivelyndash The number of patterns is limited by the word
length wbull Each pass at most w patterns are processed
ndash The basis of all modern fault simulators
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 106
「DIP概論」- IP Testing
Example of PPSFPbull Consider fault f s-a-0 and four pattern p3 p2
p1 and p0
0 1 0 1 1 0 1 0
1 0 0 1
1 1 0 1
0 1 0 1
1 0 0 0
1 1 1 1a
b
f
c
de
g
h
i
s-a-0
p3 p2 p1 p0
0 0 0 00 0 0 0
0 1 0 1
rArr Fault f s-a-0 are detected by test pattern p3 (a b f) = (1 0 1)
(faulty values)1 0 0 1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 107
「DIP概論」- IP Testing
Sensitive Inputs
bull A gate input a is sensitive if complementing the value of a changes the value of the gate output
ab
1rarr0
1
c
a is sensitive
ab 0
0 c
a is not sensitive
1rarr0 0 rarr1
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「DIP概論」- IP Testing
Critical Pathsbull Let l(v) be the fault-free value of line l
under input pattern t We say that line l is critical with respect to t iff t detects the fault l s-a-l(v)
bull A gate input i is critical with respect to t if the gate output is critical and i is sensitive
bull A path consisting of only critical lines is said to be a critical path
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「DIP概論」- IP Testing
Critical Path Tracing
bull Two-step procedurendash Perform true-value simulation and identify
sensitive gate inputsndash Backtrace from POs to identify the critical lines
bull O(|G|) for fanout-free circuitsndash The fanout-free situation is very rare
bull Perform in fanout-free region and the stem faults are simulated by other methods mentioned earlier
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「DIP概論」- IP Testing
Example of Critical Path Tracing (12)
a
b
f
c
d e
g
h
i
1
0
11
1
0
1fanout-free region
sensitive input
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「DIP概論」- IP Testing
Example of Critical Path Tracing (22)
a
b
f
c
d e
g
h
i
1
0
11
1
0
1fanout-free region
sensitive inputcritical line
rArrFaults i0 h0 f0 e0 and d1 are detected by test pattern (a b f) = (1 0 1)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 112
「DIP概論」- IP Testing
Anomaly of Critical Path Tracinga
b
f
c
d e
g
h
i
1
0
11
1
0
1critical line
bull Stem criticality is hard to infer from branchesndash Eg Fault b s-a-1 is not detected by (a b f) = (1 0 1)
even though branches c and d are critical
stem
branch
branch
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「DIP概論」- IP Testing
Multiple Path Sensitizationa
b
f
c
d
g
h
i
1
1
1
1
1
1fanout-free region
sensitive inputcritical line
bull Both c and d are not critical but b is critical and bs-a-0 can be detected by (a b f) = (1 1 1)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 114
「DIP概論」- IP Testing
Summariesbull Does specific test patterns detect specific
faultsndash Serial fault simulationndash Parallel fault simulationndash PPSFP
bull Which faults does a specific test pattern detect (suitable for ATPG)ndash Deductive fault simulationndash Concurrent fault simulationndash Critical Path Tracing
Chapter 4
Test Generation (TG)
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「DIP概論」- IP Testing
Test Generation (TG) Methods
bull From truth tablebull Using Boolean equationbull Using Boolean differencebull From circuit structure
Impractical
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 117
「DIP概論」- IP Testing
TG from Truth Table
bull Based on the serial fault simulationndash Impractical
ab
c
f
α s-a-0abc f fα000 0 0001 0 0010 0 0011 0 0100 0 0101 1 1110 1 0111 1 1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 118
「DIP概論」- IP Testing
TG Using Boolean Equation
bull Based on the definition of detectability we have
Tα = (a b c) | f(a b c) oplus fα(a b c) = 1= (1 1 0)
bull High complexity
ab
c
f
α s-a-0
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 119
「DIP概論」- IP Testing
Boolean DifferenceThe Boolean difference of f(x) with respect to xi is
)()()( 1f0fdx
xdfii
i
oplus=
where fi(0) = (x1 hellip 0 hellip xn) and fi(1) = (x1 hellip 1 hellip xn)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 120
「DIP概論」- IP Testing
Physical Meaning of Boolean Difference
bull Find all the input combinations such that the change of xi will cause the change of f(x)
bull Relationship between TG and Boolean difference
x1xixn
fcircuit0 rarr 1
0 rarr1
1rarr0or x1
xixn
fcircuit1rarr 0
1 rarr0
0 rarr1or
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 121
「DIP概論」- IP Testing
Case 1 Faults are present at PIsab
c
f
cb0cb1f0fda
xdfaa +=++bull=oplus= )(1)()()(
The set of all tests for a s-a-1 is (a b c) | a(b + c) = (0 1 x) (0 x 1)The set of all tests for a s-a-0 is (a b c) | a(b + c) = (1 1 x) (1 x 1)
TG Using Boolean Difference (12)
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「DIP概論」- IP Testing
TG Using Boolean Difference (22)Case 2 Faults are present at internal lines
ab
c
f
h = ab
caacac1f0fdh
xdfachf hh +=bull+bull=oplus=+= 11)()()(
The set of all tests for h s-a-1 is (a b c) | h(a + c) = (0 x x) (x 0 0)The set of all tests for h s-a-0 is (a b c) | h(a + c) = (1 1 0)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 123
「DIP概論」- IP Testing
Controlling and Inversion Valuesbull The value c of an input is said to be controlling
if it determines the value of the gate output regardless of the values of the other inputs then the output value is c oplus i where i for the inversion
bull The basic gates can be characterized by the two parametersndash The controlling value cndash The inversion value i
c iAND 0 0OR 1 0NAND 0 1NOR 1 1
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「DIP概論」- IP Testing
Composite Logic Values and Operations
vvf symbol
00 0
11 1
10 D
01 D
AND 0 1 D0 0
DD0x
1DDx
00000
D x0 0
D0Dx
10xxx
DDx x
OR 0 1 D1 D
1D1x
1111
01DDx
D x0 D
11Dx
1x1xx
DDx x
5-valued operations
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 125
「DIP概論」- IP Testing
Line Justification (LJ)bull Set PIs to some values such that the specific
line has the predetermined value ab
c
f
10 = D
0
1
1
0
s-a-0D
h
ndash Eg Set both a and b to 1 h has the desired value 1 to activate the fault s-a-0 additionally set c to 0 the fault effect will be propagated to f
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 126
「DIP概論」- IP Testing
Justify(l val)Justify(l val)beginset l to valif l is a PI then returnc = controlling value of li = inversion of linval = val oplus i
if(inval = c)then for every input j of l
Justify(j inval)else
beginselect one input j of lJustify(j inval)
endend
Line justification for a fanout-free circuit
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「DIP概論」- IP Testing
TG from Circuit Structure
bull Two basic goalsndash Fault activation (FA)ndash Fault propagation (FP)
rArrLine justification (LJ)
ab
c
f
10 = D larr fault activation (FA)
0 larr fault propagation (FP)
1
1
0
s-a-0D
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 128
「DIP概論」- IP Testing
TG for l s-a-vTG(l v)begin
set all values to xJustify(l v) FA if v = 0 then Propagate(l D) FP else Propagate(l D)
end
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 129
「DIP概論」- IP Testing
Propagate(l err)Propagate(l err) err is D or D beginset l to errif l is PO then returnk = the fanout of l c = controlling value of ki = inversion of kfor every input j of k other than lJustify(j c)
Propagate(k err oplus i)end
Error propagation for a fanout-free circuit
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 130
「DIP概論」- IP Testing
Implication
bull Compute the values that can be uniquelydetermined and check for their consistency with the previously determined ones
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 131
「DIP概論」- IP Testing
Decision Trees
bull Decision Treesndash Consist of decision nodes for problems that the
algorithm is attempting to solvendash A branch leaving a decision node corresponds
to a decisionndash A SUCCESS terminal node labeled S
represents finding a test ndash A FAILURE terminal node labeled F
indicates the detection of an inconsistency
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 132
「DIP概論」- IP Testing
Backtracking
bull A systematic exploration of the complete space of possible solutions and recovery from incorrect decisions recovery involves restoring the state of the computation to the state existing before the incorrect decision
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 133
「DIP概論」- IP Testing
Backtracking of Incorrect Decisions
0xxx
ad
d = 0
F F
a = 0 a = 1b = 0
a = 1b = 1c = 0
bc
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 134
「DIP概論」- IP Testing
bull A FA problem is a LJ problembull A FP problem
ndash Select a FP path to a PO rArr decisionsndash Once the FP path is selected rArr a set of LJ
problemsbull A LJ problem is an either implication or
decision problem
Common Concepts of Structural TG (12)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 135
「DIP概論」- IP Testing
Common Concepts of Structural TG (22)
bull Incorrect decision(inconsistency) rArr Backtrack and make another decisions
bull Once the fault effect is propagated to a PO and all lines to be justified are justified the test pattern is generated otherwise the decision process is repeatedly until all possible decisions have been tried
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 136
「DIP概論」- IP Testing
A Simple Example of TG (12)
s-a-1
abc
d
e
G2
G1
G3
G5
G4
G6
f1
f2
bull FA rArr G1 = D rArr a = 1 b = 1 c = 1 rArr G2 = 0 (rArr G5 = 0) G3 = 0
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 137
「DIP概論」- IP Testing
A Simple Example of TG (22)bull FP through G5 or G6 (the last page)
ndash Decision through G5rArr G2 = 1 inconsistency rArr backtracking
ndash Decision through G6rArr G4 = 1 rArr e = 0 rArr SUCCESS
rArrThe resulted test pattern is 111x0 G5 G6
F S
G5 G6
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 138
「DIP概論」- IP Testing
Advanced Example (14)
s-a-1
ab
cd
efh
k
l
mno
p
q
r s
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 139
「DIP概論」- IP Testing
Advanced Example (24)
bull FA rArr h = D
bull FPrArr e = 1(rArr o = 0) f = 1 rArr q = 1 r = 1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 140
「DIP概論」- IP Testing
Advanced Example (34)rArr Justify q = 1 rArr l = 1 or k = 1
ndash Decision l = 1rArr c = 1 d = 1 rArr m = 0 n = 0 rArr r = 0rArr inconsistency rArr backtracking
ndash Decision k = 1rArr a = 1 b = 1
rArr Justify r = 1 rArr m = 1 or n = 1rarr Decision m = 1
rArr c = 0 rArr SUCCESSrarr Decision n = 1
rArr d = 0 rArr SUCCESS
rArrThe resulted test is pattern 110x110 or 11x0110
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 141
「DIP概論」- IP Testing
Advanced Example (44)
q = 1
F
l = 1 l = 0 k = 1
r = 1
S
m = 1
S
n = 1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 142
「DIP概論」- IP Testing
A Generic TG AlgorithmSolve( )beginif Imply_and_check( ) = FAILUREthen return FAILURE
if(error at PO and all lines are justified)then return SUCCESS
if(no error can be propagated to a PO)then return FAILURE
select an unsolved problemrepeat
begin backtracking select one untried way to solve itif solve( ) = SUCCESS then
return SUCCESSend
until all ways to solve it have been triedreturn FAILURE
end
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 143
「DIP概論」- IP Testing
D-frontier And J-frontier
bull D-frontierndash The set of all gates whose output value is
currently x but have one or more fault signals on their inputs
bull J-frontierndash The set of all gates whose output value is
known but is not implied by their input values
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 144
「DIP概論」- IP Testing
Example of D-frontier
bull Initially the D-frontier is G6
s-a-1
abc
d
e
G2
G1
G3
G5
G4
G6
f1
f2
D
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 145
「DIP概論」- IP Testing
Example of J-frontierbull Initially the J-frontier is q = 1 r = 1
s-a-1
ab
cd
efh
k
l
mno
p
q
r s
1
1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 146
「DIP概論」- IP Testing
LocalGlobal Implication
bull Local implicationndash Propagate values from one line to its immediate
inputs or outputsbull Global implication
ndash Propagation of values involves a larger area of the circuit and reconvergent fanout
bull Case analysis the SOCRATES system
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 147
「DIP概論」- IP Testing
Local Implication (Backward)
larr 1x
x
larr 0x
1
larr 0x
xlarr 1
x
x
Before
J-frontier = hellip
After1larr 1
larr 1
0larr 0
1
0x
xJ-frontier = hellip a
11
1 rarr
a
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 148
「DIP概論」- IP Testing
Local Implication (Forward) (12)bull Binary values
x
Before0 rarr x
1
x
0 rarr
x
0a
1 rarr
1 rarr
x
0a
D
1 rarr
xa
D
0 rarr
xa
J-frontier = hellip a
J-frontier = hellip a
D-frontier = hellip a
D-frontier = hellip a
x
After0
10
x
0
1
1
larr 0
0
D
1 aD
0 a
J-frontier = hellip
J-frontier = hellip
D-frontier = hellip
D-frontier = hellip
0 rarr
1 rarr
D rarr
0 rarr
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 149
「DIP概論」- IP Testing
Local Implication (Forward) (22)bull Error values
Before After
x
x1D
D-frontier = hellip a
x
1
D-frontier = hellipa a
D rarr x
Dx a D-frontier = hellip a
D rarr D rarr
D rarrx D
DD rarr
D
DD-frontier = hellip a D-frontier = hellip
aD rarrx D
D0 rarr
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 150
「DIP概論」- IP Testing
Unique D-drive
Before
xx a D-frontier = hellip aD
After
D rarr
larr 1D-frontier = hellip
D
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 151
「DIP概論」- IP Testing
x-path
bull A path is said to be a x-path if all its lines have value x
[Theorem 4-1] Let G be a gate on D-frontier The error(s) on the input(s) of G can be propagated to a PO Z if there exists at least one x-path between G and Z
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 152
「DIP概論」- IP Testing
Error-Propagation Look-Ahead (12)
DD
x
x x
x
x
00
11
bull By Theorem 4-1 none of the fault effects can be observed on any POs
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 153
「DIP概論」- IP Testing
Error-Propagation Look-Ahead (22)
bull Using the error-propagation look-ahead technique we may prune the decision tree by recognizing states from which any further decisions will lead to a failure
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 154
「DIP概論」- IP Testing
D-Algorithm
bull FP is always given priority over LJbull Propagate fault effects on several
reconvergent paths referred to as ldquomultiple-path sensitizationrdquondash Some faults cannot be detected by sensitizing
only a single path
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 155
「DIP概論」- IP Testing
The D-algorithm Implementation (12)D-alg( )begin Implicationsif Imply_and_check( ) = FAILURE
then return FAILURE
if(error not at PO) thenbeginif D-frontier = empty
then return FAILURE
repeat beginselect an untried gate G from
D-frontier Decisionsc = controlling value of Gassign c to every input of G with
value xif D-alg( ) = SUCCESS
then return SUCCESSend
until all gates from D-frontier have been tried
return FAILUREend if (error not at PO)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 156
「DIP概論」- IP Testing
if J-frontier = emptythen return SUCCESS
select a gate G from the J-frontierc = controlling value of G
repeat begin Decisionsselect an input j of G with value xassign c to jif D-alg( ) = SUCCESS
then return SUCCESSassign c to j
end
until all inputs of G are specifiedreturn FAILURE
end D-alg
The D-algorithm Implementation (22)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 157
「DIP概論」- IP Testing
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011 D
1
Example of D-Algorithm (0113)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 158
「DIP概論」- IP Testing
Example of D-Algorithm (0213)bull Value computation (16)
Decisions Implications Commentsa = 0 Fault activationh = 1b = 1 Unique D-driven through gc = 1g = D D-frontier = i k m
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 159
「DIP概論」- IP Testing
Example of D-Algorithm (0313)bull Value computation (26)
Decisions Implications Commentsd = 1 Fault propagation through i
Propagate fault effects on i = Dd = 0
a single path D-frontier = k m n
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 160
「DIP概論」- IP Testing
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011 D
1D
01
Example of D-Algorithm (0413)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 161
「DIP概論」- IP Testing
bull Value computation (36)Decisions Implications Comments
j = 1 Fault propagation through nk = 1 Propagate fault effects onl = 1 a single path m = 1
n = De = 0e = 1k = D Contradiction
Example of D-Algorithm (0513)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 162
「DIP概論」- IP Testing
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011 D
1D
01
01
DContradiction
Example of D-Algorithm (0613)
D
1
11
1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 163
「DIP概論」- IP Testing
bull Value computation (46)Decisions Implications Comments
e = 1 Fault propagation through kk = D Propagate fault effects on e = 0 two paths j = 1 D-frontier = m n
Example of D-Algorithm (0713)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 164
「DIP概論」- IP Testing
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011 D
1D
01
D
10 1
Example of D-Algorithm (0813)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 165
「DIP概論」- IP Testing
bull Value computation (56)Decisions Implications Comments
l = 1 Fault propagation through nm = 1 Propagate fault effects on
n= D two reconvergent paths f = 0
f = 1
m =D Contradiction
Example of D-Algorithm (0913)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 166
「DIP概論」- IP Testing
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011 D
1D
01
D
10 1
01
D
Contradiction
Example of D-Algorithm (1013)
D
1
1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 167
「DIP概論」- IP Testing
bull Value computation (66)Decisions Implications Comments
f = 1 Fault propagation through mm = D Propagate fault effects onf = 0 three paths l = 1n= D Fault effects on POrsquos
Example of D-Algorithm (1113)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 168
「DIP概論」- IP Testing
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011 D
1D
01
D
10 1
10
D
1
D
Example of D-Algorithm (1213)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 169
「DIP概論」- IP Testing
bull Decision treendash Nodes the associated D-frontierndash Branches the taken decision ie the gate selected from the
D-frontieri k m
k m n
m nF
F S
i
n k
n m
Two times of backtracking
Example of D-Algorithm (1313)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 170
「DIP概論」- IP Testing
Partial Specification of The x Valuebull For a ldquototally unspecifiedrdquo composite value x
both v and vf are unknownndash x for 0 1 D D
bull For a ldquopartially specifiedrdquo composite value x v is binary and vf is unknown(u) vice versandash 0u for 0 D ndash 1u for D 1ndash u0 for 0 Dndash u1 for D 1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 171
「DIP概論」- IP Testing
9-V Algorithmbull Similar to D-algorithm except that the
considered logic values are 0 1 D D 0u 1u u0 u1 uu (9-value)
bull Drive a D(D) through a gate G with controlling value c the values it assigns to the unspecified inputs of G correspond to the set c D(c D)
bull ub or bu (b is binary) at a PI is immediately transformed to bb
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 172
「DIP概論」- IP Testing
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011 D
1
Example of 9-V Algorithm (17)
u1
u1
u1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 173
「DIP概論」- IP Testing
Example of 9-V Algorithm (27)
Decisions Implications Commentsa = 0 Fault activationh = 1b = 1 Unique D-driven through gc = 1g = Di = u1k = u1m = u1 D-frontier = i k m
bullV
alue computation (13)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 174
「DIP概論」- IP Testing
Example of 9-V Algorithm (37)
Decisions Implications Commentsd = 1 Fault propagation through i
i = Dd = 0
n = 1u D-frontier = k m n
bullV
alue computation (23)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 175
「DIP概論」- IP Testing
Example of 9-V Algorithm (47)
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011 D
1
u1
1
0
D
1u
u1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 176
「DIP概論」- IP Testing
Example of 9-V Algorithm (57)
bullV
alue computation (33)
Decisions Implications Commentsl = u1 Fault propagation through nj = u1
n = Df = u0f = 1f = 0
e = u0
e = 1e = 0k = D
m = D
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 177
「DIP概論」- IP Testing
0
1D
Example of 9-V Algorithm (67)
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011 D
1
u1
u1
1
0
D
D0
1D
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 178
「DIP概論」- IP Testing
Example of 9-V Algorithm (77)bull Decision tree
ndash Nodes the associated D-frontierndash Branches the taken decision ie the gate selected from the
D-frontier
i k m
k m n
S
i
n
No backtracking
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 179
「DIP概論」- IP Testing
D-Algorithm vs 9-V Algorithm
bull Whenever there are k possible paths for FPndash D-algorithm may eventually try all the 2k-1
combinations of pathsndash 9-V algorithm tries only one path at a time but
without precluding simultaneous FP on the other k-1 paths
bull Enumerate at most k ways of FP
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 180
「DIP概論」- IP Testing
Inversion Parity
bull In circuits composed only of AND OR NAND NOR and NOT gates we can define the ldquoinversion parityrdquo of a path as the number taken modulo 2 of the inverting gates (NAND NOR and NOT) along that path
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 181
「DIP概論」- IP Testing
Path-Oriented DEcision Making (PODEM)bull PODEM allows the value assignments for LJ
problems only on PIs ie backtracking can occur only on PIs ndash Treat a value vk to be justified for line k as an
objective (k vk)ndash Use the backtracing procedure to map the object
into a PI assignment that ldquois likely to contributerdquo to achieve the objective
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 182
「DIP概論」- IP Testing
BacktracingObjective (k vk)Step 1 Find a x-path from line k to a PI say aStep 2 Count the inversion parity of the pathStep 3 If the inversion parity is even then
return (a vk) otherwise (a vk)
Note No non-PI values are assigned during backtracing ie these values are assigned only by simulating PI assignments (implications)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 183
「DIP概論」- IP Testing
The Backtracing ImplementationBacktrace(k vk) map objective into PI assignment beginv = vk
while k is a gate output begin
i = inversion of kselect an input j of k with value xv = v oplus ik = j
endreturn (k v) k is a PI
end
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 184
「DIP概論」- IP Testing
Example of Backtracing ProcedureObjective (f 1)
fd
e
ca
bx
x
x
xxx
fd
e
ca
bx
1
x
10x
The first time of backtracing
fd
e
ca
bx
1
x1
0x
fd
e
ca
b1
1
0
101
The second time of backtracing
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 185
「DIP概論」- IP Testing
Choosing of Objectives (12)
bull In PODEM the order of the objectives being considered is as follows1 The objectives for FA2 Repeatedly select a gate G from the D-frontier
(until some fault effect is at a PO or the D-frontier is empty) and consider the input with x value as an objective
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 186
「DIP概論」- IP Testing
Choosing of Objectives (22)
Objective( )being
the target fault is l s-a-v if (the value of l is x) then return (l v)select a gate G from the D-frontierselect an input j of G with value xc = controlling value of G return (j c)
end
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 187
「DIP概論」- IP Testing
The PODEM ImplementationPODEM( ) beginif (error at PO) then return SUCCESSif (test not possible) then return FAILURE(k vk) = Objective( )(j vj) = Backtrace(k vk) j is a PI Imply(j vj)if PODEM( ) = SUCCESS then return SUCCESSImply(j vj) reverse decision if PODEM( ) = SUCCESS then return SUCCESSImply(j x)return FAILURE
end
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 188
「DIP概論」- IP Testing
Example 1 of PODEM (18)
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011
11 0
D
D
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 189
「DIP概論」- IP Testing
Example 1 of PODEM (28)bull Value computation (13)
Objective PI Assignment Implications D-frontier Comments
(a 0) a = 0 h = 1 g
(b 1) b = 1 g(c 1) c = 1 g = D i k m
(d 1) d = 1 d = 0
i = D k m n
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 190
「DIP概論」- IP Testing
Example 1 of PODEM (38)bull Value computation (23)Objective PI Assignment Implications D-frontier Comments
(k 1) e = 0 e = 1j =0
k =1n = 1 m x-path check fails
e = 1 e = 0 reversal
j = 1k = D m n
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 191
「DIP概論」- IP Testing
Example 1 of PODEM (48)
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011
11 0
00
1
D
D
11
x-path(to PO)check failsrArr Backtracking
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 192
「DIP概論」- IP Testing
Example 1 of PODEM (58)
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011
11 0
11
0
D
D
1D
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 193
「DIP概論」- IP Testing
Example 1 of PODEM (68)bull Value computation (33)Objective PI Assignment Implications D-frontier Comments
(l 1) f = 1 f = 0l = 1
m = Dn = D
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 194
「DIP概論」- IP Testing
Example 1 of PODEM (78)
abc
s-a-1g
d
e
f
h
i
j
k
l
m
n
d
e
f
011
11 0
11
0
D
D
11 0
D
D
D
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 195
「DIP概論」- IP Testing
Example 1 of PODEM (88)bull Decision tree
ndash Nodes the PIs selected to be assigned valuesndash Branches the value assigned to the PI
a0b1
c1d1
e0F f1
S
1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 196
「DIP概論」- IP Testing
Features of PODEMbull PODEM examines all possible input
patterns implicitly but exhaustively as tests for a given fault ie a complete TG
bull PODEM does not needndash Consistency checkndash The J-frontierndash Backward implications
bull Generally faster than D-algorithm
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 197
「DIP概論」- IP Testing
A More Intelligent Backtracing (12)bull To guide the backtracing process of PODEM
controllability for each line is measuredndash CY1(a) the probability that line a has a value 1ndash CY0(a) the probability that line a has a value 0
bull Eg f = ab assume CY1(a) = CY0(a) = CY1(b) = CY0(b) = 05ndash CY1(f) = CY1(a) CY1(b) = 025ndash CY0(f) = 1 - CY1(f) = 075
ab f
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 198
「DIP概論」- IP Testing
bull How to guide the backtracing process using controllabilityndash Principle 1 Among several unsolved problems first
attack the hardest onendash Principle 2 Among several solutions of a problem
first try to the easiest onebull Eg
ndash Objective (c 1) rArr Choose path c-a to backtracendash Objective (c 0) rArr Choose path c-a to backtrace
A More Intelligent Backtracing (22)
ab c
CY1(a) = 033 CY0(a) = 067CY1(b) = 05 CY0(b) = 05
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 199
「DIP概論」- IP Testing
Example 2 of PODEM (14)Initial objective(G5 1)G5 is an AND gate Choose the hardest-1rArr Current objective is (G1 1)G1 is an AND gate Choose the hardest-1 rArr Arbitrarily current objective is (A 1)A is a PI Implication rArr G3 = 0
Ps Initially CY1 and CY0 for all PIs are set to 05
C1(G1) = 025
C1(G1) = 0656
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 200
「DIP概論」- IP Testing
Example 2 of PODEM (24)Is the initial objective justified No rArr Current objective (G5 1)G5 is an AND gate Choose the hardest-1rArr Current objective is (G1 1)G1 is an AND gate rArr Choose the hardest-1 rArr Arbitrarily current objective is (B 1)B is a PI rArr Implication rArr G1 = 1 G6 = 0
C1(G1) = 025
C1(G1) = 0656
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 201
「DIP概論」- IP Testing
Example 2 of PODEM (34)Is the initial objective justified No rArr Current objective (G5 1)The value of G1 is known rArr Current objective (G4 0)The value of G3 is known rArr Current objective(G2 0)A B are known rArr Current objective (C 0)C is a PI rArr Implication rArr G2 = 0 G4 = 0 G5 = D G7 = D
C1(G1) = 025
C1(G1) = 0656
No backtracking
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 202
「DIP概論」- IP Testing
Example 2 of PODEM (44)
bull If the backtracing process is not guided ndash Two times of backtracking may occur
G5rarr G4rarr G2rarr A
G5rarr G4rarr G2rarr B
G5rarr G4rarr G2rarr C
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 203
「DIP概論」- IP Testing
Head Lines
bull A line that is reachable from at least one stem is said to be bound otherwise free
bull A head line is a free line that directly feeds a bound line
head linesbound
DE
ABC
F
G
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 204
「DIP概論」- IP Testing
The Property of Head Lines[Theorem 4-2] If l is a head line the value of l can be justified without contradicting any other values previously assignedHintThe subcircuit feeding l is fanout-free
head linesbound
DE
ABC
F
G
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 205
「DIP概論」- IP Testing
Fanout-Oriented (FAN) Algorithmbull The FAN algorithm introduces two major
extensions to the backtracing concept of PODEMndash Rather than stopping at PIs backtracing in
FAN may stop at internal lines ie head lines ndash Rather than trying to satisfy one objective
FAN use a multiple-backtrace procedure that attempts to simultaneously satisfy a set of objectives
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 206
「DIP概論」- IP Testing
FAN vs PODEM
head linesbound
DE
ABC
F
G
Assume that setting G = 0 causes the D-frontier to become empty
A1B0
F C0F
1
1
G0F
1
PODEM FAN
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 207
「DIP概論」- IP Testing
Multiple Backtracing (13)Mbacktrace(Current_objectives)beginrepeat
beginremove one entry (k vk) from
Current_objectivesif k is a head line
then add (k vk) to Head_objectiveselse if k is a fanout branch
thenbegin
j = stem(k)increment number of requests at
j for vk
add j to Stem_objectivesend else if k is a fanout branch
else continue tracingbegin
i = inversion of kc = controlling value of k
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 208
「DIP概論」- IP Testing
Multiple Backtracing (23)
if(vkoplus i = c) then
beginselect an input j of k with
value xadd (j c) to
Current_objectivesend if(vkoplus i = c)
elsefor every input j of k with
value x
add (j c) to Current_objectives
end continue tracingend
until Current_objectives = empty
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 209
「DIP概論」- IP Testing
Multiple Backtracing (33)
if Stem_objectives ne emptybeginremove the highest-level stem k from
Stem_objectives
vk = most requested value of k
if(k has contradictory requirements and k is not reachable from target fault)
then return (k vk)add (k vk) to Current_objectivesreturn
Mbacktrace(Current_objectives)end if Stem_objectives ne empty
remove one objective (k vk) from Head_objectivesreturn (k vk)
end Mbacktrace
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 210
「DIP概論」- IP Testing
Generation of Conflicting Values on A Stem
0
1
0
1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 211
「DIP概論」- IP Testing
Example of Multiple Backtracing (12)
AB
A1
A2E
E1
E2
G
H
I
JC
1
0
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 212
「DIP概論」- IP Testing
Example of Multiple Backtracing (22)
(I 1 ) (J 0 ) (I 1 )
(J 0 ) (G 0 ) (J 0 )
(G 0 ) (H 1 ) (G 0 )
(H 1 ) (A1 1 ) (E1 1) (H 1 )
(A1 1 ) (E1 1 ) (E2 1) (C 1) (A1 1 ) A(E1 1 ) (E2 1 ) (C 1 ) (E1 1 ) A E(E2 1 ) (C 1 ) (E2 1 ) A E(C 1) (C 1 ) A E C
A C(E 1 ) (E 1 ) A C(A2 0 ) (A2 1 ) A C
A C
Current_objectivesProcessed
entry Stem_objectives Head_objectives
empty
empty
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 213
「DIP概論」- IP Testing
The FAN Implementation (12)FAN( ) beginif Imply_and_check( ) =
FAILUREthen return FAILURE
if (error at PO and all bound lines are justified) then
beginjustify all unjustified head lines return SUCCESS
end
if(error not at PO and D-frontier = empty)then return FAILURE
add every unjustified bound lines to Current_objectivesselect one gate G from the D-frontier c = controlling value of Gfor every input j of G with value xadd (j c) to Current_objectives
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 214
「DIP概論」- IP Testing
The FAN Implementation (22)(i vi) = Mbackrace(Current_objectives)Assign(i vi)if FAN( ) = SUCCESSthen return SUCCESS
Assign(i vi) reverse decisionif FAN( ) = SUCCESSthen return SUCCESS
Assign(i x)return FAILURE
End FAN( )
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 215
「DIP概論」- IP Testing
ATPG (12)
bull Basic schemeinitialize the test set to NULLrepeat
generate a new test vectorevaluate fault coverage for the test vectorif the test vector is acceptable then add it to the test set
until the required fault coverage is obtained
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 216
「DIP概論」- IP Testing
ATPG (22)
bull Accelerationndash Phase I Random test patterns are generated
first to detect easy-to-detect faultsndash Phase II A deterministic TG is then performed
to generate test patterns for the remaining faults
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 217
「DIP概論」- IP Testing
Sequential TG
bull For circuits with unknown initial statesndash Time-frame expansion based
bull Extended D-algorithmbull 9-V sequential TG
ndash Simulation basedbull CONTEST [Agrawal and Cheng IEEE TCAD Feb
1989]
bull For circuits with known initial statesndash STALLION [Ma et al IEEE TCAD Oct 1988]
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 218
「DIP概論」- IP Testing
Iterative Logic Array (ILA) Model
bull Here the model is restricted to synchronous sequential circuits
initial states
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 219
「DIP概論」- IP Testing
Extended D-algorithm1 Pick up a target fault f2 Create a copy of the combinational logic say Time-
frame 03 Generate a test pattern for f using D-algorithm for
time-frame 04 If all the fault effects are propagated into the FFrsquos
continue the fault propagation in the next time-frame5 If there are values required to be justified in the
FFrsquos continue the line justification (LJ) in the previous time-frame
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 220
「DIP概論」- IP Testing
I
OY1
Y2y1
y2 s-a-1
FF2
FF1
Example of Extended D-algorithm (12)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 221
「DIP概論」- IP Testing
Example of Extended D-algorithm (22)
OY1
Y2
I
y1
y2 s-a-1
time-frame 00
1
D
I
OY1
Y2
y1
y2 s-a-1
time-frame 1
1D
I
y1
y2 s-a-1
time-frame -1
0
0
Y1
Y2
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 222
「DIP概論」- IP Testing
9-V Sequential TG
bull Extended D-algorithm is not completebull If 9-V instead of 5-V is used it will be a
complete algorithmndash Since it takes into account the possible repeated
effects of the fault in the ILA model
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 223
「DIP概論」- IP Testing
Example of 9-V Sequential TG (12)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 224
「DIP概論」- IP Testing
Example of 9-V Sequential TG (22)bull If 5-V Sequential TG is usedhelliphellip
D D
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 225
「DIP概論」- IP Testing
Problems of Time-frame Approachesbull The requirements created during the
forward process (FP) have to be justified (LJ) by the backward processes laterndash Need going both forward and backward time
framesndash Need to maintain a large number of time-
framesbull How many Cyclesbull Implementation is complicated
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 226
「DIP概論」- IP Testing
Simulation-Based Approaches
bull Advantagesndash Timing is considered and asynchronous circuits
can be handledndash Can be easily implemented by modifying a
fault simulatorbull Disadvantages
ndash Can not identify undetectable faultsndash Hard-to-activate faults may not be detected
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 227
「DIP概論」- IP Testing
Difficulties of Sequential Test Generation
bull Initialization is difficultndash Justify invalid statesndash Long initialization sequences (simulator
limitations)bull Timing cannot be considered by time-frame
expansionsndash Races and hazardsndash Asynchronous circuits cannot be handled
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 228
「DIP概論」- IP Testing
Why FC of 100 Is Hard
bull If each undetected fault is redundant then FC will easily reach at 100ndash Proving that the undetected fault is a redundant
fault may be very and very hardbull How to increase FC
faultsredundant the-list fault of size thefaultsredundant the-fault undetected of size the-1
faultsredundant the-list fault of size thefaults detected the
=
=FC
Chapter 5
Design for Testability (DFT)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 230
「DIP概論」- IP Testing
Motivation bull Test costs
ndash Test Generation (TG)ndash Fault Simulationndash Test Application Timendash Memory spacendash helliphellip
bull Test difficultiesndash Sequential gt Combinationalndash helliphellip
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 231
「DIP概論」- IP Testing
Testability Measures
bull Controllabilityndash The difficulty of setting a particular logic signal
to a 0 or 1bull Observability
ndash The difficulty of observing the state of a logic signal
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 232
「DIP概論」- IP Testing
SCOAPbull Sandia ControllabilityObservability
Analysis Program [Goldstein 1979]bull Use six cost functions of type integer to
reflect the relative difficulties of controlling and observing signals in digital circuitsndash Higher numbers indicate more difficult to
control or observe signals
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 233
「DIP概論」- IP Testing
Combinational SCOAP Measures
bull For signal lndash CC0(l)
bull The combinational ldquorelative difficultyrdquo of setting l to 0
ndash CC1(l)bull The combinational ldquorelative difficultyrdquo of setting l to 1
ndash CO(l)bull The combinational ldquorelative difficultyrdquo of propagating
a fault effect from l to a PO
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 234
「DIP概論」- IP Testing
bull For signal lndash SC0(l)
bull The sequential ldquorelative difficultyrdquo of setting l to 0
ndash SC1(l)bull The sequential ldquorelative difficultyrdquo of setting l to 1
ndash SO(l)bull The sequential ldquorelative difficultyrdquo of propagating a
fault effect from l to a PO
Sequential SCOAP Measures
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 235
「DIP概論」- IP Testing
Initialization
bull CC0(i) = CC1(i) = SC0(i) = SC1(i) = 1 for all PI ibull CO(o) = SO(o) = 0 for all PO obull Set others to infin
The controllabilities range between 1 and infin
The observabilities range between 0 and infin
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 236
「DIP概論」- IP Testing
Controllability of Combinational Components (12)
bull CC0(z) = CC0(a) + CC0(b) + 1bull CC1(z) = minCC1(a) CC1(b) + 1bull SC0(z) = SC0(a) + SC0(b)bull SC1(z) = minSC1(a) SC1(b)
ab z
CC0 or CC1 are related to the number of signals that may be manipulated to control SC0 or SC1 are related to the number of time-frames needed to control
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 237
「DIP概論」- IP Testing
Controllability of Combinational Components (22)ab
ab
abab
ab
ab
z
z
z
z
z
z
CC0(z) = minCC0(a) CC0(b) + 1CC1(z) = CC1(a) + CC1(b) + 1
CC0(z) = CC1(a) + CC1(b) + 1CC1(z) = minCC0(a) CC0(b) + 1CC0(z) = CC0(a) + CC0(b) + 1CC1(z) = minCC1(a) CC1(b) + 1CC0(z) = minCC1(a) CC1(b) + 1CC1(z) = CC0(a) + CC0(b) + 1
CC0(z) = minCC1(a) + CC1(b) CC0(a) + CC0(b) + 1CC1(z) = minCC0(a) + CC1(b) CC1(a) + CC0(b) + 1
CC0(z) = minCC0(a) + CC1(b) CC1(a) + CC0(b) + 1CC1(z) = minCC1(a) + CC1(b) CC0(a) + CC0(b) + 1
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 238
「DIP概論」- IP Testing
Controllability of Sequential Components
bull CC0(Q) = minCC0(R) CC1(R) + CC0(D) + CC0(C) + CC1(C)bull CC1(Q) = CC1(R) + CC1(D) + CC0(C) + CC1(C)bull SC0(Q) = minSC0(R) SC1(R) + SC0(D) + SC0(C) + SC1(C) + 1bull SC1(Q) = SC1(R) + SC1(D) + SC0(C) + SC1(C) + 1
D
C
Q
R
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 239
「DIP概論」- IP Testing
Observability (12)
P
QR
N
bull CO(P) = CO(N) + CC1(Q) + CC1(R) + 1bull SO(P) = SO(N) + SC1(Q) + SC1(R)
D
C
Q
R bull CO(R) = CO(Q) + CC1(Q) + CC0(R)bull SO(R) = SO(Q) + SC1(Q) + SC0(R) + 1
CO are related to the number of signals that may be manipulated to observeSO are related to the number of time-frames needed to observe
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 240
「DIP概論」- IP Testing
Observability (22)ab
ab
abab
ab
ab
z
z
z
z
z
z
CO(a) = CO(z) + CC1(b) + 1CO(b) = CO(z) + CC1(a) + 1
CO(a) = CO(z) + CC1(b) + 1CO(b) = CO(z) + CC1(a) + 1
CO(a) = CO(z) + CC0(b) + 1CO(b) = CO(z) + CC0(a) + 1CO(a) = CO(z) + CC0(b) + 1CO(b) = CO(z) + CC0(a) + 1
CO(a) = CO(z) + minCC0(b) CC1(b) + 1CO(b) = CO(z) + minCC0(a) CC1(a) + 1CO(a) = CO(z) + minCC0(b) CC1(b) + 1CO(b) = CO(z) + minCC0(a) CC1(a) + 1
zz1z2
zn
CO(z) = minCO(z1) CO(zz) helliphellip CO(zn)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 241
「DIP概論」- IP Testing
Example of SCOAP (13)
1
23
4
5
6
PI3
PI2
PI1
PO
Note ( C0 C1 )
(11)
(11)
1
23
4
5
6
PI3
PI2
PI1
PO
(11)
(11)
(11)
(11)
(11)
Computation of controllability (12)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 242
「DIP概論」- IP Testing
Example of SCOAP (23)
Note ( C0 C1 )
(11)
(11)
1
23
4
5
6
PI3
PI2
PI1
PO
(11)
(11)
(11)
(11)
(11)
(22)
(22)
(23)
(35)
(27)
(54)
Note ( C0 C1 ) O
(11)
(11)
1
23
4
5
6
PI3
PI2
PI1
PO
(11)
(11)
(11)
(11)
(11)
(22)
(22)
(23)
(35)
(27)
(54) 0
Computation of controllability (22)
Computation of observability (13)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 243
「DIP概論」- IP Testing
Example of SCOAP (33)
Note ( C0 C1 ) O
(11) 5
(11) 5
1
23
4
5
6
PI3
PI2
PI1
PO
(11)
(11)
(11) 9
(11) 9
(11) 9
(22) 8
(22) 8
(23) 3
(35) 5
(27) 3
(54) 0
Note ( C0 C1 ) O
(11) 5
(11) 5
1
23
4
5
6
PI3
PI2
PI1
PO
(11) 5
(11) 5
(11) 9
(11) 9
(11) 9
(22) 8
(22) 8
(23) 3
(35) 5
(27) 3
(54) 0
Computation of observability (23)
Computation of observability (33)
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 244
「DIP概論」- IP Testing
Importance of Testability Measures
bull Speed up test generation (TG) algorithmsbull Improve the testability of the circuit under
design ndash Guide the design for testability (DFT) insertion
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 245
「DIP概論」- IP Testing
Design for Testability (DFT)
bull DFT techniquesndash Design efforts specifically employed to ensure
that a circuit is testablebull In general DFT is achieved by employing
extra hardware overheadndash Conflict between design and test engineersndash Balance between amount of DFT and gain
achieved
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 246
「DIP概論」- IP Testing
Benefits of DFTbull Fault coverage uarr (must guarantee) bull Test generation time darrbull Test lengthTest memoryTest application time darrbull Support a test hierarchy
ndash Chipsndash Boardsndash Systems
rArrPay less now and pay more latter without DFT
FC100
with DFT
of T
without DFT
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 247
「DIP概論」- IP Testing
Costs Associated with DFT
bull Pin overhead uarrbull Area uarrbull Yield darrbull Performance darrbull Design time uarr
rArrThere is no free lunch
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 248
「DIP概論」- IP Testing
DFT Techniques
bull Ad hoc DFT techniquesbull Scan-based designsbull Boundary scan
教育部顧問室「超大型積體電路與系統設計」教育改進計畫 DIP聯盟淡江大學電機工程學系 饒建奇 249
「DIP概論」- IP Testing
Ad Hoc DFT Techniquesbull Test pointsbull Initializationbull Monostable multivibrators (one-shots)bull Oscillators and clocksbull Partitioning counters and shift registersbull Partitioning of large combinational circuitsbull Logic redundancybull Break global feedback paths