Introduction to Altera devices - cms3.koreatech.ac.kr
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© 2005 HANBACK Corporation
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Introduction to Altera devices
An industry leader in programmable logic– Inventor of the EPLD in 1983
Programmable Logic Families– Excalibur™ Embedded Processor Solutions
+ARM®-Based, Nios II™– SRAM Based
+APEX™ II, APEX™ 20K, Mercury™, HardCopy™, ACEX™ 1K, FLEX 10K®, FLEX® 6000, FLEX 8000, Cyclone, Cyclone II, Stratix, Stratix GX, Stratix II
– EEPROM Based+MAX II, MAX® 3000, MAX 7000, MAX 9000, Classic™
Configuration Devices Software development systems: Quartus® II, MAX+PLUS® II
© 2005 HANBACK Corporation
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What’s New in Quartus II ?New Product Support– APEX™ II Family– FLEX 10KE Family– ACEX 1K Family
Improved Design Flow With LogicLock– Performance preservation– Incremental synthesis
Excalibur MegaWizard®
PowerFit™ Fitter Improvements– Multiple slack timing tables implemented
New Timing Assignments– Wildcard allowed & ability to apply multi-cycle to enables
PowerGauge™ Enhancements– Mercury, LVDS I/O, & ModelSim™ support
Toolnet Cross Probing with Synplicity 7.0
© 2005 HANBACK Corporation
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Features32 Bit RISC Processor– Up to 200 MHz ARM922T™
High Performance .18 µm 8LM TSMC ProcessAMBA™ Bus Architecture– Industry Standard Bus Architecture
Stripe Memory– Single Port and Dual Port
External Memory I/F– Embedded SDRAM/DDR SDRAM Controller (Dedicated Pin)– Flash/EEPROM/SRAM (Through EBI Bus)
© 2005 HANBACK Corporation
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Hard Processor PLD Architecture
PLL
Timer
UART
InterruptControllerWatchdog
Timer
JTAG
128 Kbytes SRAM64 Kbytes DPRAM
32 Kbytes SRAM16 Kbytes DPRAM
256 Kbytes SRAM128 Kbytes DPRAM
EmbeddedProcessorStripe
PLD
DPRAM
EPXA1
EPXA4
EPXA10
TraceModule
ARM922T
SRAM SRAM SRAM
DPRAM DPRAM
ExternalMemory
InterfacesProcessor & Interfaces
I-CACHE D-CACHEARM 8K Bytes 8K Bytes
LEs 4160ESB Bytes 6.5K
LEs 16400ESB Bytes 26K
LEs 38400ESB Bytes 40K
© 2005 HANBACK Corporation
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Feature EPXA1 EPXA4 EPXA10
Maximum System Gates 263,000 1,052,000 1,772,000
Typical Gates 100,000 400,000 1,000,000
LEs 4,160 16,640 38,400
Embedded System Blocks (ESBs) 26 104 160
Maximum RAM Bits 53,248 212,992 327,680
Maximum User I/O Pins 178 360 521
Single-Port SRAM 32 Kbytes 128 Kbytes 256 Kbytes
Dual-Port SRAM 16 Kbytes 64 Kbytes 128 Kbytes
Total Ram Bits (PLD + Stripe) 446,464 1,785,856 3,473,408
Device Summary
HBE-SOC-Entry II Platform
© 2005 HANBACK Corporation
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Excalibur Device Packages
Pins 484 672 1020 612 864
Pitch (mm) Plastic, 1.0 Plastic, 1.0 Plastic, 1.0 Plastic, 1.27 Plastic, 1.27
EPXA1 173 178 178
EPXA4 275 360 215 360
EPXA10 521 365
Migration Vertical Vertical Vertical Vertical
I/O FineLine BGA BGA
Size (mm) 23 27 33 35 45
N/A
HBE-SOC-Entry II Platform
© 2005 HANBACK Corporation
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PLD Area for Customer Design
ARM922TCore
Single-PortRAM
Dual-PortRAM
Die Picture
Stripe IP is placed physically
on the top of the APEX20KE PLD
© 2005 HANBACK Corporation
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Excalibur Stripe Components32 Bit RISC Processor AHB1 & AHB2 BusesPLL SupportMemory– Single Port– Dual Port– SDRAM Controller
Expansion Bus InterfacePeripherals– UART– Interrupt Controller– Watchdog Timer– Timer
Reset & Mode control
© 2005 HANBACK Corporation
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Excalibur Stripe Components
WatchdogTimer
PLL
AHB 1-2Bridge
Dual Port SRAM
SDRAMController
Single Port SRAM
32 Bit RISC Processor
Interrupt Controller
AHB1
AHB2
SDRAM
Embedded StripeSRAMFLASH
APEX 20KE
PLD - Stripe Bridge
PLDMaster
ConfigurationLogic Master
Reset Module Timer
PLD Slave
UARTBus
Expansion (EBI)
Stripe - PLD Bridge
ROM
PLD Slave
PLDModule
PLDModule
Excalibur Hard IP
External Devices
APEX Soft IP
© 2005 HANBACK Corporation
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Excalibur MegaWizard
Select ARM®-Based™ Excalibur™
– Easily create the desired stripe configuration
© 2005 HANBACK Corporation
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MegaWizard
Select family and device
Hold processor in reset?
Endianess
Reserve pins
Boot from FLASH?
© 2005 HANBACK Corporation
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AMBA High Performance Bus (AHB)
AMBA - Advanced Micro-controller Bus Architecture Connects Embedded Stripe and PLD Devices 200MHz Maximum Clock Rate32 Bit Wide Pipelined Bus– Burst transfers - one cycle per data word– Non-tristate implementation
Multi-master With Distributed Address Decoding– Single-cycle bus master handover
Split Transactions Extensions– Needed to fully exploit bus bandwidth in a multi-master bus
© 2005 HANBACK Corporation
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AHB1 Bus
Processor Is the Sole MasterSupport for Locked TransfersUser Will Not Interface to This BusHighest Speed Bus Connection to Memory (200MHz)– SRAM– SDRAM– DDR RAM
© 2005 HANBACK Corporation
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AHB1 Bus
WatchdogTimer
PLL
AHB 1-2Bridge
Dual Port SRAM
SDRAMController
Single Port SRAM
32 Bit RISC Processor
Interrupt Controller
AHB1
SDRAMEmbedded Stripe
SRAMFLASH
APEX 20KE
PLD - Stripe Bridge
PLDMaster
ConfigurationLogic Master
Reset Module Timer
PLD Slave
UARTBus
Expansion (EBI)
Stripe - PLD Bridge
ROM
PLD Slave
PLDModule
PLDModule
Excalibur Hard IP
External Devices
APEX Soft IP
© 2005 HANBACK Corporation
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AHB2 Bus
Connects Processor Standard Cell to the PLD Master and Slave Devices3 Bus Masters– AHB1-2 bridge– Configuration logic– PLD master interface
Multiple Slave DevicesSupports Split Transaction– Needed to fully exploit bus bandwidth
Operates at Half the Frequency of AHB1
© 2005 HANBACK Corporation
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AHB2 Bus
WatchdogTimer
PLL
AHB 1-2Bridge
Dual Port SRAM
SDRAMController
Single Port SRAM
32 Bit RISC Processor
Interrupt Controller
AHB2
SDRAMEmbedded Stripe
SRAMFLASH
APEX 20KE
PLD - Stripe Bridge
PLDMaster
ConfigurationLogic Master
Reset Module Timer
PLD Slave
UARTBus
Expansion (EBI)
Stripe - PLD Bridge
ROM
PLD Slave
PLDModule
PLDModule
Excalibur Hard IP
External Devices
APEX Soft IP
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