Functional Timing Analysis Made Fast and General Presenter: Yi-Ting Chung Advisor: Jie-Hong Roland Jiang 03/09/2012 Graduate Institute of Electronics Engineering,

Functional Timing Analysis Made Fast and General

Presenter: Yi-Ting Chung Advisor: Jie-Hong Roland Jiang

03/09/2012Graduate Institute of Electronics Engineering,

National Taiwan University, Taiwan (ROC)

Outline

2

• Introduction

• Preliminaries

• TCF Construction

• Algorithms

• Experimental Results

• Conclusions And Future Work

• References

Circuit ModelSensitization CriteriaSatisfiability of Timing Requirement

TCF without 0/1-SpecificityTCF with 0/1SpecificityComparison on TCF FormulasTCF Equivalence Reduction

Delay ComputationCritical Region Identification

2

3

Introduction

• In modern synthesis flow of very large scale integration (VLSI) design, timing analysis is essential in– Identifying timing critical regions for re-synthesis– Determining operable clock frequencies– Avoiding wasteful over-optimization and thus accelerating

design closure in meeting stringent timing constraints

1

Combinational circuit

Critical regionFFs FFs

Lower bound of clock period

4

Introduction

• Timing analysis has two main approaches– Static timing analysis (STA)– Functional timing analysis (FTA)

2

ab

Use topological orderPro: linear-time complexityCon: may overestimate delay

STASTA

Assume under unit delay model

1 2

1

43

FTAFTAIdentify false critical paths Pro: accurateCon: NP-hard

Delay = 4

ab

Delay = 2

5

Introduction

• We focus on the delay-dependent FTA, identifying true and false paths with respect to some timing library– Delay-independent FTA is incomplete in that not every delay

path can be concluded true or false regardless of arbitrary delay assignments

3

6

Introduction

• We use satisability(SAT)-based computation engine– Reason: clean separation between timed characteristic

function (TCF) construction and SAT solving– Challenge: massive numbers of variables and clauses when

translating a complex TCF into a conjunctive normal form (CNF) formula for SAT solving

– Goal: to improve the efficiency of TCF representation

4

7

• Floating-mode operation– Signals are of unknown initial values and stablize to their final values

induced by truth assignments on the PIs

• For a gate f:– vi (controlling value of gate input gi):

the value of f can be determined by gi with vi

Some complex gates have no controlling values…– C1: the set of primes of f { ab, a’b’d’}– C0: the set of primes of f ’ { ab’, a’b, a’d}– Controlling cube: a truth assignment that

determines f regardless of other inputs ab– Controlling cube set: C = C1 + C0 – minterms { ab, ab’, a’b,

a’d}

Preliminaries

v1 = 0v2 = 0

d \ab 00 01 11 10

0 1 0 1 0

1 0 0 1 0

8

• Timed characteristic function (TCF) – the set of PI assignments that makes the output value of f

change from unknown to its final value at a specific timing requirement.

– is satisable if there exists some PI assignments to make f stablize __________ than time t

no earlier earlier no later later– 0/1-specify TCF: specify the final value of f

What Is TCF

tf ,

tf ,

tf ,

tf ,

TIMINGf ,

tf ,1 PIs make f = 1 before time t

tTCF

…

TCF Equivalence Table

9

tf ,

tf ,

2 , af 1 3 , af maf , 0

] ,( 21 aa ] ,( 32 aa ] ,( 1 mm aa ] ,0[ 1a ) ,( ma

2 , af 0 3 , af maf , 1

tTCF

…

tf ,

tf ,

1 , af 1 2 , af 1 , maf 0

) ,[ 21 aa ) ,[ 32 aa ) ,[ 1 mm aa ) ,0[ 1a ) ,[ ma

1 , af 0 2 , af 1 , maf 1

a1 =min arrival time of fam=max arrival time of f

no earlier earlier

no later

later

10

• TCF can be used to find circuit delay by formulating the problem as searching the maximum D such that the formula

or

is satisfiable.

Find Circuit Delay by TCF

Dp

POp

Dp

POp

,

,

Dp

POp

Dp

POp

,

,

Topological max delay

Searching order D

UNSAT

UNSAT

SAT

D

UNSAT

UNSAT

UNSAT

SAT

Functional max delay

UNSAT: cannot find a PO stablizing later than time D

Need more test !

no/ earlier no/ earlier

no/ laterno/ later

(1) (2)

Algorithm

• We choose no earlier/earlier TCF to compute delay– Search the max D such that or

is satisfiable.

• For each D,– Construct these TCFs recursively from POs to PIs– Convert them to CNF – SAT solving• Satisfiable: functional max delay is D• Unsatisfiable: reduce D and try again

Dp

POp

,

Dp

POp

,

12

d = 1

Delay Model

• Fall/rise-combined delay model– Unit delay model– fanout delay model

• Fall/rise-separate delay model– TSMC 0.18um delay model

d = 1.4

df = 0.23

dr = 0.27

• formula [1] (for simple gate only)

• Our formula

• Example: construct

Simple TCF Formula

))(( ,

)(

,

)(

,i

dtg

cglitCc

dtg

fFIg

tf glitii

i

ii

i

13

))(( ,

)(

,

)(

,

i

ii

i

ii

i

nidtg

fFIg

dtg

fFIg

tf vg

ab f

(3)

)(

)(

)(

, ,

, ,

, , ,

b

ab

a

ba

dtbtf

dtatf

dtbdtatf

adta ,bdtb ,adta ,

bdtb ,a

b

(4)

13 clauses + 3 extra variables

tf ,

3 clauses

tf ,

Dp

POp

,

Target: to build

(3)

(4)

• Assume delay of INV = 1, delay of AND = 3• Compute A={topological arrival time list}

• Search max D such that is satisfiable. (D = 7 initially)

• The functional max delay is 7, sensitized by “a=1, b=1”

Example

14

ef

ab

{0}{0}

{1}{3, 4}

{3, 6, 7}d

Df , 0 0 (by equivalence table)

Must be 1

0 0

Must be 1

Must be 1

1Satisfiable!

))()(( 4 ,4 ,4 ,4 ,7 , be bebef

))()(( 1 ,1 ,1 ,1 ,4 , da dadae

Combined delay model

• Prior formula [2] (for simple gate only)

• Prior formula [3]

• Our formulas

0/1-Specify TCF Formula

15

)( ,0 ,1

DpDp

POppp

Target: to build

(6)

(5)

ii dtkg

cLCc

tvf

,

)it(g

,

iv

ii dtkg

cLCc

tvf

,

)it(g

,

iv

ifi

iri

dtg

F

tf

dtg

F

tf

,0

I(f) g

,0

,1

I(f) g

,1

i

i

ifi

iri

dtg

F

tf

dtg

F

tf

,0

I(f) g

,0

,1

I(f) g

,1

i

i

AND OR

v={0,1}k=0 if Lit(gi)=gi’K=1 if Lit(gi)=gi

(7) (8)

• Problem– Topological arrival time lists are not efficient for fall/rise-

separate delay models.– INV: falling delay df = 12, rising delay dr = 21– AND: falling delay df = 23, rising delay dr = 27– Compute A

Example

16

ef

ab

{0}{0}

{12, 21}{23, 27, 35, 39, 44, 48}

{23, 27, 46, 50, 54, 58,

62, 66, 67, 71, 75, 79}d

Many arrival times…

UNSAT

Separate delay model

• Each gate f has two arrival time lists• A0(f) = {Falling arrival time list} (arrival times for f = 0)• A1(f) = {Rising arrival time list} (arrival times for f = 1)

• Define the output controlling value of simple gate f to be co .i.e. the value of f is determined from unknown to co by an input gi with input controlling value ci.

• Define the output non-controlling value of f to be nco . i.e. the value of f is determined from unknown to nco by every input gi with input non-controlling value nci. – Ex. co = 1, c1 = 0, c2 = 1 nco = 0, nc1 = 1, nc2 = 0

0/1-Separate Arrival Time List

17

g1

g2f

1

• Compute fall/rise-separate arrival time lists– Output controlling value must be sensitized by an input

controlling value.

18

)( )()( )(

idafAo

iicio c

gAafFIgc

g1

g2 fA0(g1) = {1, 5}

A0(g2) = {2, 5}A0(f) = {24, 25, 28}

d0 = 23

Linear time complexity

20/1-Separate Arrival Time List

• Compute fall/rise-separate arrival time lists– Output non-controlling value must not be sensitized by an

earlier input non-controlling value.

3

19

)( )( ),( )(

idafAo

iincio nc

pagAafFIgnc

}min{max)( )( ap

iinci gAafFIg Before p, at least one fanin is not ready to input

controlling value, so f cannot be determined yet.

g1

g2 fA1(g1) = {1, 3, 5}

A1(g2) = {4, 6}A1(f) = {28, 30, 31, 32, 33}

d1 = 27

p = 4 arrival times 1 and 3 need not propagate to FO

PS. Also work for XOR gates

0/1-Separate Arrival Time List

• Before separation of 0/1:

• After separation of 0/1:

Comparison

20

ef

ab

A(a)={0}

A(b)={0}

{12, 21}{23, 27, 35, 39, 44, 48}

{23, 27, 46, 50, 54, 58,

62, 66, 67, 71, 75, 79}d

ef

ab

A0(a)={0}A1(a)={0}

dA0(b)={0}A1(b)={0}

{12}{21}

{23, 35}{42} {23, 46, 58}

{75}

Many redundant arrival times

INV: df = 12, dr = 21AND: df = 23, dr = 27

Equivalence look-up table is more efficient

• Compute 0/1-separate arrival time lists

– D = 75– D = 58

21

ef

ab

A0(a)={0}A1(a)={0}

dA0(b)={0}A1(b)={0}

{12}{21}

INV: df = 12, dr = 21AND: df = 23, dr = 27

{23, 35}{42} {23, 46, 58}

{75}

0 1

0

UNSATRemove {75}

How to build gate function efficiently?

0

10 SAT when D=58 Return “a=1, b=1”

fff ff 75 ,175 ,0 85 ,085 ,185 ,0 fff fff

))(( 53 ,053 ,085 ,0 bef bef

))(( 21 ,012 ,053 ,0 dae dae

ExampleSeparate delay model

• Directly transform

• Use implication when only need f or f’, remove all BUF/INV

CNF of Gate Function

22

))()()()((

))()((

))()((

bdbddeaedae

bfefbef

bdadeebf

))()()((

))((

beaebfef

baeebf

Replace d by b’ directly

a a’ a a’

a

Example

• 1. Fall/rise-separate arrival time lists add the concept of p• 2. Build gate functions remove all BUFF and INV • 3. Change TCF formulas of [1] to implication form • SAT solver time (s):

Experimental Results

23

Delay Circuit [1] New 123 Our New12

Unitb18 1.72 1.15 0.29 0.18

b19 11.50 6.98 0.76 0.53

leon3mp 12229 7250 0.79 0.37

TSMCleon3 130.69 8.1 12.73 10.96

leon3mp 603.09 107 50.22 35.27

netcard 92964 99380 90456 83803

73843 without New3

New

• Accelerate the program• Use X(f, =t)?• Is the critical region computed by combined TCF formula useful for a

separate delay model?• Can deal with incremental delay change?

[1] L. Silva, J. Marques-Silva, L. Silveira, and K. Sakallah. Satisability models and algorithms for circuit delay computation. ACM Trans. on Design Automation of Electronic Systems, 7(1): 137-158, Jan. 2002.

[2] Y.-M. Kuo, Y.-L. Chang, and S.-C. Chang. Efficient Boolean characteristic function for timied automatic test pattern generation. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 28(3): 417-425, March 2009.

[3] P. McGeer, A. Saldanha, R. Brayton, and A. Sangiovanni-Vincentelli, Logic Synthesis and Optimization, ch. Delay Models and Exact Timing Analysis, pp. 167189. Kluwer Academic Publishers, 1993.

Future Work & References

24Thank You!