ELCT 501: Digital System Design - GUCeee.guc.edu.eg/Courses/Electronics/ELCT501 Digital System Design... · A1 A2 CS 1-to-2 Decoder Column Decoder D0 D1 D2 D3 Tristate Buffer (read)
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ELCT 501:
Digital System Design
Lecture 2: Memory and Programmable Logic
Dr. Mohamed Abd El Ghany,
Department of Electronics and Electrical Engineering
Memory
2 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Random Access Memory
(RAM)
Read-Only Memory
(ROM)
Can be read and written
Static Random Access Memory
(SRAM)
Data stored so long as vdd
is applied
6-transistors per cell
Faster
Dynamic Random Access
Memory (DRAM)
Require periodic refresh
Smaller (can be
implemented by 1 or 3
transistors)
slower
A memory device in which permanent
binary information is stored
Mask ROM: The programming is done by
the semiconductor company during the
last fabrication process of the unit
PROM: Once the PROM is programmed,
it cannot be reversed
EPROM: An erasable PROM and can be
erased by exposure to UV light
EEPROM: Can be erased and
programmed with electrical pulses
Flash memory: High-density read/write
memories that are nonvolatile. They have
the ability to retain charge for years with
no applied power
ELCT 501: Digital System
Design
Winter 2011
Block Diagram of Memory
3 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
2k words N-bit per word
Memory Unit
N-bit Data Input (for Write)
N-bit Data Output (for Read)
K-bit address lines
Read/Write
Chip Enable
N
N
K
Example: 2MB memory, byte-addressable
-N =8 (because of byte-addressability)
-K= 21 (1 word= 8-bit)
ELCT 501: Digital System
Design
Winter 2011
Static Random Access Memory
(SRAM)
4 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
BitLine BitLine
Wordline (WL)
Typically each bit is implemented with 6 transistors (6T SRAM Cell)
During read, the bitline and its inverse are precharged to Vdd (1) before set
WL=1
During write, put the value on Bitline and its inverse on Bitline_bar before
set WL=1
ELCT 501: Digital System
Design
Winter 2011
Dynamic Random Access Memory
(DRAM)
5 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
1-transistor DRAM cell
During a write, put value on bitline and then set WL=1
During a read, prechage bitline to Vdd (1) before assert WL to 1
Storage decays, thus requires periodic refreshing (read-sense-write)
Bitline
Wordline (WL)
ELCT 501: Digital System
Design
Winter 2011
Memory Description
6 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Memory # of addr # of data lines # of addr lines # of total bytes
1M x 8 1,048,576 8 20 1 MB
2M x 4 2,097,152 4 21 1 MB
1K x 4 1024 4 10 512 B
4M x 32 4,194,304 32 22 16 MB
16K x 64 16,384 64 14 128 KB
Capacity of a memory is described as
# addresses x Word size
ELCT 501: Digital System
Design
Winter 2011
How to address Memory
7 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
0
1
2
3
D7 D6 D5 D4 D3 D2 D1 D0
4x8 Memory
2-to-4 Decoder
A0
A1
CS
Chip Select
ELCT 501: Digital System
Design
Winter 2011
How to address Memory
8 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
0
1
2
3
D7 D6 D5 D4 D3 D2 D1 D0
4x8 Memory 2-to-4 Decoder
A0=1
A1=0
CS
Chip Select=1
Access address = 0x1
ELCT 501: Digital System
Design
Winter 2011
Use 2 Decoders
9
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
0
1
2
3
2-to-4 Decoder Row Decoder
A1
A2
CS
1-to-2 Decoder Column Decoder
D0 D1 D2 D3
Tristate Buffer (read)
0 1
A0
Chip Select CS
Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
8x4 Memory
ELCT 501: Digital System
Design
Winter 2011
Tristate Buffer
10 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Input Output
En
Input Output
En
Output
En
En Input
Vdd
CMOS circuit
Could amplify signal
Typically used for signal
traveling e.g. bus
ELCT 501: Digital System
Design
Winter 2011
Bi-directional Bus using Tri-state
Buffer
11 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Direction (control data flow for read/write)
A
B
Input/Output
ELCT 501: Digital System
Design
Winter 2011
Read/Write Memory
12
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
0
1
2
3
2-to-4 Decoder Row Decoder
A1
A2
CS
1-to-2 Decoder Column Decoder
D0 D1 D2 D3
0 1
A0
Chip Select CS
8x4 Memory
Rd / Wr = 0
ELCT 501: Digital System
Design
Winter 2011
Read/Write Memory
13
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
0
1
2
3
2-to-4 Decoder Row Decoder
A0
A1
CS
1-to-2 Decoder Column Decoder
D0 D1 D2 D3
0 1
A0
Chip Select=1 CS
8x4 Memory
Rd / Wr = 1
ELCT 501: Digital System
Design
Winter 2011
Building Memory in Hierarchy
14 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
D3
D2
D1
D0
A19 A18 A17
A0
1Mx4
R/W CS
D7
D6
D5
D4
A19 A18
1Mx4
R/W CS
A17
A0 CS
Design a 1Mx8 using
1Mx4 memory chips
ELCT 501: Digital System
Design
Winter 2011
Building Memory in Hierarchy
15 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Design a 2Mx4 using
1Mx4 memory chips
A19 A18 A17
A0
1Mx4
R/W CS
A19 A18 A17
A0
1Mx4
R/W CS
A20 1-to-2 Decoder
CS
1
0
D3
D2
D1
D0
ELCT 501: Digital System
Design
Winter 2011
Building Memory in Hierarchy
16
Design a 2Mx8 using
1Mx4 memory chips
A19 A18 A17
A0
1Mx4
CS R/W
A19 A18 A17
A0
1Mx4
CS R/W
A19 A18 A17
A0
1Mx4
CS R/W
A19 A18 A17
A0
1Mx4
CS R/W
D7
D6
D5
D4
D3
D2
D1
D0
A19 A18 A17
A0
A20 1-to-2 Decoder
CS
1
0
Dr. Mohamed Abd el Ghany
17 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Memory Model
Flat Memory Model
0x0A
0xB6
0x41
0xFC
Lower Memory Address
0x00000000
Higher Memory Address
0x00000001
0x00000002
0x00000003
0xFFFFFFFF 0x0D
32-bit address space
can address up to 4 GB
(232) different memory
locations
ELCT 501: Digital System
Design
Winter 2011
18 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Endianness [Danny Cohen 91]
A byte ordering- How a multiple byte data word stored in memory
Endianness (from Gulliver’s Travels)
Big Endian
Most significant byte of a multi-byte word is stored at the lowest
memory address
E.g. Sun Sparc, PowerPC
Little Endian
Least significant byte of a multi-byte word is stored at the lowest
memory address
e.g. Intel x86
Some embedded & DSP processors would support both for interoperability
ELCT 501: Digital System
Design
Winter 2011
19 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Endianness Examples
Store 0x21436587 at address 0x0000
0x87
0x65
0x43
0x21
Lower Memory Address
Higher Memory Address
0x0000
0x0001
0x0002
0x0003
BIG ENDIAN
0x21
0x43
0x65
0x87
Lower Memory Address
Higher Memory Address
0x0000
0x0001
0x0002
0x0003
LITTLE ENDIAN
ELCT 501: Digital System
Design
Winter 2011
20 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
“Permanent” binary information is stored
Non-volatile memory
Power off does not erase information stored
Read Only Memory (ROM)
2k words N-bit per work
ROM N-bit Data Output
K-bit address lines
N K
ELCT 501: Digital System
Design
Winter 2011
21 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
32x8 ROM
32x8 ROM 8 5
0 1 2 3
28 29 30 31
D7 D6 D5 D4 D3 D2 D1 D0
A4
A3
A2
A1
A0
5-to-32 Decoder
Each represents 32 wires
Fuse can be implemented as a diode or a pass transistor
ELCT 501: Digital System
Design
Winter 2011
Programming the 32x8 ROM
22
0 1 2
29 30 31
D7 D6 D5 D4 D3 D2 D1 D0
A4
A3
A2
A1
A0
5-to-32 Decoder
Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 1 1 0 0 0 1 0 1
0 0 0 0 1 1 0 0 0 1 0 1 1
0 0 0 1 0 1 0 1 1 0 0 0 0
… … … … … … … … … … … … …
1 1 1 0 1 0 0 0 1 0 0 0 0
1 1 1 1 0 0 1 0 1 0 1 1 0
1 1 1 1 1 1 1 1 0 0 0 0 1
ELCT 501: Digital System
Design
Winter 2011
Example: Lookup Table
23 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
X F(X)=X2
0 0
1 1
2 4
3 9
4 16
5 25
6 36
7 49
X F(X)=X2
000 000000
001 000001
010 000100
011 001001
100 010000
101 011001
110 100100
111 110001
Design a square lookup table for F(X)=X2 using ROM
ELCT 501: Digital System
Design
Winter 2011
Square Lookup Table using ROM
24 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
X F(X)=X2
000 000000
001 000001
010 000100
011 001001
100 010000
101 011001
110 100100
111 110001
0
1
2
3
F5 F4 F3 F2 F1 F0
X2
X1
X0
3-to-8 Decoder 4
5
6
7
ELCT 501: Digital System
Design
Winter 2011
Square Lookup Table using ROM
25 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
X F(X)=X2
000 000000
001 000001
010 000100
011 001001
100 010000
101 011001
110 100100
111 110001
0
1
2
3
F5 F4 F3 F2 F1 F0
X2
X1
X0
3-to-8 Decoder 4
5
6
7
=X0
Not used
ELCT 501: Digital System
Design
Winter 2011
Square Lookup Table using ROM
26 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
X F(X)=X2
000 000000
001 000001
010 000100
011 001001
100 010000
101 011001
110 100100
111 110001
0
1
2
3
F5 F4 F3 F2 F0
X2
X1
X0
3-to-8 Decoder 4
5
6
7
F1
ELCT 501: Digital System
Design
Winter 2011
Classifying Three Basic PLDs
27 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Fixed AND plane (decoder)
Programmable OR plane
Programmable Connections
(Programmable) Read-Only Memory (ROM)
INPUT OUTPUT
Programmable OR plane
Programmable Connections
Programmable Logic Array (PLA)
Programmable AND plane
INPUT OUTPUT
Programmable AND plane
Fixed OR plane
Programmable Array Logic (PAL) Devices PAL: trademark of AMD, use PAL as an adjective or expect to receive a letter from AMD’s lawyers
INPUT OUTPUT
F/F
ELCT 501: Digital System
Design
Winter 2011
Programmable Logic Array (PLA)
28 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
C
B
A
C C B B A A
Programmable AND Plane
Programmable OR Plane
F2
ELCT 501: Digital System
Design
Winter 2011
Example using PLA
29 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
m(0,5,6,7)C)B,F2(A,
m(0,1,2,4) C)B,F1(A,
CBAACABF2
BCACABF1
CBCABAF1
ELCT 501: Digital System
Design
Winter 2011
Example using PLA
30 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
C
B
A
C C B B A A
CBAACABF2
BCACABF1
AB
AC
BC
A B C
F2 F1
ELCT 501: Digital System
Design
Winter 2011
PLA Device
31 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
A
B
IO1
IO2
IO1 IO1 B B A A IO2 IO2
Programmable AND Plane
Fixed OR Plane
ELCT 501: Digital System
Design
Winter 2011
PLA Device Design Example
32 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
A
B
IO1
IO2
IO1 IO1 B B A A
DCBADCADCBACABIO2
DCBACABIO1
D D C C
Not programmed
ELCT 501: Digital System
Design
Winter 2011
CPLD and FPGA [brown & Rose 96]
33 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Complex Programmable Logic Device (CPLD)
Multiple PLDs (e.g. PALs, PLAs) with Programmable interconnection
structure
Pioneered by Altera
Field-Programmable Gate Array (FPGA)
High logic capacity with large distributed interconnection structure
Logic capacity= number of 2-input NAND gates
Offers more narrow logic resources
CPLD offers logic resources with a wide number of inputs (AND planes)
Offer a higher ratio of Flip-flops to logic resources than CPLD
High Capacity PLD (HCPLD) is often used to refer to both CPLD and FPGA
ELCT 501: Digital System
Design
Winter 2011
CPLD Structure
34 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
PLD PLD PLD PLD
PLD PLD PLD PLD
Logic block
Interconnects
I/O block
ELCT 501: Digital System
Design
Winter 2011
FPGA Structure
35 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Logic block
I/O block
Interconnects
ELCT 501: Digital System
Design
Winter 2011
FPGA Programmability
36 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Floating gate transistor
Used in EPROM and EEPROM
SRAM-controlled switch-Control
Pass transistors
Multiplexers (to determine how to route inputs)
Antifuse
Similar to fuse
Originally an Open-Circuit
One-Time Programmable (OTP)
ELCT 501: Digital System
Design
Winter 2011
References
37 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Logic and Computer Design Fundamentals
by M. Morris Mano and Charles R. Kime. 4th
edition, Prentice Hall. 2008.
P. Marwedel: Embedded System Design,
Springer, 2006
“First Steps with Embedded Systems” Byte
Craft Limited
ELCT 501: Digital System
Design
Winter 2011
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