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Decoder Mano Section 4.9
18

Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Dec 24, 2015

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Jane Moore
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Page 1: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Decoder

Mano Section 4.9

Page 2: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Outline

• Decoder• Applications• Verilog

Page 3: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Example of a Decoder

Convert binary information from n input lines to 2n unique outputlines.

This particular circuit take a binary number and convert it to an octal number.

Page 4: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Hardware Implementation

Page 5: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

AND and NOR Decoders

Take an n-bit address.Produce 2n outputs,One of which is activated.

(NOR Decoder)

Page 6: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Organization of Memory Systems

Page 7: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Basic SRAM and VTC

A wordline is used to select the cellBitlines are used to perform read and write operations on the cell

Page 8: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Cross Coupled Configuration

The cell can only flip its internal state when one of its internal cross VS.During a read op, we must not disturb its current state.During a write op, we must force the internal voltage to swing past VS to change a state.

Page 9: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

A 2-to-4 decoder with Enable

(typo, should be a 0)

Page 10: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Demultiplexer

A Demux is a circuit that receives information from a singleline and directs it to one of 2n possible output lines.

Page 11: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Use a 2-to-4 decoder as a Demux

(typo, should be a 0)

Treat A and B as the selector bits. i.e. A and B select which bit should receive infomraiton.E is treated as the data line.

Page 12: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Implement a Full Adder with a Decoder

Page 13: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Build a Bigger Decoders

Use w to enable either top or bottom decoder.

Page 14: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

3-to-8 decoder in verilog

Page 15: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

3-to-8 decode

Input bits

Page 16: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Use a Test Bench to Generate output

Initial statements execute oncestarting from time 0.

$monitor: display variable whenever a value changes.$time display the simulation time

Page 17: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

Run functional Simulation

Page 18: Decoder Mano Section 4.9. Outline Decoder Applications Verilog.

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