Datorteknik TopologicalSort bild 1 To verify the structure Easy to hook together combinationals and flip-flops Harder to make it do what you want.

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Datorteknik TopologicalSort bild 1

To verify the structure

Easy to hook together combinationals and flip-flops

Harder to make it do what you want

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To verify the structure

We want to check:

Does my structure contain combinatorial loops?

We want to compute:

What values are being computed

by the structure right now? (simulation)

We will need to estimate:

How fast can we clock this structure (timing analysis)

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To verify the structure

These three problems are all related to each other

The underlying concepts are graphtheoretical

We use topological sort

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Answer:

Impossible to be sure by “inspection”

We need a procedure

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Where do we begin?

...... At the primary inputs

But ...

What is an input to the circuit?

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Inputs

Here’s one!

It’s a “break”. There is nothing “upstream”

As far backwards as we can go

&

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Is there a path through this?

D Q

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The D- flip flop

Combinationally, the D-flip flop is like this:

D Q

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Branch

logic

Sgn/Ze

extend

Zero ext.

ALU

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The procedure

Visit_line (p);

Mark line

For each component connected

Visit_component (p)

End;

Visit_component (q)

Mark input [save q]

If all inputs marked then

Calculate output

For all outputs

Visit_line (output)

End;Main

For all inputs

Visit_line (value)

If all lines visited then OK

Else Combinatorial loop

End;

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Combinational loop

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Static timing analysis

Use the topological sort procedure

Use max delay as component output

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Compiled simulation

Use the topological sort procedure

Use logic function as component output

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4, Propagate NEG INPUT

1010

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NEG

POS

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