Datorteknik TopologicalSort bild 1 To verify the structure Easy to hook together combinationals and flip-flops Harder to make it do what you want
Apr 01, 2015
Datorteknik TopologicalSort bild 1
To verify the structure
Easy to hook together combinationals and flip-flops
Harder to make it do what you want
Datorteknik TopologicalSort bild 2
To verify the structure
We want to check:
Does my structure contain combinatorial loops?
We want to compute:
What values are being computed
by the structure right now? (simulation)
We will need to estimate:
How fast can we clock this structure (timing analysis)
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To verify the structure
These three problems are all related to each other
The underlying concepts are graphtheoretical
We use topological sort
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Answer:
Impossible to be sure by “inspection”
We need a procedure
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Where do we begin?
...... At the primary inputs
But ...
What is an input to the circuit?
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Inputs
Here’s one!
It’s a “break”. There is nothing “upstream”
As far backwards as we can go
&
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Is there a path through this?
D Q
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The D- flip flop
Combinationally, the D-flip flop is like this:
D Q
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Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
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A
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Add one
Equal?Left shiftone bit
B
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The procedure
Visit_line (p);
Mark line
For each component connected
Visit_component (p)
End;
Visit_component (q)
Mark input [save q]
If all inputs marked then
Calculate output
For all outputs
Visit_line (output)
End;Main
For all inputs
Visit_line (value)
If all lines visited then OK
Else Combinatorial loop
End;
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+
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1
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Equal?Left shiftone bit
A
1
M
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A
1
M
M
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Equal?Left shiftone bit
A
1
M
M
M
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A
1
M
M
M
2
M M
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A
1
M
M
M
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M M
3
M
M
M
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A
1
M
M
M
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M M
3
M
M
M
4
M
M
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A
1
M
M
M
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M M
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M
M
M
4
M
M
5
M
M
M
M
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Equal?Left shiftone bit
A
1
M
M
M
2
M M
3
M
M
M
4
M
M
5
M
M
M
M
M
M
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1
2
43
Add one
Equal?Left shiftone bit
B
1
M M
M
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1
2
43
Add one
Equal?Left shiftone bit
B
1
M M
M
2
M M
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1
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43
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Equal?Left shiftone bit
B
1
M M
M
2
M M
3
M
M
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+
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1
2
43
Add one
Equal?Left shiftone bit
B
1
M M
M
2
M M
3
M
M
4
M
M
M
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1
2
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Add one
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B
1
M M
M
2
M M
3
M
M
4
M
M
M
Combinational loop
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Static timing analysis
Use the topological sort procedure
Use max delay as component output
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2
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A
32
15
26
20
18
8
0
00
0
0
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1
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A
1
0
8
8
32
15
26
20
18
8
0
00
0
0
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1
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Equal?Left shiftone bit
A
1
2
20
0
8
8
32
15
26
20
18
8
0
00
0
0
0
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0
8
8
32
15
26
20
18
8
0
00
0
0
+
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1
2
5
3
4
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Equal?Left shiftone bit
A
1
2
0 20
3
40
40
0
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0
8
8
32
15
26
20
18
8
0
00
0
0
+
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1
2
5
3
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Add one
Equal?Left shiftone bit
A
1
2
0 20
3
40
40
0
4
00
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A
1
2
3
4
5
0
15
5581
0
8
8
32
15
26
20
18
8
0
00
0
0
0 2040
40
0
00
0
26
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A
1
2
3
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5
15
8140
0
26
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Compiled simulation
Use the topological sort procedure
Use logic function as component output
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A
5
47
11
1
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A
1
12
5
47
11
1
2
2
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A
1
2
655
47
11
112
2
2
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1
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-9
-9
11
5
47
11
1
65
12
2
2
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7
5
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11
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-9
-9
11
65
12
2
2
7
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77
4
5
47
11
1
-9
-9, N=1
11
65
12
2
2
4, Propagate NEG INPUT
1010
0
NEG
POS
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10-9
7
0