Chapter 11_1 (chap 10 ed 8) Digital Logic. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 2 NOT AND OR XOR NAND NOR Truth Tables Boolean.

Chapter 11_1 (chap 10 ed 8)

Digital Logic

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

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• NOT• AND• OR• XOR• NAND• NOR• Truth Tables

Boolean Operators

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

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• NOT A = Ā • A AND B = AB• A OR B = A + B• A XOR B = 1 if and only if

one of A or B is 1

• A NAND B = NOT ( A AND B)• NOR = NOT (A OR B)• Truth Tables

Boolean Operators

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

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Boolean Algebra• Based on symbolic logic, designed by George

Boole• Boolean expressions created from:– NOT, AND, OR

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

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NOT• Inverts (reverses) a boolean value• Truth table for Boolean NOT operator:

NOT

Digital gate diagram for NOT:

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

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AND• Truth table for Boolean AND operator:

AND

Digital gate diagram for AND:

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

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OR• Truth table for Boolean OR operator:

OR

Digital gate diagram for OR:

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

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Operator Precedence• Examples showing the order of operations:

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

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Truth Tables (1 of 3)• A Boolean function has one or more Boolean

inputs, and returns a single Boolean output.• A truth table shows all the inputs and outputs

of a Boolean function

Example: X Y

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

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Truth Tables (2 of 3)• Example: X Y

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

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Truth Tables (3 of 3)• Example: (Y S) (X S)

muxX

Y

S

Z

Two-input multiplexer

Basic Identities of Boolean AlgebraBasic Postulates

A • B = B • A A + B = B + A Commutative Laws

A • (B + C) = (A • B) + (A • C) A + (B • C) = (A + B) • (A + C) Distributive Laws

1 • A = A 0 + A = A Identity Elements

A • = 0 A + = 1 Inverse Elements

Other Identities

0 • A = 0 1 + A = 1

A • A = A A + A = A

A • (B • C) = (A • B) • C A + (B + C) = (A + B) + C Associative Laws

DeMorgan's Theorem

A A

A B A B A B A B

De Morgan’s Theorem

• A NOR B = (NOT A) AND (NOT B)• A NAND B = (NOT A) OR (NOT B)

Basic Logic Gates

NAND Gates

NOR Gates

Functionally complete set

• AND, OR and NOT can be implemented fully with NAND gates or NOR gates

• Thus it is called a functionaly complete set.

Sum-of-Products Implementation of Table 11.3

Sum of products

F = ABC + ABC + ABC

Product-of-Sums Implementationof Table 11.3

Product of sums

(XYZ) = X + Y + Z (De Morgan)

Simplification of Boolean expression

• Algebraic simplification• Karnaugh maps• Quine McKluskey Tables

Algebraic simplification

Show how to simplifyF = ABC + ABC + ABC

To become

F = AB + BC= B(A + C)

Impementation of F

F = ABC + ABC + ABC

Simplified implementation of F = ABC + ABC + ABC = B(A + C)

Karnaugh Maps

The use of Karnaugh maps

Overlapping groups F = ABC + ABC + ABC

= B(A + C)

The Quine-McKluskey Method

2nd stageAll pairs that differ in one variable

Last stage

Final stage

• Circle each x that is alone in a column.• Then place a square around each X in any row

in which there is a circled X. • If every column now has either a squared or a

circled X, then we are done, and those row elements whose Xs have been marked constitute the minimal expression.

ABC + ACD + ABC + ACD

A B C F

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0

Table 11.3 A Boolean Function of Three Variables

NAND

MultiplexorS2 S1 F

0 0 D0

0 1 D1

1 0 D2

1 1 D3

Multiplexor implementation

Decoder

Use of decoders

To address 1K byte memory using four 256 x 8 bit RAM chips

Small-scale integration

• Early integrated circuit provided from one to ten gates on a chip.

• The next slide shows a few examples of these SSI chips.

Programmable Logic Array (PLA)

Programmable Logic Array (PLA)

Read-only memory

A 64 bit ROM

Binary Addition Truth Tables

Table 11.9 Binary Addition Truth Tables

4-Bit Adder

Implementation of an Adder

Multi-output adder

The output from each adder depends on the output from the previous adder.

Thus there is an increasing delay from the least significant to the most significant bit.

For larger adders the accumulated delay can become unacceptably high.

32-Bit Adder using 8-Bit Adders

Carry look ahead