Advances in Clockless and Mixed-Timing Digital Systems
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Advances in Clockless and Mixed-Timing Digital Systems
Prof. Steven M. Nowick
Email: nowick@cs.columbia.edu
Department of Computer ScienceColumbia University
OUTLINE
I. Asynchronous & Mixed-Timing Design: Overview & Recent Developments
II. Low-Latency Interface Circuits for
Mixed-Timing Domains
Trends and Challenges
Trends in Chip Design: next decade• “Semiconductor Industry Association (SIA) Roadmap”
(97-8)
Unprecedented Challenges:• complexity and scale (= size of systems)
• clock speeds
• power management
• “time-to-market”
Design becoming unmanageable using a centralized
(synchronous) approach….
Trends and Challenges (cont.)
1. Clock Rate:
• 1980: several MegaHertz
• 2001: ~750 MegaHertz - 1+ GigaHertz
• 2004: several GigaHertz
Design Challenge:• “clock skew”: clock must be near-simultaneous
across entire chip
Trends and Challenges (cont.)
2. Chip Size and Density:
Total #Transistors per Chip: 60-80% increase/year
– ~1970: 4 thousand (Intel 4004)
– today: 10-20+ million
– 2004 and beyond: 100 million-1 billion
Design Challenges: • system complexity, design time, clock distribution• soon, clock will not reach across chip in 1 cycle!
Trends and Challenges (cont.)
3. Power Consumption
• Low power: ever-increasing demand
– consumer electronics: battery-powered
– high-end processors: avoid expensive fans,
packaging
Design Challenge:• clock inherently consumes power continuously
• “power-down” techniques: only partly effective
Trends and Challenges (cont.)
4. Design Re-Use, Scalability
Increasing pressure for faster “time-to-market”. Need: • reusable components: “plug-and-play” design
• scalable design: easy system upgrades
Design Challenge: mismatch w/ central fixed-rate clock
Trends and Challenges (cont.)
5. Future Trends: “Mixed Timing” DomainsChips themselves becoming distributed
systems…. • contain many sub-regions, operating at different
speeds:
Design Challenge:Design Challenge: breakdown of single centralbreakdown of single centralclock controlclock control
Introduction Synchronous vs. Asynchronous Systems?
• Synchronous Systems: use a global clock– entire system operates at fixed-rate
– uses “centralized control”
clock
Introduction (cont.)
Synchronous vs. Asynchronous Systems? (cont.)
• Asynchronous Systems: no global clock
– components can operate at varying rates
– communicate locally via “handshaking”
– uses “distributed control”
“handshaking interfaces”
Introduction (cont.)
Asynchronous Circuits:– long history (since early 1950’s), but...
– early approaches often impractical: slow, complex
Synchronous Circuits: – used almost everywhere: highly successful
– benefits: simplicity, support by existing design tools
But recently: renewed interest in asynchronous circuits
Asynchronous Design
Several Potential Advantages:
• Lower Power– no clock ==> components use power only “on demand”
• Robustness, Scalability– no global timing==>“mix-and-match” varied components
• Higher Performance– systems not limited to “worst-case” clock rate
Asynchronous Design: Challenges
Critical Design Issues:• components must communicate cleanly = “hazard-free”
• highly-concurrent designs: much harder to understand!
Lack of Existing Design Tools:• most commercial “CAD” tools targeted to synchronous
Asynchronous Design: Recent Commercial Interest
1. Philips Semiconductors [86-present]• async chips now in commercial pagers, cell phones• 3-4x lower power than synchronous• much lower electromagnetic interference (EMI)
2. Motorola/Theseus Logic [99-]• Joint venture: develop async embedded processor
3. Intel [96-98]• experimental high-speed design: instruction-length decoder• 3-4x faster than synchronous
Asynchronous Design: Recent Commercial Interest
4. Sun Labs [~95-present]• experimental high-speed pipelines, routing fabric, systems
5. IBM Research [~98-present]• experimental high-speed pipelines, etc.
6. Several recent async startups:• Theseus Logic (Florida)• ADD (Pasadena)• Self-Timed Solutions (UK)
My Research: Highlights
3 Main Asynchronous Areas:
1. CAD Tools: optimization algorithms + software
packages
2. High-Speed Asynchronous Pipelines
3. Interface Circuits: for mixed-timing domains
My Research: Funding
NSF: 2 Large-Scale “ITR” Awards ($2.5 Million) [2000]
1. “CAD Tools” to Design/Optimize Asynchronous Systems
(joint with USC)
2. 3rd-Generation Wireless Systems (async, very low power)
(joint with Columbia EE - Ken Shepard)
Other Funding: NSF, Sun, NYS CAT, Sloan Fdtn.
1. Developing Asynchronous CAD Tools
Focus: 2 types of CAD tools(a) for individual controllers (i.e., finite-state machines) (b) for entire digital systems
(a) The “MINIMALIST” Package [ICCAD-91/95/97/99, DAC-96]– R. Fuhrer, M. Theobald– Downloaded to 60+ sites/18+ countries
(b) High-Level Synthesis Package [DAC-01, DATE-02]– M. Theobald, T. Chelcea
Include: many sophisticated optimization algorithmsGoal: provide many options for design-space exploration
1(a). Synthesizing A ControllerUsing the “MINIMALIST” CAD Tool
Inputs:req-sendtreqrd-iqadbld-outack-pkt
Outputs:tackpeackadbld
0
1
2
7
3
4
5
6
8
9
10
req-send+ treq+ rd-iq+/adbld+
adbld-out+/peack+
rd-iq-/peack- adbld- tack+
adbld-out- treq-rd-id+/ adbld+
adbld-out+/peack+
rd-iq-/ peack- adbld- tack-
adbld-out- treq+ ack-pkt+/ peack+ tack+
ack-pkt- treq-/peack- tack-
treq-/tack-
treq+/tack+
ack-pkt+/peack- tack-
adbld-out-treq- ack-pkt+/
peack+
req-send-/--
adbld-out- treq+ rd-iq+/ adbld+From HP Labs
“Mayfly” Project
EXAMPLE (cont.):
Examples:
Basic Digital Building Blocks = datapath components • adders, multipliers, dividers, …• central to almost all digital systems
Asynchronous Design: several potential advantages• high speed (not limited by commercial clock rates)
• adaptible interfacing (easy reuse in different environments)
Goal: • new architectures + designs for very fast async
datapath components
Use Pipelining: to improve performance
2. High-Speed Digital Design
global clock
SYNCHRONOUS
ASYNCHRONOUS
PIPELINED COMPUTATION: like an assembly line
no global clock
2. High-Speed Digital Design
FunctionBlock Completion
Detector
Datain
Dataout
PC
AN ASYNCHRONOUS PIPELINE: Williams/Horowitz (Stanford 86-91)
2. High-Speed Digital Design
Our Goal: extremely high-speed digital components• much faster than commercial processors
Contribution: 3 new async pipeline styles [Singh/Nowick]dynamic logic:
1. Lookahead Pipelines [Async-00]
2. High-Capacity Pipelines [ISSCC-02, Async-02, WVLSI-00]
static logic:
3. MOUSETRAP Pipelines [ICCD-01]
2. High-Speed Digital Design
Contributions (cont.):
• introduce novel highly-concurrent protocols
• basic operating speed: ~3.5+ GigaHertz [0.25 micron]
• gracefully handle variable input/output rates
Technology Transfer: IBM T.J. Watson [2000-2001]• in fabricated experimental FIR filter chip (for disk
drives)
2. High-Speed Digital Design
Critical challenge: interface sync/async, sync/sync systems -- operating at different clock rates
--robustly, at high-speed!
ASYNCSYSTEM
Interface Circuits = “glue circuits”
SYNCSYSTEM:CLOCK 1
SYNCSYSTEM:CLOCK 2
3. Robust Interface Circuitsfor “Mixed-Timing” Domains
[DAC-01]
4. Low-Power Applications
Now investigating several promising async
applications:
• 3rd-Generation Wireless Systems (with K. Shepard, EE)
– very low power, reconfigurable to different standards
• Embedded Processors
– used in cell phones, automobiles, digital cameras, ...
5. Tech Transfer: IBM Research
Invited to transfer pipeline technology:
• PhD Student (Montek Singh): 5-month internship (5-12/00)
• IBM Application: filter design
– async design -- sandwiched between sync interfaces
• Fabricated Chip: evaluated in Feb.-March 2001
• Benefits: “adaptive-pipelining” [ISSCC-02]
Potential for future use in IBM products….
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