32-bit Arm Cortex -M0+ MCU with BLE Transparent ... · 32-bit Arm ® Cortex -M0+ MCU with BLE Transparent Transmission Controller Features • Operating Voltage: 3.3V (Typical) •
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Rev. 1.00 1 October 26, 2017 Rev. 1.00 PB October 26, 2017
BC32F7611 32-bit Arm® Cortex®-M0+ MCU with
BLE Transparent Transmission Controller
Features• OperatingVoltage:3.3V(Typical)• Core
♦ 32-bitArm®Cortex®-M0+processorcore ♦ 0.93DMIPS/MHz(Dhrystonev2.1) ♦ Upto40MHzoperatingfrequency
• On-chipMemory ♦ 64KBFlashMemory ♦ 8KBSRAM
• ClockControlUnit ♦ External4~16MHzcrystaloscillator ♦ External32.768kHzcrystaloscillator ♦ Internal8MHz(±2%)RCoscillator ♦ Internal32kHzRCoscillator
• Peripherals ♦ GPIO:22GPIOspin-sharedwithotheralternativefunctions
♦ ADC:6externalchannels1MSPS12-bitSARADC ♦ twoI2Cinterfaceswithaspeedupto1MHz ♦ OneUniversalSynchronous/AsynchronousReceiver/Transmitter–USART
♦ TwoUniversalAsynchronousReceiver/Transmitters–UART
♦ Master/SlaveSPIcontrollerwithFIFO ♦ One16-bitGeneral-PurposeCounter/Timerswith4independentinputchannels
♦ One16-bitup-counterSingle-ChannelTimerwith6inputchannels
♦ MotorControlTimer ♦ CRC-16/32generator ♦ Real-timeClock(RTC)withalarmfunction ♦ WatchdogTimer
• DebugSupport ♦ SerialWireDebugPort–SW-DP
• BLE ♦ IntegratedhighperformanceRFandMODEMforBLE(BluetoothLowEnergy)applications
♦ On-chip capacitors for BLE 32MHz crystaloscillator
♦ IntegratedDC/DCconverterandLDOsallowingawidersupplyrangewithasinglepowersupply
♦ Over75dBRXgainandprogrammablegainsteps ♦ Sleep,Deep-SleepandPower-Downmodesforlowpowerconsumption
♦ Few external components required forBLEapplications
• PowerManagement ♦ Multiplepowersavingmodes:Sleep,Deep-Sleep1andDeep-Sleep2forlowpowerconsumption
• Packagetype:46-pinQFN–6.5mm×4.5mm
Applications• Healthcareproducts• Smarthomeappliances• Beacons
General DescriptionTheBC32F7611deviceisafully-integrated,single-chipBLESoC (SystemonChip)microcontrollerbased around a high performance, low powerconsumption32-bitArm®Cortex®-M0+ processorcore.TheBLEfunctionisdesignedtoactasaBLEslavecontroller in accordancewith theBluetoothspecificationv4.1.
Thedeviceoperatesata frequencyofup to40MHzwithaFlashacceleratortoobtainmaximumefficiency.Itprovides64KBofembeddedFlashmemory forcode/data storage and8KBof embeddedSRAMmemoryforsystemoperationandapplicationprogramusage.Avarietyofperipherals, suchasADC, I2C,USART,UART,SPI,GPTM,SCTM,MCTM,CRC-16/32,RTC,WDT,SW-DP(SerialWireDebugPort),etc., are also implemented in thisdevice.Severalpowersavingmodesprovidetheflexibilityformaxi-mumoptimizationbetweenwakeuplatencyandpow-erconsumption,anespeciallyimportantconsiderationinlowpowerapplications.
Theabovefeaturesensure that thedevice issuitableforuse inawiderangeofapplications,especially inareassuchaswhitegoodsapplicationcontrol,powermonitors,alarmsystems,consumerproducts,handheldequipment,data loggingapplications,health careproducts,smarthomeandsoon.
Moreover,duringtheintervalswithnoactiveBLERFconnection,TheBC32F7611worksinthesleepmodewhichcanfurtherlyreducepowerconsumption.
Rev. 1.00 2 October 26, 2017
BC32F7611
Block Diagram
WDT
PWRCU
GPTM
RTC
SPI
I2C 0~1
BFTM 0~1
SCTM
12-bit ADC
USART
UART 0~1
AFIO
EXTI
MCTM
AHB2APB
MOSI, MISO, SCK, SEL
SDA, SCL
CH0~CH3
SCMT0~SCMT3
TX, RXTX, RX,
RTS, CTS
ADC_IN2~7
BRK, CH1~CH3,CH1N~CH2N
GPIO
Bus Matrix
Cortex-M0+Processor
SWCLK,SWDIO SW_DP
PA: 0~5,9,12~15PB: 0~4,9~14
POR /PDR
HSE HSIXTALOUT
XTALINLDOBOD
LVD
PLL
CLDO
LSE LSIX32KOUT
X32KIN
BLE
RF+
Controller
BLE_SPI
DCDC_SW
VOUT_15
WAKEUP
INT_EXT
RST_N
PVIN
RFIO
VDDRF_15
VDDIF_15
DVDD_12
RFGND
VDDLO_15
SRA
M 8K
B
Flash 64KB
XI
XO
AlternateFunctions
nRST
WAKEUP
VDDVSSAVDD
Rev. 1.00 3 October 26, 2017
BC32F7611
Memory Map
Reserved
Reserved
Reserved
GPIO A~B
Reserved
Reserved
Reserved
BFTM1BFTM0
GPTM
RTC/PWRCU
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x4002_2000
UART1
Reserved
Up to 64 KB on-chip Flash
0x0000_0000
Reserved0x0001_0000
Boot loader0x1F00_0000
Reserved0x1F00_0800
Option byte alias0x1FF0_0000
Up to64 KB
2 KB
1 KB
Reserved0x1FF0_0400
Code
SRAM
Peripheral
Up to 8 KB on-chip SRAM
0x2000_0000
Reserved
0x2000_2000
8 KB
APB peripherals0x4000_0000
AHB peripherals0x4008_0000
0x4010_0000
Private peripheral bus0xE000_0000
Reserved
0xE010_0000
0xFFFF_FFFF
512 KB
512 KB
USART0x4000_0000UART00x4000_1000
SPI
BLE_SPI
0x4000_4000
I2C1
0x4000_5000
I2C0
ADCReserved
0x4001_0000
EXTI0x4002_3000
0x4004_5000
AFIO
0x4002_4000
WDT
0x4004_2000 Reserved
0x4003_6000
0x4004_8000
0x4002_C000
0x4006_9000
0x4002_D000
0x4006_B0000x4006_A000
0x4004_A000
0x4006_E000
0x4003_4000
APB
FMC0x4008_0000Reserved0x4008_2000
CKCU/RSTCU0x4008_8000CRC0x4008_A000
0x400F_FFFF
AHB
0x4000_2000
0x4004_4000
0x4002_5000
0x4004_1000
0x4008_C000
0x400B_00000x400B_1000
0x4001_1000
0x4004_9000
0x4006_8000
0x4006_F000
0x4007_60000x4007_70000x4007_8000
SCTM0SCTM20x4003_5000
SCTM1SCTM3
0x4007_40000x4007_5000
Reserved0x400A_80000x400A_A0000x400A_C000
0x4004_3000
ReservedReserved
Reserved
MCTM
Rev. 1.00 4 October 26, 2017
BC32F7611
Register Map Start Address End Address Peripheral Bus0x4000_0000 0x4000_0FFF USART
APB
0x4000_1000 0x4000_1FFF UART00x4000_2000 0x4000_3FFF Reserved0x4000_4000 0x4000_4FFF SPI0x4000_5000 0x4001_9FFF Reserved0x4001_0000 0x4001_0FFF ADC0x4001_1000 0x4002_1FFF Reserved0x4002_2000 0x4002_2FFF AFIO0x4002_3000 0x4002_3FFF Reserved0x4002_4000 0x4002_4FFF EXTI0x4002_5000 0x4002_BFFF Reserved0x4002_C000 0x4002_CFFF MCTM0x4002_D000 0x4003_3FFF Reserved0x4003_4000 0x4003_4FFF SCTM00x4003_5000 0x4003_5FFF SCTM20x4003_6000 0x4004_0FFF Reserved0x4004_1000 0x4004_1FFF UART10x4004_2000 0x4004_2FFF Reserved0x4004_3000 0x4004_3FFF Reserved0x4004_4000 0x4004_4FFF BLE_SPI0x4004_5000 0x4004_7FFF Reserved0x4004_8000 0x4004_8FFF I2C00x4004_9000 0x4004_9FFF I2C10x4004_A000 0x4006_7FFF Reserved0x4006_8000 0x4006_8FFF WDT0x4006_9000 0x4006_9FFF Reserved0x4006_A000 0x4006_AFFF RTC/PWRCU0x4006_B000 0x4006_DFFF Reserved0x4006_E000 0x4006_EFFF GPTM0x4006_F000 0x4007_3FFF Reserved0x4007_4000 0x4007_4FFF SCTM10x4007_5000 0x4007_5FFF SCTM30x4007_6000 0x4007_6FFF BFTM00x4007_7000 0x4007_7FFF BFTM10x4007_8000 0x4007_FFFF Reserved0x4008_0000 0x4008_1FFF FMC
AHB
0x4008_2000 0x4008_7FFF Reserved0x4008_8000 0x4008_9FFF CKCU/RSTCU0x4008_A000 0x4008_BFFF CRC0x4008_C000 0x400A_7FFF Reserved0x400A_8000 0x400A_BFFF Reserved0x400A_C000 0x400A_FFFF Reserved0x400B_0000 0x400B_1FFF GPIOA0x400B_2000 0x400B_3FFF GPIOB0x400B_4000 0x400B_5FFF Reserved0x400B_6000 0x400F_FFFF Reserved
Rev. 1.00 5 October 26, 2017
BC32F7611
Pin Assignment
RFIO
VD
DR
F_15
PB
1
PA15
X32KOUT/PB11
DC
DC
_SW
AV
DD
WA
KEU
P
PA2
DVDD_12
PA14
PA
9_BO
OT
SWC
LK/PA12
PB0
RFGND
PB
4
XI
VDD
VDD
IF_15
NC
RFG
ND
VDDLO_15
PA0
XTALOUT/PB14
SW
DIO
/PA
13
I NT_E
XT
RST_N
DC_TEST
XO
RFGND
PV
IN
PB2
PB3
VSSnRST
PB9X32KIN/PB10
PB12XTALIN/PB13
NC
VDDRF_15
PA
5
PA
3
CLD
O
PA
4
PA
1
VO
UT_15
BC32F761146 QFN-A
123456789
10 11 12 13 14 15 16 17 18 19 20 21 22
343536373839
23242526272829303132
3340414243444546
Expose Pad
Note:Notallpin-sharedfunctionsareshowninthepinassignment,refertothePinAlternateFunctionMappingtableformoredetails.
Pin DescriptionPin Name Pin No. I/O Description
VDD 1 P Digital power supply; 2.2V~3.6VVSS 2 P Connect to groundnRST 3 DI MCU core reset inputPB9 4 IO General Purpose I/O / MT_CH3X32KIN/PB10 5 IO X32KIN / General Purpose I/O / GT_CH0 / USR_TX / SCTM2X32KOUT/PB11 6 IO X32KOUT / General Purpose I/O / GT_CH1 / USR_RX / SCTM3PB12 7 IO PB12 / SPI_MISO / UR0_RX / SCTM0 / WAKEUPXTALIN/PB13 8 AIO Crystal Input / PB13 / UR0_TX / I2C0_SCLXTALOUT/PB14 9 AIO Crystal Output / PB14 / UR0_RX / I2C0_SDAPA9_BOOT 10 DI General Purpose I/O / Boot mode selections / SPI_MOSI / SCTM3 / CKOUTSWCLK/PA12 11 DIO Serial-Wired debug clock input / PA12SWDIO/PA13 12 DIO Serial-Wired debug data pin / PA13PA14 13 IO General Purpose I/O / MT_CH0 / USR_RTS / I2C1_SCLPA15 14 IO General Purpose I/O / MT_CH0N / USR_CTS / I2C1_SDA / SCTM1PB0 15 IO General Purpose I/O / MT_CH1 / USR_TX / I2C0_SCLPB1 16 IO General Purpose I/O / MT_CH1N / USR_RX / I2C0_SDA / SCTM2PB2 17 IO General Purpose I/O / MT_CH2 / SPI_SEL / UR1_TXPB3 18 IO General Purpose I/O / MT_CH2N / SPI_SCK / UR1_RX / SCTM1PB4 19 IO General Purpose I/O / MT_BRK / SPI_MOSI / UR1_TX / SCTM0VDDIF_15 20 P Analog power for IF part, connect to VOUT_15
VDDRF_15 21 P Analog power for RF part, connect to VOUT_15
RFIO 22 AIO RF input or outputRFGND 23 P RF Power GroundVDDRF_15 24 P Analog power for RF part, connect to VOUT_15DC_TEST 25 AO Test pin for RF functionVDDLO_15 26 P Analog power for RF part, connect to VOUT_15
Rev. 1.00 6 October 26, 2017
BC32F7611
Pin Name Pin No. I/O DescriptionXI 27 AI BLE 32MHz Crystal oscillator inputXO 28 AO BLE 32MHz Crystal oscillator output
DVDD_12 29 P Internal digital power 1.2V, require a 0.1μF capacitor to RFGND
RFGND 30 P RF Power GroundNC 31 — Connect to groundNC 32 — Connect to groundRST_N 33 DI BLE hardware reset inputINT_EXT 34 DO BLE External InterruptWAKEUP 35 DI BLE Wakeup pinPVIN 36 DI BLE Power-supply; 2.2V~3.6VVOUT_15 37 P 1.5V power outputDCDC_SW 38 P Switching Output. Connect this pin to the switching end of the inductorAVDD 39 P +3.3V Analog Power supply PA0 40 AIO General Purpose I/O / ADC_IN2 / GT_CH0 / USR_RTS / I2C1_SCLPA1 41 AIO General Purpose I/O / ADC_IN3 / GT_CH1 / USR_CTS / I2C1_SDAPA2 42 AIO General Purpose I/O / ADC_IN4 / GT_CH2 / USR_TXPA3 43 AIO General Purpose I/O / ADC_IN5 / GT_CH3 / USR_RXPA4 44 AIO General Purpose I/O / ADC_IN6 / GT_CH0 / SPI_SCK / UR1_TX / I2C0_SCLPA5 45 AIO General Purpose I/O / ADC_IN7 / GT_CH1 / SPI_MISO / UR1_RX / I2C0_SDA
CLDO 46 P MCU Core power LDO 1.5V output. It is recommended to connect a 1μF capacitor as close as possible between this pin and VSS.
RFGND EP P
Exposed Pad on the bottom of the package. Internally connected to RFGND. Solder this exposed pad to a PCB pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the noted RF performance.
Legend:AI=AnalogInput;AO=AnalogOutput;AIO=AnalogInput/Output,DI=DigitalInput;DO=DigitalOutput;P=Power
Rev. 1.00 7 October 26, 2017
BC32F7611
Pin Alternate Function MappingTheBC32F7611usesthesamearchitectureastheCoretex-M0+32-bitStandardMCU(http://www.holtek.com.tw/producthome/-/pid/35/164/165),fortheMCUfilepleasedirectlyrefertotheHT32F52241relateddocuments(http://www.holtek.com.tw/productdetail/-/vg/HT32F52231-41_HT32F52331-41).
Thefollowingtableis thePinAlternateFunctionMappingoftheBC32F7611,notethedifferencebetweentheBC32F7611andHT32F52241whenusingtheHT32F52241relateddocuments.
AF0 AF1 AF2 AF4 AF5 AF6 AF7 AF13 AF15
Pin No. SystemDefault GPIO ADC GPTM
/MCTM SPI USART/UART I2C SCTM System
Other4 PB9 MT_CH35 X32KIN PB10 GT_CH0 USR_TX SCTM26 X32KOUT PB11 GT_CH1 USR_RX SCTM37 PB12 SPI_MISO UR0_RX SCTM0 WAKEUP8 XTALIN PB13 UR0_TX I2C0_SCL9 XTALOUT PB14 UR0_RX I2C0_SDA
10 PA9_BOOT SPI_MOSI SCTM3 CKOUT11 SWCLK PA1212 SWDIO PA1313 PA14 MT_CH0 USR_RTS I2C1_SCL14 PA15 MT_CH0N USR_CTS I2C1_SDA SCTM115 PB0 MT_CH1 USR_TX I2C0_SCL16 PB1 MT_CH1N USR_RX I2C0_SDA SCTM217 PB2 MT_CH2 SPI_SEL UR1_TX18 PB3 MT_CH2N SPI_SCK UR1_RX SCTM119 PB4 MT_BRK SPI_MOSI UR1_TX SCTM040 PA0 ADC_IN2 GT_CH0 USR_RTS I2C1_SCL41 PA1 ADC_IN3 GT_CH1 USR_CTS I2C1_SDA42 PA2 ADC_IN4 GT_CH2 USR_TX43 PA3 ADC_IN5 GT_CH3 USR_RX44 PA4 ADC_IN6 GT_CH0 SPI_SCK UR1_TX I2C0_SCL45 PA5 ADC_IN7 GT_CH1 SPI_MOSI UR1_RX I2C0_SDA
Electrical Characteristics
Absolute Maximum Ratings
SupplyVoltage........................... VIN-0.3VtoVIN+3.6VInputVoltage.............................. VIN-0.3VtoVIN+0.3V
StorageTemperature.......................... -50°Cto125°COperatingTemperature............................0°Cto70°C
Note:Thesearestressratingsonly.Stressesexceedingtherangespecifiedunder“AbsoluteMaximumRatings”maycausesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedin thespecificationisnot impliedandprolongedexposuretoextremeconditionsmayaffectdevicereliability.
Rev. 1.00 8 October 26, 2017
BC32F7611
BLE D.C. CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. UnitVIN Power Supply Voltage(Note) — 2.2 3.3 3.6 VDigital InputsVIH High Level Input Voltage — 0.7×VIN — — VVIL Low Level Input Voltage — — 0.2×VIN VIIH High Level Input Current — — 10 — μAIIL Low Level Input Current — — 10 — μACI Input Capacitance — — 5 — pFDigital OutputsVOH High Level Output Voltage IOH = 1mA VIN-0.5 — — VVOL Low Level Output Voltage IOL = 1mA — — 0.5 VIOZ High Impedance Output Current — — — 1 μASupply Current (Ta=25°C, VIN=3.3V, unless otherwise specified)IRX RX Mode — 14.5 — mAITX TX Mode, 0dBm Output Power — 9 — mAISLEEP Idle Mode when MCU sleep — 13 20 μAIACT Idle Mode when MCU active — 2 — mAIPDN Power-Down — 280 360 μA
Note:IftheBC32F7611deviceisoperatingundertheconditionwhereVIN<2.2V,theLDOmodemustbeselected.Howeveritwillconsumemorepower.
BLE A.C. CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Min. Typ. Max. UnitCrystal Oscillator
Frequency — 32 — MHzFrequency Accuracy Requirement -40 — 40 ppm
ESR Equivalent Series Resistance — — 100 ΩC0 Crystal Shunt Capacitance 1.5 7 — pFCL Crystal Load Capacitance 8 12 16 pFRX CharacteristicsPSENS Sensitivity — -90 — dBm
Sensitivity(Dirty On) — -88 — dBmPIN Maximum Input Power — -5 — dBmCI0
In-band Blocking
Co-channel interference — 12 — dBCI1 Interfere at fOFFS = +/- 1MHz — -2/4 — dBCI2 Interfere at fOFFS = +/- 2MHz — -25/-35 — dBCI3 Interfere at fOFFS = +/- 3MHz — -40/-40 — dBCI4 Interfere at fIMAGE — -35 — dBCI5 Interfere at fIMAGE +/- 1MHz — 4/-38 — dB
Out-of-band Blocking
f = 30 ~ 2000MHz — -20 — dBmf = 2000 ~ 2399MHz — -25 — dBmf = 2484 ~ 3000MHz — -25 — dBmf = 3000 ~ 12750MHz — -30 — dBm
Intermodulation performance for wanted signal at -64dBm and 1 Mbps BLE, 3rd, 4th and 5th offset channel
— -40 — dBm— — — —
Rev. 1.00 9 October 26, 2017
BC32F7611
Symbol Parameter Min. Typ. Max. UnitTX CharacteristicPTX Output Power -18 — +3 dBm
TX RF Output Steps — 6 — dBΔF2AVG Average Frequency Deviation for 10101010 Pattern — 230 — kHzΔF1AVG Average Frequency Deviation for 11110000 Pattern — 260 — kHzEO Eye Opening = ΔF2AVG/ΔF1AVG — 0.88 —
Frequency Accuracy -50 — +50 kHzMaximum Frequency Drift — 30 — kHzInitial Frequency Drift — 10 — kHz
FDR Drift Rate — 0.2 — kHz/50μs
Spurious Emissions
Frequency < 2.4GHz — -50 — dBmFrequency in 2.4 ~ 12GHz — -40 — dBm
In-band Emissions
< f ± 2MHz (f = 2400 ~ 2483.5MHz, PTX = 0dBm) — -51 — dBm> f ± 3MHz (f = 2400 ~ 2483.5MHz, PTX = 0dBm) — -55 — dBm
CLDO Voltage Regulator CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VLDOInternal Regulator Output Voltage
VDD ≥ 2.0V regulator input @ ILDO = 35mA, voltage variant = ±5% after trimming 1.425 1.5 1.57 V
ILDO Output Current VDD = 2.0V regulator input @ VLDO = 1.5V — 30 35 mA
CLDOExternal Filter Capacitor Value for Internal Core Power Supply
The capacitor value is dependent on the core power current consumption — 1 — μF
Power ConsumptionTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. Unit
IDD
Supply Current (Run Mode)
VDD = 3.3V, HSE = 8MHz, PLL = 40MHz, fHCLK = 40MHz, fPCLK = 40MHz, all peripherals enabled
— 12 — mA
VDD = 3.3V, HSE = 8MHz, PLL = 40MHz, fHCLK = 40MHz, fPCLK = 40MHz, all peripherals disabled
— 7 — mA
VDD = 3.3V, HSE off, PLL off, LSI on, fHCLK = 32kHz, fPCLK = 32kHz, all peripherals enabled
— 45 — μA
VDD = 3.3V, HSE off, PLL off, LSI on, fHCLK = 32kHz, fPCLK = 32kHz, all peripherals disabled
— 40 — μA
Supply Current (Sleep Mode)
VDD = 3.3V, HSE = 8MHz, PLL = 40MHz, fHCLK = 0MHz, fPCLK = 40MHz, all peripherals enabled
— 7.5 — mA
VDD = 3.3V, HSE = 8MHz, PLL = 40MHz, fHCLK = 0MHz, fPCLK = 40MHz, all peripherals disabled
— 2 — mA
Supply Current (Deep-Sleep1 Mode)
VDD = 3.3V, all clock off (HSE/PLL/fHCLK), LDO in low power mode, LSI on, RTC on — 35 — μA
Supply Current (Deep-Sleep2 Mode)
VDD = 3.3V, all clock off (HSE/PLL/fHCLK), LDO off DMOS on, LSI on, RTC on — 5 — μA
Notes:1.HSEmeanshighspeedexternaloscillator;HSImeans8MHzhighspeedinternaloscillator.2.LSEmeans32.768kHzlowspeedexternaloscillator;LSImeans32kHzlowspeedinternaloscillator.3.RTCmeansrealtimeclock.4.Code=while(1)208NOPexecutedinFlash.
Rev. 1.00 10 October 26, 2017
BC32F7611
Reset and Supply Monitor CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VPORPower-On Reset Threshold(Rising Voltage on VDD)
Ta = 0°C ~ 70°C1.66 1.79 1.90 V
VPDRPower-Down Reset Threshold(Falling Voltage on VDD) 1.49 1.64 1.78 V
VPORHYST POR Hysteresis — — 150 — mVtPOR Reset Delay Time VDD = 3.3V — 0.1 0.2 ms
Notes:1.Databasedoncharacterizationresultsonly,nottestedinproduction.2.Guaranteedbydesign,nottestedinproduction.
3.IftheLDOisturnedon,theVDDPORhastobeinthede-assertioncondition.WhentheVDDPORisintheassertionstatethentheLDOwillbeturnedoff.
LVD/BOD CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VBOD Brown Out Detection VoltageTa = 0°C ~ 70°Cafter factory-trimmed (VDD falling edge)
2.02 2.1 2.18 V
VLVD Low Voltage Detection Voltage Ta = 0°C ~ 70°C(VDD falling edge)
LVDS = 000 2.17 2.25 2.33 VLVDS = 001 2.32 2.4 2.48 VLVDS = 010 2.47 2.55 2.63 VLVDS = 011 2.62 2.7 2.78 VLVDS = 100 2.77 2.85 2.93 VLVDS = 101 2.92 3.0 3.08 VLVDS = 110 3.07 3.15 3.23 VLVDS = 111 3.22 3.3 3.38 V
VLVDHTST LVD Hysteresis VDD = 3.3V — — 100 — mVtsuLVD LVD Setup Time VDD = 3.3V — — — 5 μstatLVD LVD Active Delay Time VDD = 3.3V — — — — μsIDDLVD Operation Current (3) VDD = 3.3V — — 5 15 μA
Notes:1.Databasedoncharacterizationresultsonly,nottestedinproduction.2.Guaranteedbydesign,nottestedinproduction.
3.Bandgapcurrentisnotincluded.
4.TheLVDSfieldisinthePWRCULVDCSRregister
Rev. 1.00 11 October 26, 2017
BC32F7611
External Clock CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. UnitHigh Speed External Clock (HSE) CharacteristicsVDD Operation Range — 2.0 — 3.6 V
fHSEHigh Speed External Oscillator Frequency (HSE) — 4 — 16 MHz
CLHSE Load Capacitance VDD = 3.3V, RESR = 100Ω @ 16MHz — — 22 pF
RFHSEInternal Feedback Resistor between XTALIN and XTALOUT Pins — — 1 — MΩ
RESR Equivalent Series Resistance
VDD = 3.3V, CL = 12pF @16MHz, HSEDR= 0
— — 160 ΩVDD = 2.4V, CL = 12pF @16MHz, HSEDR = 1
DHSE HSE Oscillator Duty Cycle — 40 — 60 %IDDHSE HSE Oscillator Current Consumption VDD = 3.3V @ 16MHz — TBD — mAIPWDHSE HSE Oscillator Power-Down Current VDD = 3.3V — — 0.01 μAtSUHSE HSE Oscillator Startup Time VDD = 3.3V — — 4 msLow Speed External Clock (LSE) CharacteristicsVBAK Operation Range — 2.0 — 3.6 VfCK_LSE LSE Frequency VBAK = 2.0V ~ 3.6V — 32.768 — KHzRF Internal Feedback Resistor — — 10 — MΩRESR Equivalent Series Resistance VBAK = 3.3V 30 — TBD kΩCL Recommended Load Capacitance VBAK = 3.3V 6 — TBD pF
IDDLSE
Oscillator Supply Current(High Current Mode)
fCK_LSE = 32.768kHz, RESR = 50kΩ, CL ≥ 7pF, VBAK = 2.0V ~ 2.7V, Ta = 0°C ~ 70°C
— 3.3 6.3 μA
Oscillator Supply Current(Low Current Mode)
fCK_LSE = 32.768kHz, RESR = 50kΩ, CL < 7pF, VBAK = 2.0V ~ 3.6V,Ta = 0°C ~ 70°C
— 1.8 3.3 μA
Power-Down Current — — — 0.01 μA
tsuLSE Startup Time ( Low Current Mode) fCK_LSI = 32.768kHz, VBAK = 2.0V ~ 3.6V 500 — — ms
Note:ThefollowingguidelinesarerecommendedtoincreasethestabilityoftheHSE/LSEcrystalcircuitsinthePCBlayout.
1.ThecrystaloscillatorshouldbelocatedascloseaspossibletotheMCUtokeepthetracelengthsasshortaspossibletoreduceanyparasiticcapacitance.
2.Shieldlinesinthevicinityofthecrystalbyusingagroundplanetoisolatesignalsandreducenoise.
3.Keepanyhighfrequencysignallinesawayfromthecrystalareatopreventanycrosstalkadverseeffects.
Rev. 1.00 12 October 26, 2017
BC32F7611
Internal Clock CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. UnitHigh Speed Internal Clock (HSI) CharacteristicsVDD Operation Range — 2.0 — 3.6 VfHSI HSI Frequency VDD = 3.3V @ 25°C — 8 — MHz
ACCHSIFactory Calibrated HSI Oscillator Frequency Accuracy
VDD = 3.3V, Ta = 25°C -2 — 2 %VDD = 2.5V ~ 3.6V, Ta = 0°C ~ 70°C -3 — 3 %
VDD = 2.0V ~ 3.6V,Ta = 0°C ~ 70°C -4 — 4 %
Duty Duty Cycle fHSI = 8MHz 35 — 65 %IDDHSI Oscillator Supply Current
fHSI = 8MHz— 300 500 μA
Power-Down Current — — 0.05 μAtsuHSI Startup Time fHSI = 8MHz — — 10 μsLow Speed Internal Clock (LSI) Characteristics
fLSILow Speed Internal Oscillator Frequency (LSI) VDD = 3.3V, Ta = 0°C ~ 70°C 21 32 43 kHz
ACCLSI LSI Frequency Accuracy After factory-trimmed, VDD = 3.3V, Ta = 25°C -10 — +10 %
IDDLSI LSI Oscillator Operating Current VDD = 3.3V, Ta = 25°C — 0.4 0.8 μAtSULSI LSI Oscillator Startup Time VDD = 3.3V, Ta = 25°C — — 100 μs
PLL CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. UnitfPLLIN PLL Input Clock — 4 — 16 MHzfCK_PLL PLL Output Clock — 16 — 40 MHztLOCK PLL Lock Time — — 200 — μs
Flash Memory CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. Unit
NENDUNumber of Guaranteed Program/Erase Cycles before Failure (Endurance) Ta = 0°C ~ 70°C 10 — — K cycles
tRET Data Retention Time Ta = 0°C ~ 70°C 10 — — YearstPROG Word Programming Time Ta = 0°C ~ 70°C 20 — — μstERASE Page Erase Time Ta = 0°C ~ 70°C 2 — — mstMERASE Mass Erase Time Ta = 0°C ~ 70°C 10 — — ms
Rev. 1.00 13 October 26, 2017
BC32F7611
I/O Ports CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. Unit
IIL Low Level Input Current3.3V I/O VI = VSS,
On-chip pull-up resister disabled
— — 3 μA
Reset pin — — 3 μA
IIH High Level Input Current3.3V I/O VI = VDD,
On-chip pull-down resister disabled
— — 3 μA
Reset pin — — 3 μA
VIL Low Level Input Voltage3.3V I/O -0.5 — VDD×0.35 VReset pin -0.5 — VDD×0.35 V
VIH High Level Input Voltage3.3V I/O VDD×0.65 — VDD+0.5 VReset pin VDD×0.65 — VDD+0.5 V
VHYSSchmitt Trigger InputVoltage Hysteresis
3.3V I/O — 0.12×VDD — mVReset pin — 0.12×VDD — mV
IOLLow Level Output Current(GPIO Sink Current)
3.3V I/O 4mA drive, VOL = 0.4V 4 — — mA3.3V I/O 8mA drive, VOL = 0.4V 8 — — mA3.3V I/O 12mA drive, VOL = 0.4V 12 — — mA3.3V I/O 16mA drive, VOL = 0.4V 16 — — mABackup Domain I/O drive @ VDD = 3.3V, VOL = 0.4V, PB10, PB11, PB12
4 — — mA
IOHHigh Level Output Current(GPIO Source Current)
3.3V I/O 4mA drive, VOH = VDD - 0.4V 4 — — mA
3.3V I/O 8mA drive, VOH = VDD - 0.4V 8 — — mA
3.3V I/O 12mA drive, VOH = VDD - 0.4V 12 — — mA
3.3V I/O 16mA drive, VOH = VDD - 0.4V 16 — — mA
Backup Domain I/O drive @ VDD = 3.3V, VOL = VDD - 0.4V, PB10, PB11, PB12
— — 2 mA
VOL Low Level Output Voltage
3.3V 4mA drive I/O, IOL = 4mA — — 0.4 V3.3V 8mA drive I/O, IOL = 8mA — — 0.4 V3.3V 12mA drive I/O, IOL = 12mA — — 0.4 V3.3V 16mA drive I/O, IOL = 16mA — — 0.4 V
VOH High Level Output Voltage
3.3V 4mA drive I/O, IOH = 4mA VDD-0.4 — — V3.3V 8mA drive I/O, IOH = 8mA VDD-0.4 — — V3.3V 12mA drive I/O, IOL = 12mA VDD-0.4 — — V3.3V 16mA drive I/O, IOL = 16mA VDD-0.4 — — V
RPU Internal Pull-up Resistor 3.3V I/O — 46 — kΩRPD Internal Pull-down Resistor 3.3V I/O — 46 — kΩ
Rev. 1.00 14 October 26, 2017
BC32F7611
ADC CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. UnitVDDA Operating Voltage — 2.7 3.3 3.6 VVADCIN A/D Converter Input Voltage Range — 0 — VREF+ VVREF+ A/D Converter Reference Voltage — — VDDA VDDA VIADC Current Consumption VDDA = 3.3V — 1 TBD mAIADC_DN Power-Down Current Consumption VDDA = 3.3V — — 0.1 μAfADC A/D Converter Clock — 0.7 — 16 MHzfS Sampling Rate — 0.05 — 1 MHztDL Data Latency — — 12.5 — 1/fADC CyclestS&H Sampling & Hold Time — — 3.5 — 1/fADC CyclestADCCONV A/D Converter Conversion Time — — 16 — 1/fADC CyclesRI Input Sampling Switch Resistance — — — 1 kΩ
CI Input Sampling Capacitance No pin/pad capacitance included — 16 — pF
tSU Startup Up Time — — — 1 μsN Resolution — — 12 — bitsINL Integral Non-linearity Error fS = 750kHz, VDDA = 3.3V — ±2 ±5 LSBDNL Differential Non-linearity Error fS = 750kHz, VDDA = 3.3V — ±1 — LSBEO Offset Error — — — ±10 LSBEG Gain Error — — — ±10 LSB
Notes:1.Guaranteedbydesign,nottestedinproduction.2.ThefigurebelowshowstheequivalentcircuitoftheA/DConverterSample-and-Holdinputstagewhere
CI isthestoragecapacitor,RIistheresistanceofthesamplingswitchandRSistheoutputimpedanceofthesignalsourceVS.Normallythesamplingphasedurationisapproximatelyequalto3.5/fADC.Thecapacitance,CI,mustbechargedwithinthistimeframeanditmustbeensuredthatthevoltageatitsterminalsbecomessufficientlyclosetoVSforaccuracy.Toguaranteethis,RSisnotallowedtohaveanarbitrarilylargevalue.
SAR ADC
CI
sample
RI
RS
VS
ADC Sampling Network Model
Theworstcaseoccurswhentheextremitiesoftheinputrange(0VandVREF)aresampledconsecutively.Inthissituationasamplingerrorbelow¼LSBisensuredbyusingthefollowingequation:
INIADC
S RCf
R)2ln(
5.32+<
WherefADCistheADCclockfrequencyandNistheADCresolution(N=12inthiscase).Asafemarginshouldbeconsideredduetothepin/padparasiticcapacitances,whicharenotaccountedforinthissimplemodel.
If,inasystemwheretheA/DConverterisused,therearenorail-to-railinputvoltagevariationsbetweenconsecu-tivesamplingphases,RSmaybelargerthanthevalueindicatedbytheequationabove.
Rev. 1.00 15 October 26, 2017
BC32F7611
SCTM/GPTM/MCTM CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. UnitfTM Timer Clock Source for GPTM — — — 40 MHztRES Timer Resolution Time — 1 — — fTM
fEXT External Single Frequency on Channel 1~4 — — — 1/2 fTM
RES Timer Resolution — — — 16 bits
I2C CharacteristicsTa=25°C, unless otherwise specified
Symbol ParameterStandard Mode Fast Mode Fast Mode Plus
UnitMin. Max. Min. Max. Min. Max.
fSCL SCL Clock Frequency — 100 — 400 — 1000 kHztSCL(H) SCL Clock High Time 4.5 — 1.125 — 0.45 — μstSCL(L) SCL Clock Low Time 4.5 — 1.125 — 0.45 — μstFALL SCL and SDA Fall Time — 1.3 — 0.34 — 0.135 μstRISE SCL and SDA Rise Time — 1.3 — 0.34 — 0.135 μstSU(SDA) SDA Data Setup Time 500 — 125 — 50 — nstH(SDA) SDA Data Hold Time 0 — 0 — 0 — nstSU(STA) START Condition Setup Time 500 — 125 — 50 — nstH(STA) START Condition Hold Time 0 — 0 — 0 — nstSU(STO) STOP Condition Setup Time 500 — 125 — 50 — ns
Notes:1.Guaranteedbydesign,nottestedinproduction.2.Toachieve100kHzstandardmode,theperipheralclockfrequencymustbehigherthan2MHz.
3.Toachieve400kHzfastmode,theperipheralclockfrequencymustbehigherthan8MHz.
4.Toachieve1MHzfastmodeplus,theperipheralclockfrequencymustbehigherthan20MHz.
5.TheabovecharacteristicparametersoftheI2Cbustimingarebasedon:SEQ_FILTER=01andCOMB_FILTER_Enisdisabled.
tSU(STA)
tH(STA)
tFALL
tSCL(L)
tRISE
tSCL(H)
tH(SDA) tSU(SDA) tSU(STO)
SCL
SDA
I2C Timing Diagram
Rev. 1.00 16 October 26, 2017
BC32F7611
SPI CharacteristicsTa=25°C, unless otherwise specified
Symbol Parameter Test Conditions Min. Typ. Max. UnitSPI Master Mode
fSCK (1/tSCK) SPI Master Output SCK Clock Frequency
Master modeSPI peripheral clock frequency fPCLK
— — fPCLK/2 MHz
tSCK(H)
tSCK(L)SCK Clock High and Low Time — tSCK/2-2 — tSCK/2+1 ns
tV(MO) Data Output Valid Time — — — 5 nstH(MO) Data Output Hold Time — 2 — — nstSU(MI) Data Input Setup Time — 5 — — nstH(MI) Data Input Hold Time — 5 — — nsSPI Slave Mode
fSCK (1/tSCK) SPI Slave Input SCK Clock Frequency
Slave modeSPI peripheral clock frequency fPCLK
— — fPCLK/3 MHz
DutySCKSPI Slave Input SCK Clock Duty Cycle — 30 — 70 %
tSU(SEL) SEL Enable Setup Time — 3×tPCLK — — nstH(SEL) SEL Enable Hold Time — 2×tPCLK — — nstA(SO) Data Output Access Time — — — 3×tPCLK nstDIS(SO) Data Output Disable Time — — — 10 nstV(SO) Data Output Valid Time — — — 25 nstH(SO) Data Output Hold Time — 15 — — nstSU(SI) Data Input Setup Time — 5 — — nstH(SI) Data Input Hold Time — 4 — — ns
Note:tSCK=1/fSCK;tPCLK=1/fPCLK.fSCK:SPIoutput(input)clockfrequency;fPCLK:SPIperipheralclockfrequency.
Rev. 1.00 17 October 26, 2017
BC32F7611
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
MISO
MOSI
MISO
tSCK(H) tSCK(L)
tSCK
DATA VALID DATA VALID
DATA VALID DATA VALID
DATA VALID
DATA VALID
DATA VALID
DATA VALID
tV(MO)
CPHA = 0
CPHA = 1
tH(MO)
tH(MI)tSU(MI)
tV(MO) tH(MO)
tSU(MI) tH(MI)
DATA VALID
DATA VALID
DATA VALID
DATA VALID
SPI Timing Diagram – SPI Master Mode
SCK(CPOL=0)
SCK (CPOL=1)
MOSI
MISO
tSCK(H) tSCK(L)
tSCK
MSB/LSB OUT
MSB/LSB IN
tV(SO) tH(SO)
tSU(SI) tH(SI)
SEL
LSB/MSB OUT
LSB/MSB IN
tA(SO)
tSU(SEL)
tDIS(SO)
tH(SEL)
SPI Timing Diagram – SPI Slave Mode with CPHA=1
Rev. 1.00 18 October 26, 2017
BC32F7611
Functional Description
MCU CoreTheCortex®-M0+core is a very lowgate count,highlyenergyefficientprocessorthatis intendedformicrocontrolleranddeeplyembeddedapplicationsthatrequireanareaoptimized, low-powerprocessor.TheprocessorisbasedontheARMv6-MarchitectureandsupportsThumb®instructionsets,single-cycleI/Oport,hardwaremultiplierandlowlatencyinterruptrespondtime.
• 32-bitArm®Cortex®-M0+processorcore• Upto40MHzoperatingfrequency• 0.93DMIPS/MHz(Dhrystonev2.1)• Single-cyclemultiplication• IntegratedNestedVectoredInterruptController(NVIC)
• 24-bitSysTicktimer
Bluetooth Low Energy controller – BLEIt isdesignedtoactasaBLEslaveaccordingtotheBluetoothspecificationv4.1.
• On-chipcapacitorsinthe32MHzcrystalcircuittoreducetheBOM
• On-chipDC/DCconverterforawidepowerrangeoftheBLEcontroller
• 75dBRXgainandthegainstepisprogrammable• SupportSleep andPower-Downmode for lowpowerconsumption
• Embeddedpatchmemorytoreducesystemeffortandcost
On-Chip MemoryThe Arm®Cortex®-M0+processor accesses anddebugaccessesshare thesingleexternal interfacetoexternalAHBperipheral.Theprocessoraccessestakepriorityoverdebugaccesses.ThemaximumaddressrangeoftheCortex®-M0+is4GBsinceithasa32-bitbusaddresswidth.Additionally,apre-definedmemorymap is provided by theCortex®-M0+ processorto reduce the software complexity of repeatedimplementationbydifferentdevicevendors.However,some regionsareusedby the Arm®Cortex®-M0+systemperipherals.RefertotheArm®Cortex®-M0+TechnicalReferenceManual formore information.TheMemoryMapchapter shows thememorymapof theBC32F7611device, includingcode,SRAM,peripheral,andotherpre-definedregions.
• 64KBon-chipFlashmemoryfor instruction/dataandoptionsstorage
• 8KBon-chipSRAM• Supportsmultiplebootmodes
Flash Memory Controller – FMCTheFlashMemoryController,FMC,providesallthenecessaryfunctionsandpre-fetchbufferfor theem-beddedon-chipFlashMemory.SincetheaccessspeedoftheFlashMemoryisslowerthantheCPU,awideaccessinterfacewithapre-fetchbufferandcacheareprovidedfortheFlashMemoryinordertoreducetheCPUwaitingtimewhichwillcauseCPUinstructionexecutiondelays.FlashMemorywordprogram/pageerasefunctionsarealsoprovided.
• Flashacceleratorformaximumefficiency• 32-bitwordprogrammingwithInSystemProgrammingInterface(ISP)andInApplicationProgramming(IAP)
• Flashprotectioncapabilitytopreventillegalaccess
Reset Control Unit – RSTCUTheResetControlUnit,RSTCU,has threekindsofreset,apoweronreset,asystemresetandanAPBunitreset.Thepoweronreset,knownasacoldreset,resetsthefullsystemduringpowerup.Asystemresetresets theprocessorcoreandperipheral IPcompo-nentswiththeexceptionoftheSW-DPcontroller.Theresetscanbetriggeredbyanexternalsignal,internaleventsandtheresetgenerators.
• Supplysupervisor ♦ PowerOnReset/Power-DownReset–POR/PDR ♦ Brown-outDetector–BOD ♦ ProgrammableLowVoltageDetector–LVD
MCU Clock Control Unit – CKCUTheClockControlunit,CKCU,providesarangeofoscillatorandclockfunctions.TheseincludeaHighSpeedInternalRCoscillator(HSI),aHighSpeedEx-ternalcrystaloscillator(HSE),aLowSpeedInternalRCoscillator (LSI),aLowSpeedExternalcrystaloscillator (LSE),aPhaseLockLoop(PLL),aHSEclockmonitor,clockprescalers,clockmultiplexers,APBclockdividerandgatingcircuitry.TheAHB,APBandCortex®-M0+clocksarederivedfromthesystemclock (CK_SYS)whichcancomefromtheHSI,HSEorPLL.TheWatchdogTimerandRealTimeClock(RTC)useeithertheLSIorLSEastheirclocksource.
• External4to16MHzcrystaloscillator• External32.768kHzcrystaloscillator• Internal8MHzRCoscillatortrimmedto±2%accuracyat3.3Voperatingvoltageand25°Coperatingtemperature
• Internal32kHzRCoscillator• IntegratedsystemclockPLL• Independentclockdividerandgatingbitsforperipheralclocksources
Rev. 1.00 19 October 26, 2017
BC32F7611
Power Management – PWRCUPowerconsumptioncanbe regardedasoneof themost important issues formanyembeddedsystemapplications.Accordingly thePowerControlUnit,PWRCU,inthisdeviceprovidesmanytypesofpowersavingmodes suchasSleep,Deep-Sleep1,Deep-Sleep2 andPower-Downmode.These operatingmodesreducethepowerconsumptionandallowtheapplicationtoachievethebesttrade-offbetweentheconflictingdemandsofCPUoperating time,speedandpowerconsumption.
• SingleVDDpowersupply:2.0Vto3.6V• Integrated1.5VLDOregulatorforCPUcore,periph-eralsandmemoriespowersupply
• VDDpowersupplyforRTC• Twopowerdomains:VDD,1.5V• Fourpowersavingmodes:Sleep,Deep-Sleep1,Deep-Sleep2,Power-Down
External Interrupt/Event Controller – EXTITheExternalInterrupt/EventController,EXTI,com-prises16edgedetectorswhichcangenerateawake-upeventor interrupt requests independently.EachEXTIlinecanalsobemaskedindependently.
• 16EXTIlineswithconfigurabletriggersourceandtype
• AllGPIOpinscanbeselectedasEXTItriggersource• Sourcetriggertypeincludeshighlevel, lowlevel,negativeedge,positiveedgeorbothedge
• Individualinterruptenable,wakeupenableandstatusbitsforeachEXTIline
• SoftwareinterrupttriggermodeforeachEXTIline• Integrateddeglitchfilterforshortpulseblocking
Analog to Digital Converter – ADCA12-bitmulti-channelADCisintegratedinthedevice.Therearemultiplexedchannels,whichinclude6externalanalogsignalchannelsand2internalchannelswhichcanbemeasured. If the inputvoltage is required toremainwithinaspecificthresholdwindow,anAnalogWatchdogfunctionwillmonitoranddetectthesesignals.Aninterruptwillthenbegeneratedtoinformthedevicethattheinputvoltageisnotwithinthepresetthresholdlevels.Therearethreeconversionmodestoconvertananalogsignaltodigitaldata.TheADCcanbeoperatedinoneshot,continuousanddiscontinuousconversionmodes.
• 12-bitSARADCengine• Upto1Mspsconversionrate• 6externalanaloginputchannels
I/O Ports – GPIOThereare22GeneralPurposeI/Opins,GPIO,namedfromPortA~B for the implementationof logicinput/outputfunctions.EachoftheGPIOportshasaseriesofrelatedcontrolandconfigurationregisterstomaximizeflexibilityandtomeettherequirementsofawiderangeofapplications.
TheGPIOportsarepin-sharedwithotheralternativefunctionstoobtainmaximumfunctionalflexibilityonthepackagepins.TheGPIOpinscanbeusedasalter-nativefunctionalpinsbyconfiguringthecorrespond-ingregisters regardlessof the inputoroutputpins.TheexternalinterruptsontheGPIOpinsofthedevicehaverelatedcontrolandconfigurationregistersintheExternalInterruptControlUnit,EXTI.
• 22GPIOs• PortAandBaremappedas16externalinterrupts–EXTI• AlmostallI/Opinshaveaconfigurableoutputdrivingcurrent
Motor Control Timer – MCTMTheMotorControlTimerconsistsofasingle16-bitup/downcounter,four16-bitCCRs(Capture/CompareRegisters),singleone16-bitcounter-reloadregister(CRR), single8-bit repetitioncounterandseveralcontrol/status registers. Itcanbeusedforavarietyofpurposesincludingmeasuringthepulsewidthsofinputsignalsorgeneratingoutputwaveformssuchascomparematchoutputs,PWMoutputsorcomplementaryPWMoutputswithdead-timeinsertion.TheMCTMiscapableofofferingfullfunctionalsupportformotorcontrol,hallsensorinterfacingandbrakeinput.
• One16-bitup,down,up/downauto-reloadcounter• 16-bitprogrammableprescalerallowingcounterclockfrequencydivisionbyanyfactorbetween1and65536
• InputCapturefunction• CompareMatchOutput• PWMwaveformgenerationwithEdge-alignedandCenter-alignedCountingModes
• SinglePulseModeOutput• ComplementaryOutputswithprogrammabledead-timeinsertion
• Supports3-phasemotorcontrol andhall sensorinterface
• Breakinputtoforcethetimer’soutputsignalsintoaresetorfixedcondition
Rev. 1.00 20 October 26, 2017
BC32F7611
PWM Generation and Capture Timers – GPTMTheGeneralPurposeTimerconsistsofone16-bitup/downcounter,four16-bitCapture/CompareRegisters(CCRs),one16-bitCounterReloadRegister(CRR)and several control/status registers.They canbeusedforavarietyofpurposesincludinggeneraltimemeasurement,inputsignalpulsewidthmeasurement,outputwaveformgeneration suchas singlepulsegenerationorPWMoutputgeneration.TheGPTMsupportsanEncoderInterfaceusingadecoderwithtwoinputs.
• One16-bitup,down,up/downauto-reloadcounter• 16-bitprogrammableprescalerallowingcounterclockfrequencydivisionbyanyfactorbetween1and65536
• InputCapturefunction• CompareMatchOutput• PWMwaveformgenerationwithEdge-alignedandCenter-alignedCountingModes
• SinglePulseModeOutput• Encoderinterfacecontrollerwithtwoinputsusingquadraturedecoder
Single Channel Generation and Capture Timers – SCTMTheSingle-ChannelTimerconsistsofone16-bitup-counter,one16-bitCapture/CompareRegister(CCR),one16-bitCounter-ReloadRegister(CRR)andseveralcontrol/statusregisters.Itcanbeusedforavarietyofpurposes includinggeneral timer, inputsignalpulsewidthmeasurementoroutputwaveformgenerationsuchassinglepulsegenerationorPWMoutput.
• One16-bitupandauto-reloadcounter• Onechannelforeachtimer• 16-bitprogrammableprescalerallowingcounterclockfrequencydivisionbyanyfactorbetween1and65536
• CompareMatchOutput• PWMwaveformgenerationwithEdge-aligned• SinglePulseModeOutput
Basic Function Timer – BFTMTheBasicFunctionTimer isasimplecount-up32-bitcounterdesigned tomeasure time intervalsandgenerateaoneshotorrepetitiveinterrupts.TheBFTMoperates in twofunctionalmodes, repetitiveoroneshotmode.IntherepetitivemodetheBFTMrestartsthecounterwhenacomparematcheventoccurs.TheBFTMalsosupportsaoneshotmodewhichforcesthecounter tostopcountingwhenacomparematcheventoccurs.
• One32-bitcompare/matchcount-upcounter–noI/Ocontrolfeatures
• Oneshotmode–countingstopsafteramatchcondition• Repetitivemode– restart counterafteramatchcondition
Watchdog Timer – WDTTheWatchdogTimerisahardwaretimingcircuitthatcanbeusedtodetectsystemfailuresduetosoftwaremalfunctions.Itincludesa12-bitcount-downcounter,aprescaler,aWDTdeltavalueregister,WDToperationcontrolcircuitryandaWDTprotectionmechanism.If thesoftwaredoesnotreloadthecountervaluebe-foreaWatchdogTimerunderflowoccurs,aresetwillbegeneratedwhenthecounterunderflows.Inaddi-tion,aresetisalsogeneratedif thesoftwarereloadsthecounterwhen thecountervalue isgreater thantheWDTdeltavalue.Thismeans thecountermustbereloadedwithina limitedtimingwindowusingaspecificmethod.TheWatchdogTimercountercanbestoppedwhiletheprocessorisinthedebugmode.There isaregisterwriteprotect functionwhichcanbeenabledtopreventitfromchangingtheWatchdogTimerconfigurationunexpectedly.
• 12-bitdowncounterwith3-bitprescaler• Reseteventforthesystem• Programmablewatchdogtimerwindowfunction• Registerwriteprotectionfunction
Real Time Clock – RTCThe Real Time Clock, RTC, includes an APBinterface,a24-bitcount-upcounter,acontrolregister,aprescaler,acompareregisterandastatusregister.Mostof theRTCcircuitsare located in theBackupDomain except for theAPB interface.TheAPBinterface is located in theVDD15powerdomain.Therefore,itisnecessarytobeisolatedfromtheISOsignal thatcomesfromthepowercontrolunitwhentheVDD15powerdomain ispoweredoff, that iswhenthedeviceenters thePower-Downmode.TheRTCcounterisusedasawakeuptimertogenerateasystemresumesignalfromthePower-Downmode.
• 24-bitup-counterwithaprogrammableprescaler• Alarmfunction• InterruptandWake-upevent
Rev. 1.00 21 October 26, 2017
BC32F7611
Inter-integrated Circuit – I2CTheI2Cisaninternalcircuitallowingcommunicationwithanexternal I2C interfacewhich isan industrystandard two line serial interfaceused forconnec-tiontoexternalhardware.Thesetwoserial linesareknownasaserialdata line,SDA,andaserialclockline,SCL.TheI2Cmoduleprovidesthreedatatransferrates:100kHzin theStandardmode,400kHzin theFastmodeand1MHzintheFastPlusmode.TheSCLperiodgenerationregister isused tosetupdifferentkindsofduty cycle implementations for theSCLpulse.
TheSDAlinewhichisconnecteddirectlytotheI2Cbus isabi-directionaldata linebetween themasterandslavedevicesand isusedfordata transmissionandreception.TheI2CalsohasanarbitrationdetectfunctionandclocksynchronizationtopreventsituationswheremorethanonemasterattemptstotransmitdatatotheI2Cbusatthesametime.
• Supports bothmaster and slavemodeswith afrequencyofupto1MHz
• Provideanarbitrationfunctionandclocksynchronization• Supports7-bitand10-bitaddressingmodesandgeneralcalladdressing
• Supports slavemulti-addressingmodewithmaskableaddress
Serial Peripheral Interface – SPITheSerialPeripheralInterface,SPI,providesanSPIprotocoldata transmitandreceivefunction inbothmasterandslavemode.TheSPIinterfaceuses4pins,whicharetheserialdatainputandoutputlinesMISOandMOSI,theclockline,SCK,andtheslaveselectline,SEL.OneSPIdeviceactsasamasterdevicewhichcontrolsthedataflowusingtheSELandSCKsignals to indicate thestartofdatacommunicationandthedatasamplingrate.Toreceiveadatabyte,thestreameddatabitsarelatchedonaspecificclockedgeandstoredinthedataregisterorintheRXFIFO.Datatransmissioniscarriedout inasimilarwaybut inareversesequence.Themodefaultdetectionprovidesacapabilityformulti-masterapplications.
• Supportsbothmasterandslavemode• Frequencyofupto(fPCLK/2)MHzforthemastermodeand(fPCLK/3)MHzfortheslavemode
• FIFODepth:8levels• Multi-masterandmulti-slaveoperation
Universal Synchronous Asynchronous Receiver Transmitter – USARTTheUniversalSynchronousAsynchronousReceiverTransceiver,USART,providesaflexiblefullduplexdataexchangeusingsynchronousorasynchronousdata transfer.TheUSARTisused to translatedatabetweenparallelandserialinterfaces,andiscommonlyusedforRS232standardcommunication.TheUSARTperipheral functionsupports four typesof interruptincludingLineStatus Interrupt,TransmitterFIFOEmptyInterrupt,ReceiverThresholdLevelReachingInterruptandTimeOutInterrupt.TheUSARTmoduleincludesatransmitterFIFO,(TX_FIFO)andreceiverFIFO(RX_FIFO).ThesoftwarecandetectaUSARTerrorstatusbyreadingtheLineStatusRegister,LSR.The status includes the typeand theconditionoftransferoperationsaswellasseveralerrorconditionsresultingfromParity,Overrun,FramingandBreakevents.
• Suppor ts both asynchronous and c lockedsynchronousserialcommunicationmodes
• Asynchronousoperatingbaudrateupto(fPCLK/16)MHzandsynchronousoperatingrateupto(fPCLK/8)MHz
• Fullduplexcommunication• Fully programmable serial communicationcharacteristicsincluding: ♦ Wordlength:7,8,or9-bitcharacter ♦ Parity:Even,odd,orno-paritybitgenerationanddetection
♦ Stopbit:1or2stopbitgeneration ♦ Bitorder:LSB-firstorMSB-firsttransfer
• Errordetection:Parity,overrun,andframeerror• Autohardwareflowcontrolmode–RTS,CTS• IrDASIRencoderanddecoder• RS485modewithoutputenablecontrol• FIFODepth:8×9bitsforbothreceiverandtransmitter
Rev. 1.00 22 October 26, 2017
BC32F7611
Universal Asynchronous Receiver Trans-mitter – UARTTheUniversalAsynchronousReceiverTransceiver,UART,providesaflexiblefullduplexdataexchangeusingasynchronous transfer.TheUARTisused totranslatedatabetweenparallelandserial interfaces,andiscommonlyusedforRS232standardcommuni-cation.TheUARTperipheral functionsupportsLineStatusInterrupt.ThesoftwarecandetectaUARTerrorstatusbyreadingtheLineStatusRegister,LSR.ThestatusincludesthetypeandtheconditionoftransferoperationsaswellasseveralerrorconditionsresultingfromParity,Overrun,FramingandBreakevents.
• Asynchronous serial communicationoperatingbaud-rateuptofPCLK/16MHz
• Fullduplexcommunication• Fullyprogrammableserialcommunicationcharacteristicsincluding: ♦ Wordlength:7,8,or9-bitcharacter ♦ Parity:Even,odd,orno-paritybitgenerationanddetection
♦ Stopbit:1or2stopbitgeneration ♦ Bitorder:LSB-firstorMSB-firsttransfer
• Errordetection:Parity,overrun,andframeerror
Cyclic Redundancy Check – CRCTheCRC calculation unit is an error detectiontechniquetestalgorithmwhichisusedtoverifydatatransmissionor storagedata correctness.ACRCcalculation takesadata streamorablockofdataas its inputandgeneratesa16-bitor32-bitoutputremainder.Ordinarily,adatastreamissuffixedbyaCRCcodeandusedasachecksumwhenbeingsentorstored.Therefore,thereceivedorrestoreddatastreamiscalculatedby thesamegeneratorpolynomialasdescribedabove.IfthenewCRCcoderesultdoesnotmatchtheonecalculatedearlier,thenthismeansthatthedatastreamcontainsadataerror.
• SupportCRC16polynomial:0x8005,X16+X15+X2+1
• SupportCCITTCRC16polynomial:0x1021,X16+X12+X5+1
• SupportIEEE-802.3CRC32polynomial:0x04C11DB7,X32+X26+X23+X22+X16+X12+X11+X10
+X8+X7+X5+X4+X2+X+1• Supports1’scomplement,bytereverse&bitreverseoperationondataandchecksum.
• Supportsbyte,half-word&worddatasize• ProgrammableCRCinitialseedvalue• CRCcomputationexecutedin1AHBclockcyclefor8-bitdataand4AHBclockcycles for32-bitdata
• SupportsPDMAtocompleteaCRCcomputationofablockofmemory
BLE Application Controller Interface TheBC32F7611BLEfunctionissetbytheinternalSPIinterface.FortheBLEprotocol, theWriteFIFOcommandmustbesent first foreachCMDfromthehosttotheBLEcontrollerandthereadFIFOcommandmustbesentfirstforeachReturnoperation.Datafollowsthelittle-endianformat.Commandsareshownbelow.
Abbreviation ExplanationBD Bluetooth DeviceBD_Addr Bluetooth Device AddressBD_Name Bluetooth Device Name
Rev. 1.00 23 October 26, 2017
BC32F7611
Opcode Read Command Write Command Description
0x30 IntvRead Read connection interval setting (only valid when connected)
0x31 BDNameRead BDNameWrite Read / write Bluetooth device name0x32 BaudRateRead BaudRateWrite Read / write UART baud rate0x33 BDAddrRead BDAddrWrite Read / write Bluetooth device address0x35 AdvIntvRead AdvIntvWrite Read / write Bluetooth device advertising interval
0x36 AdvDataRead AdvDataWrite Read / write manufacturer specific data field of advertising packet
0x37 WhiteListRead WhiteListWrite Read / write white list, devices which are not in white list will be rejected
0x38 TxPowerRead TxPowerWrite Read / write RF TX power0x3B BatteryLevelWrite Update Battery level let cell phone to read it
0x3F BaudRateUpdate Update new baud rate (baud rate must be set by BaudRateWrite first)
0x40 IntvLatencyWrite2 Write connection interval setting0x50 AdvDataWrite2 Write whole advertising packet0x51 ScanResDataWrite Write whole scan response packet0x5F DisconnectWrite Force to disconnect
Type Dir.Header Payload
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th ... Nth
Read Command M→S 0x20 Opcode
(byte×1)
Read Event M←S 0x21 Opcode(byte×1)
Length(byte×1)
Data(byte×Length, MSB)
Payload PacketCommand M↔S 0x22
Length(byte×1
max=200)
RF Payload(byte×Length, MSB)
Write Command M→S 0x25
Opcode(byte×1,
unit=byte×1)
Length(byte×1)
Data(byte×Length, MSB)
Write Event / Payload Packet Event
M←S 0x26Opcode(byte×1,
unit=byte×1)
Result(byte×1)
Write Physical Address M→S 0x55
Length(byte×1,
unit=byte×4,max=60)
Reserved(byte×2)
Address(byte×4,LSB)
Data(byte×Length×4,LSB)
Read Physical Address M→S 0x56
Length(byte×1,
unit=byte×4,max=60)
Address(byte×4)
Read Physical Address Return M←S 0x57
Length(byte×1,
unit=byte×4,max=60)
Reserved(byte×2)
Address(byte×4,LSB)
Data(byte×Length×4,LSB)
BLE ACI Protocol
Notes:1.“Dir.”Meansthetransferdetection.2.“M→S”:fromMastertoSlave;
“M←S”:fromSlavetoMaster;
where“M”istheMCUand“S”istheBLEdevice.
3.“Reserved”means0x00.
Rev. 1.00 24 October 26, 2017
BC32F7611
BLE Control InterfaceThe innerconnectionbetween theMCUandBLEcontrollerisdescribedasbelow.Thedeviceincludesa5-wire,8-bit,MSB-first,Motorola-compatiblewithCPOL=0andCPHA=0SPIinterface.Theinterfacehasthefollowingfeatures.
• Clockspeedupto10MHz• SupportsMode0only• Integrated32bytesRX/TXFIFOsforcontinuousbursts.
BLE SPI Signal nameBLE Signal
Name In/Out BLE SPI Description
SPI_CLK In ClockSPI_MOSI In Master output slave inputSPI_MISO Out Master input slave outputSPI_CS In EnableSPI_INT Out Interrupt request
BLE SPI Signal Function
Protocol and TimingTheBLESPItimingdiagramisshownbelow.
SPI_CLK CPOL=0
SPI_MOSI
SPI_MISO
SPI_CS
MSB 6 5 4 3 2 1 LSB
MSB 6 5 4 3 2 1 LSB
BLE SPI Timing Diagram
BLE Command Format and TimingTheBLEregisterscanbeaccessedbyboththehostandcontrollerforgettingorconfiguringthestatusofBLEcontroller.
BLE Register
name
BLE Register Address
Parameter Value Description
Threshold 0x00 Bit[11:6]: BLE TX FIFO threshold Bit[5:0]: BLE RX FIFO threshold
Int_status 0x01
Interrupt status: Bit[4]: BLE RX FIFO not empty Bit[3]: BLE RX FIFO overflow Bit[2]: BLE RX FIFO over threshold Bit[1]: BLE RX FIFO empty Bit[0]: BLE RX FIFO under threshold
Int_Set 0x02
Interrupt Enable: For detail bits definition, refer to Int_status. Set 1 to enable INT
Int_Clr 0x03Interrupt clear, write onlyFor detail definition, refer to Int_status. Set 1 to clear the status bit
FIFOCount 0x04 Bit[11:6]: BLE TX FIFO countBit[5:0]: BLE RX FIFO count
BLE SPI Interface Register Description
BLE CMD FORMATCMD Name Bit[7:5] Bit[4:0]
Read Register 000b Bit[4:1]: BLE Register address,
bit[0] =1Write Register 001b Bit[4:1]: BLE Register address,
bit[0] =1Read FIFO 011b Bit[4:0]=data length, 0 means 32
bytes, 1 means 1 byteWrite FIFO 101b Bit[4:0]=data length, 0 means 32
bytes, 1 means 1 byte
BLE SPI Register and FIFO Operation List
Rev. 1.00 25 October 26, 2017
BC32F7611
D7 D6 D5 D4 D3 D2 D1 D0
SPI_CS
SPI_CLK
SPI_MOSI
D7 D6 D5 D4 D3 D2 D1 D0SPI_MISO D7 D6 D5 D4 D3 D2 D1 D0
Read Reg CMD
Reg value high 8 bits Reg value low 8 bits
Read BLE Register Operation
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0D7
Write Reg CMD Reg value high 8 bits Reg value low 8 bits
SPI_CS
SPI_CLK
SPI_MOSI
SPI_MISO
Write BLE Register Operation
D7 D6 D5 D4 D3 D2 D1 D0
SPI_CS
SPI_CLK
SPI_MOSI
D7 D6 D5 D4 D3 D2 D1 D0SPI_MISO D7 D6 D5 D4 D3 D2 D1 D0
Read FIFO CMD
FIFO data 0 FIFO data N
Read BLE FIFO Operation
SPI_CS
SPI_CLK
SPI_MISO
FIFO data 0 FIFO data ND7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0D7
Write FIFO CMDSPI_MOSI
Write BLE FIFO Operation
Rev. 1.00 26 October 26, 2017
BC32F7611
Sleep and Wake-up TheWAKEUP pin is used for the BC32F7611operationmode setting.When theWAKEUPpinis low, theBLEcanenter the sleepmodeand theBC32F7611 can check the operationmode bymonitoringtheSTATEpin.WhentheBLEcontrollerisinSleepmode,itcanbewokenupbytheinternalBLE_SPIortheWAKEUPpin.
Power-Down Mode ThePDNpinisusedfortheBLEpower-downmodesetting.IfthePDNpinpulledlow,theBLEcontrollerwill enter thepower-downmode and all internalclockswillbedisabled.
External InterruptTheBLEcontrollerprovidesan INT_EXTpin tooutput the interruptsignalof themicrocontroller. IftheINT_EXTpin is low, itmeans thevaliddata isready.
Debug Support• SerialWireDebugPort–SW-DP• 4comparatorsforhardwarebreakpointorcode/literalpatch
• 2comparatorsforhardwarewatchpoints
Rev. 1.00 27 October 26, 2017
BC32F7611
Application Circuits
BC32F761146 QFN-A
Expose Pad
1
2
3
4
5
6
7
8 RFGND
9
1710 11 12 13 14 15 16 2118 19 20 22 23
46 45 44 43 42 41 40 39 38 37 36 35 34 33
31
30
29
28
27
26
25
24
32
0.1uF
32MHz
VDD15
0.1uF
Bead
VDD15
0.1uF
Bead
VDDVDD15
uH2.2
C7
C8
C9
L3
L4
L6
X1
10K
R1
X32KOUT/PB11
VDD
XTALOUT/PB14
VSS
nRST
PB9
X32KIN/PB10
PB12
XTALIN/PB13
RFIO
VDD
RF_15
PB
1
PA
15
PA
14
PA
9_BO
OT
SW
CLK
/PA
12
PB
0
PB
4
VD
DIF_15
RFG
ND
SW
DIO
/PA
13
PB
2
PB
3
VDD
DVDD_12
RFGND
XI
NC
VDDLO_15
DC_TEST
XO
NC
VDDRF_15
DC
DC
_SW
VO
UT_15
WA
KE
UP
PA
2
PA
0
INT_ E
XT
RS
TN
PA
5
PA
3
CLD
O
PA
4
PV
IN
PA
1
VDD
0.1uFC3
0.1uFC2
1uFC14
0.1uF
C10
4.7uFC11
AV
DD
3.3pF
Antenna
2.4pF 4.7nH
C5C4 L1ANT1
VDD15
0.1uF
BeadC6
L2
MCU Peripheral (alternate function)
BeadL5
Bead
L7
4.7uFC1
0.1uFC12
4.7uF
C13
AVDD
Note:Alldecouplingcapacitorsshouldbelocatedasclosetothedevicepinsaspossible.
Rev. 1.00 28 October 26, 2017
BC32F7611
Package Information
Notethat thepackageinformationprovidedhereisforconsultationpurposesonly.Asthis informationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.
Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.
• PackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)
• TheOperationInstructionofPackingMaterials
• Cartoninformation
Rev. 1.00 29 October 26, 2017
BC32F7611
SAW Type 46-pin (6.5mm×4.5mm) QFN Outline Dimensions
SymbolDimensions in inch
Min. Nom. Max.A 0.031 0.033 0.035
A1 0.000 0.001 0.002A3 — 0.008 BSC —b 0.006 0.008 0.010D 0.254 0.256 0.258E 0.175 0.177 0.179e — 0.016 BSC —
D2 0.197 0.201 0.205E2 0.118 0.122 0.126L 0.012 0.016 0.020K — — —
SymbolDimensions in mm
Min. Nom. Max.A 0.800 0.850 0.900
A1 0.000 0.020 0.040A3 — 0.200 BSC —b 0.150 0.200 0.250D 6.450 6.500 6.550E 4.450 4.500 4.550e — 0.40 BSC —
D2 5.00 5.10 5.20E2 3.00 3.10 3.20L 0.30 0.40 0.50K — — —
Rev. 1.00 30 October 26, 2017
BC32F7611
Copyright© 2017 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com/en/.
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