1 Signal and Timing Parameters II Source Synchronous Timing – Class 3 a.k.a. Co-transmitted Clock Timing a.k.a. Clock Forwarding. Assignment for next class:
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1
Signal and Timing Parameters IISource Synchronous Timing – Class 3
a.k.a. Co-transmitted Clock Timing
a.k.a. Clock Forwarding. Assignment for next class: Download HSPICE manual from Intel Lab.
Acknowledgements: Intel Bus Boot Camp: Howard Heck
Signal Parameters & Timing Class 3
2
Contents
Synchronous Bus Limitations Source Synchronous Concept &
Advantages Operation Timing Equations Timing Loop Analysis Maximum Transfer Rate Beyond “Double Pumping” Edge Considerations
Signal Parameters & Timing Class 3
3
Common Clock Limitations
Max frequency is defined by min cycle time Min cycle time is limited by maximum delays. Can we find a way to remove the dependence
on absolute delays?
A BData
Clock
CLK
min,max
1cycleTf
skewsetupflightdrivercycle TTTTT max,max,min,
Signal Parameters & Timing Class 3
4Source Synchronous Signaling Concept
The transmitting agent (A) sends the clock (“strobe”), along with the data signal.
A central clock is not (directly) required to control data flow from transmitter to receiver.
Overview: Drive the strobe and data signals with a known phase relationship.Design the strobe and data signals to be identical in order to preserve the phase relationship.As long as the phase relationship can be maintained, the lines can be arbitrarily long (limited by other effects, such as losses, latencies, etc.).
BData
StrobeA
Signal Parameters & Timing Class 3
5Source Synchronous Concept Example
Suppose that we transmit a data signal 1 ns prior to transmitting the strobe.
You’re given a 500 ps receiver setup requirement.
You find that the flight time for the data signal varies between 5.5 ns and 5.7 ns.
You find that the flight time for the strobe signal also varies between 5.5 ns and 5.7 ns, but the two signals are not correlated.
Can we meet the setup requirement?
Signal Parameters & Timing Class 3
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Source Synchronous Advantage From the preceding example, it should be
apparent that source synchronous performance depends on relative, rather than absolute delays.
True for drivers and interconnect, though we must still meet the absolute setup/hold requirements for the receiver.
In real systems, the difference in delay between signals can be made much smaller than the absolute delays.
Therefore, with source synchronous signaling we can expect
to achieve higher performance to be able to use longer traces
Signal Parameters & Timing Class 3
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Transfer Rate Comparison
SynchronousSource Synchronous
FSB 133 MHz400 MT/s(533 MT/s)
Graphics 66 MHz266 MT/s (533 MT/s)
Memory 133 MHz 800 MT/s
Items in parentheses are in development, all others are released in products.
Signal Parameters & Timing Class 3
8Source Synchronous Bus Operation
PLL
D Q
SystemClock
Driver Chip
Strobe
D Q
Data
From Core
n
From Core
Clock Distribution Tree
n
PLL
Q D
Receiver Chip
Str
ob
e
Q D
Data
Clock Distribution Tree
To Core
DELAY
n
n
Signal Parameters & Timing Class 3
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Operation #2
The transmitted strobe (and data) signals are generated from the on-chip bus clock.
Typically, the strobe is phase shifted by ½ cycle from the data signal. Some buses do the shifting in the receiver.
Duty cycle variations will cause variation on the phase relationship
The timing path starts at the flip-flop of the transmitting agent and ends at the flip-flop of the receiving agent.
The strobe signal is used as the clock input of the receiver flip-flop.
PLL
D Q
SystemClock
Driver Chip
Strobe
D Q
Data
From Core
n
From Core
Clock Distribution Tree
n
PLL
Q D
Receiver Chip
Str
ob
e
Q D
Data
Clock Distribution Tree
To Core
DELAY
n
n
Signal Parameters & Timing Class 3
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Operation #2 Typically, there is
one strobe signal (or pair of signals) per two bytes of data signals. Varies by
design Signal
relationships at the transmitter are shown below.
Setup Hold
CLK
DATA
STROBE
Setup Hold
PLL
D Q
SystemClock
Driver Chip
Strobe
D Q
Data
From Core
n
From Core
Clock Distribution Tree
n
PLL
Q D
Receiver Chip
Str
ob
e
Q D
Data
Clock Distribution Tree
To Core
DELAY
n
n
Signal Parameters & Timing Class 3
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Source Synchronous Operation
TvaTvb
DATA
ThmarTruman
t
@ DRIVER
ThTsu
Tsuskew
STROBE/STROBEThskew
@ RECEIVER
Tsuskew: flight time skew for setup
Tsumar: setup margin
Tvb: min driver phase offset (setup)
Thskew: flight time skew for hold
Thmar: hold margin
Tvb: min driver phase offset (hold)
Signal Parameters & Timing Class 3
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Source Synchronous Equations
The sum of the timings at the receiver must equal the timing at the driver:
This implies that we must design with minimum driver offsets:
sumarsuskewsuvb TTTT hmarhskewhva TTTT
suskewsuvb TTT hskewhva TTT
TvaTvb
DATA
ThmarTruman
@ DRIVER
ThTsu
Tsuskew
STROBE/STROBEThskew
@ RECEIVER
Signal Parameters & Timing Class 3
13Source Synchronous Equations #2
We must also satisfy the following relationship:
This determines our maximum transfer rate.
min,max
1cycleTf
vbvacycle TTT min,
TvaTvb
DATA
ThmarTruman
@ DRIVER
ThTsu
Tsuskew
STROBE/STROBEThskew
@ RECEIVER
Signal Parameters & Timing Class 3
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Question Based on what we’ve covered in the
previous slides, what are the implications to:
The transmitter design?The receiver design?The interconnect design?
Example:Tsu = 500 ps, Th = 250 ps
The target transfer rate is 500 MT/s.What are reasonable flight time skew targets?
Signal Parameters & Timing Class 3
15Setup Timing Diagram & Loop Analysis
Tco(STB)
Tsumar
TBCLK/4
TBCLK
BCLK
STB/STBDRIVER
DATADRIVER
DATARECEIVER
RECEIVER STB/STB
Tflight(DATA) Tsu
Tco(DATA) Tflight(STB)
04 DATATDATATTTSTBTSTBTTflightcosumarsuflightco
BCLK
DCLK
Signal Parameters & Timing Class 3
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Setup Analysis
For a “double pumped” bus, the difference between Tco(DATA) and Tco(STB) is typically set to one-half of the cycle time (TDCLK/2 = TBCLK/4) to center the strobe in the data valid window.
Double pumped: source synchronous transfer rate is 2x the central clock rate.
This relationship is typically specified as Tvb (data “valid before” strobe ), which signifies the minimum time for which the data at the transmitter is valid prior to transmission of the strobe.
Mathematically:
Simplify the loop equation:
04 DATATDATATTTSTBTSTBTTflightcosumarsuflightco
BCLK
4maxmin,BCLK
cocovbTSTBTDATATT
0min, DATATTTSTBTT flightsumarsuflightvb
Signal Parameters & Timing Class 3
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Setup Analysis #2
Both data & strobe propagate over the interconnect.Goal: identical flight times.
In reality, there will be some difference in flight times between data and strobe.
trace length, loading, crosstalk, ISI, etc.
Define flight time skew for the setup condition:
Simplify the loop equation:
sumarflightflightsuvb TDATATSTBTTT min,
sumarsuskewsuvb TTTT min,
Signal Parameters & Timing Class 3
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Notes on the Setup Equation
You may see the timing equation written in other forms.
The way we defined Tvb makes it a negative quantity. Others may define it to be positive.
We defined Tsuskew to be a positive quantity.
sumarsuskewsuvb TTTT min,
Signal Parameters & Timing Class 3
19Hold Timing Diagram & Loop Analysis
DATADRIVER
DCLK
Tflight(STB)
Tco(STB) Tco(DATA)
Th
Thmar
DATARECEIVER
TBCLK/4
BCLK
TBCLK
STB/STBDRIVER
RECEIVER STB/STB Tflight(DATA)
04 STBTSTBTTTDATATDATATTcoflightholdhmarflightco
BCLK
Signal Parameters & Timing Class 3
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Hold Analysis
Just as for the setup case, we need to specify the minimum phase relationship between data and strobe:
In addition, define the flight time skew for the hold case:
In addition, define the flight time skew for the hold case:
Note that the Thskew is defined such that it is a negative quantity, while Tva is defined to be positive.
04 STBTSTBTTTDATATDATATTcoflightholdhmarflightco
BCLK
4minmin,BCLK
cocovaTSTBTDATATT
min
STBTDATATT flightflighthskew
hmarhskewholdva TTTT min,
Signal Parameters & Timing Class 3
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Maximum Transfer Rate
The maximum transfer rate can be determined using the definitions for Tva and Tvb. minmin,4 STBTDATATTT cocovaBCLK
maxmin,4 STBTDATATTT cocovbBCLK
We can calculate the limit of TBCLK (for a double pumped bus) by adding the two equations above.
min,min,min, 4 vavbBCLK TTT
DATA
Tva,min
STB/STB
-Tvb,min
Tcycle,min
Signal Parameters & Timing Class 3
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Higher Transfer Rates (e.g. “Quad Pumped”)
The setup and hold equations remain the same.
What changes are the Tva and Tvb definitions:
BCLK
DATADRIVER
RECEIVER
STB/STBDRIVER
DATARECEIVER
TholdTflight(DATA)
Tco(STB)
Tflight(STB)
Tco(DATA)
Tmargin
DCLK
TBCLK/8
TBCLK
STB/STB
BCLK
DATADRIVER
RECEIVER
STB/STBDRIVER
DATARECEIVER
Tsetup
Tco(STB)
Tflight(STB)Tco(DATA)
Tmargin
DCLK
TBCLK/8
TBCLK
STB/STB
Tflight(DATA)
8maxBCLK
cocovbTSTBTDATATT
8minBCLK
cocovaTSTBTDATATT
Signal Parameters & Timing Class 3
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Part C: Edge Considerations and Real Specs
Signal Parameters & Timing Class 3
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Review Edge Triggered Clocking
D-Latch
Data in (d)
clock (clk)
Data out (Q)
Set up time
Clock to out time or data valid time
Holdtime
Data in (d)
Data out (Q)
clock (clk)
Signal Parameters & Timing Class 3
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First stage is a buffer
Converts to internal digital levels
Its convenient to think of buffer as differential comparator
Finer look at the latch
Threshold
ThresholdData in
Data in
Internal output
time
Buffer delay
Internal output
Signal Parameters & Timing Class 3
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Switching Threshold The transfer function of the
input buffer is linear for only for a very small region on a input signals edge.
We want it to work in the saturation region above and below threshold.
This is so the output is either is high or low and converted to the internal voltage representation of high or low. I.e. binary
The assumption is that the signal edge is sufficiently fast enough to guarantee predictable switching of high to low and visa-versa.
Linear Region
Saturated Region
SI engineers often measure slew rate as a
reported budget parameter
Signal Parameters & Timing Class 3
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Vil and Vih Vil is the voltage
required to switch the output of the input buffer to a low state.
Vih is the voltage required to switch the output of the input buffer to a high state.
Vil
Vih
Data in
Signal Parameters & Timing Class 3
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Relation to timing Transmitter output times are
measured at a threshold level.
This is how the Tco’s are measured.
Max and min values reported in budgets are normally
The maximum of all the design configuration and process variations max values The minimum of all the design configurations and process variations min values.
Transmitter out out into reference load
Input to Receiver
Output Reference Threshold
Vil
VihMin low going edge Flight time Max high going edge Flight time
Min high going edge Flight time Max low going edge Flight time
Signal Parameters & Timing Class 3
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Assignment: Determine Tva and Tvb Give UI (unit interval
= 10 ns)Meaning 20ns period and 10ns bit time with sufficiently fast rise time
The sources are 1 Volt with source resistance of 50 ohms
Data has 5pF tied to it Strobe has 10p tied to
it. The threshold voltage
VOL and VOH are 0.8 v
What are Tva and Tvb
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