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Analyzing Timing A,er you set the 4ming constraints such as clocks, input delays, and output delays, it is a good idea to use the check_4ming command to check for 4ming setup problems and 4ming condi4ons such as incorrectly specified generated clocks and combina4onal feedback loops. The command checks the 4ming a?ributes of the current design and issues warning messages about any unusual condi4ons found. The default report shows the startpoint, endpoint, path group (clock domain), path type (minimum delay, maximum delay, max_rise, min_fall, and so on), the incremental and cumula4ve 4me delay values along the data and clock paths, the data required 4me at the path endpoint, and the 4ming slack for the path.
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Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

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Page 1: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

AnalyzingTimingA,eryousetthe4mingconstraintssuchasclocks,inputdelays,andoutputdelays,itisagoodideatousethecheck_4mingcommandtocheckfor4mingsetupproblemsand4mingcondi4onssuchasincorrectlyspecifiedgeneratedclocksandcombina4onalfeedbackloops.Thecommandchecksthe4minga?ributesofthecurrentdesignandissueswarningmessagesaboutanyunusualcondi4onsfound.

Thedefaultreportshowsthestartpoint,endpoint,pathgroup(clockdomain),pathtype(minimumdelay,maximumdelay,max_rise,min_fall,andsoon),theincrementalandcumula4ve4medelayvaluesalongthedataandclockpaths,thedatarequired4meatthepathendpoint,andthe4mingslackforthepath.

Page 2: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

AnalyzingTiming

Page 3: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

AnalyzingTimingUsingtheGUI,youcangeneratecolor-codeddiagramsshowingtheloca4onsofworst-case4mingcondi4onssuchaspathslack,cellslack,netcapacitance,clocklatency/transi4on,andcrosstalk.

Page 4: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

AnalyzingPowerThereport_powercommandcalculatesandreportspowerforadesign.Thecommandusestheuser-annotatedswitchingac4vitytocalculatethenetswitchingpower,cellinternalpower,andcellleakagepower,anditdisplaysthecalculatedvaluesinapowerreport.

Page 5: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

Repor4ngQualityofResultsYoucangenerateareportonthequalityofresults(QoR)forthedesigninitscurrentstatebyusingthecreate_qor_snapshotcommand(orbychoosingTiming>CreateQoRSnapshotintheGUI).Thiscommandmeasuresandreportsthequalityofthedesignintermsof4ming,designrules,area,power,conges4on,clocktreesynthesis,rou4ng,andsoon.

Page 6: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

Repor4ngQualityofResults

Page 7: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

CellDensityMapTogenerateacelldensitymap,thetooldividesthelayoutintoagridofsquaresmeasuringfivestandard-cellheightsoneachside.Itfindstheareau4liza4onineachgridsquareandthencolor-codeseachsquareaccordingtotheu4liza4onvalue.Italsodisplaysahistogramshowingthenumberofgridsquaresineachoftheu4liza4onvaluebins.

Page 8: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

CellDensityMap

Page 9: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

CellDensityMap

Page 10: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

Conges4onMapsAconges4onmapcanhelpyouvisualizethequalityofplacementwithrespecttotheavoidanceofrou4ngconges4on.

Page 11: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

HierarchyVisualModeThehierarchyvisualmodeisadisplayofthedesignwithcellshighlightedandcolor-codedaccordingtoblockmembershiporlevelsofhierarchy

Page 12: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

Clock-TreeVisualModeTheclocktreevisualmodehighlightstheflylinesandcellsofaclocktreeusingadifferentcolorforeachbufferlevelofthetree.Forexample,Figureshowstheconnec4onsinlevels0,1,and2ofthesys_clkclocktree,withthelevel0inyellow,level1inmagenta,andlevel2inblue.Thisdisplaycanhelpyouvisualizetheextentandapproximateroutelengthsoftheclocktree.

Page 13: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

NetConnec4onsThenetconnec4onsinareavisualmodeletsyouvisualizethenetsenclosedinorcrossingaspecifiedrectangularareaofthedesignandexaminetheproper4esofthosenets.

Page 14: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

NetConnec4onsThenetconnec4onsinareadisplaycapabilityletsyoudeterminethenettopologyinapar4cularregionandobservetheproper4esofthenetsinthatarea.Thisfeatureworkswithbothroutedandunrouteddesigns.Youcananalyzethenetsthatcrossaspecificareaandusetheinforma4ontochangethefloorplanoraddconstraintssuchasblockages.Forexample,excessivelocalnetsmightimplythatu4liza4onchangesareneeded,orexcessiveglobalorpass-throughnetsmightimplythatfloorplanorplacementconstraintchangesareneeded.

Page 15: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

ClockTreeSynthesisDesignPrerequisites•  Thedesignisplacedandop4mized.Usethecheck_legality-verbosecommandtoverifythattheplacementislegal.Runningclocktreesynthesisonadesignthatdoesnothavealegalplacementmightresultinlongrun4mesandreducedQoR.Thees4matedQoRforthedesignshouldmeetyourrequirementsbeforeyoustartclocktreesynthesis.Thisincludesacceptableresultsfor

•  Conges4onIfconges4onissuesarenotresolvedbeforeclocktreesynthesis,theaddi4onofclocktreescanincrease

conges4on.Ifthedesigniscongested,you canrerunplace_optwiththe-conges4onand-efforthighop4ons,buttherun4mecanbelong.

•  Timing•  Maximumcapacitance•  Maximumtransi4on4me

Toensurethattheclocktreecanberouted,verifythattheplacementissuchthattheclocksinksarenotinnarrowchannelsandthattherearenolargeblockagesbetweentheclockrootanditssinks.Ifthesecondi4onsoccur,fixtheplacementbeforerunningclocktreesynthesis.•Thepowerandgroundnetsareprerouted.•High-fanoutnets,suchasscanenables,aresynthesizedwithbuffers.

Page 16: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

ClockTreeSynthesisLibraryPrerequisites•Anycellinthelogiclibrarythatyouwanttouseasaclocktreereference(abufferorinvertercellthatcanbeusedtobuildaclocktree)orforsizingofgatesontheclocknetworkmustbeusablebyclocktreesynthesisandop4miza4on.Bydefault,clocktreesynthesisandop4miza4oncannotusebuffersandinvertersthathavethedont_usea?ributetobuildtheclocktree.•  Thephysicallibraryshouldinclude•  Allclocktreereferences(thebufferandinvertercellsthatcanbeusedtobuildtheclocktrees)•  Rou4nginforma4on,whichincludeslayerinforma4onandnon-defaultrou4ngrules•  TLUPlusmodelsmustexist.

Extrac4onrequiresthesemodelstoes4matethenetresistanceandcapacitance.

Page 17: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

AnalyzingTheClockTreeBeforerunningclocktreesynthesis,analyzeeachclocktreeinyourdesigntodetermineitscharacteris4csanditsrela4onshiptootherclocktreesinthedesign.Foreachclocktree,determine•Whattheclockrootis•Whatthedesiredclocksinksandclocktreeexcep4onsare•Whethertheclocktreecontainspreexis4ngcells,suchasclock-ga4ngcells•Whethertheclocktreeconverges,eitherwithitself(aconvergentclockpath)orwithanotherclocktree(anoverlappingclockpath)•Whethertheclocktreehas4mingrela4onshipswithotherclocktreesinthedesign,suchasinterclockskewrequirements•Whatthelogicaldesignruleconstraints(maximumfanout,maximumtransi4on4me,andmaximumcapacitance)are•Whattherou4ngconstraints(rou4ngrulesandmetallayers)are

Usethisinforma4onwhenyoudefinetheclocktreesandtovalidatethatthetoolhasthecorrectclocktreedefini4ons.

Page 18: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

DefiningTheClockTreeThetoolusestheclocksourcesdefinedbythecreate_clockcommandastheclockrootsandderivesthedefaultsetofclocksinksbytracingthroughallcellsinthetransi4vefanoutoftheclockroots.Youcandesignateeitheraninputportorinternalhierarchicalpinasaclocksource.

Page 19: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

DefiningTheClockRootA?ributeIftheclockrootisaninputport(withoutanI/Opadcell),youmustaccuratelyspecifythedrivingcelloftheinputport.Aweakdrivingcelldoesnotaffectlogicsynthesis,becauselogicsynthesisusesidealclocks.However,duringclocktreesynthesis,aweakdrivingcellcancausethetooltoinsertextrabuffersasthetooltriestomeettheclocktreedesignruleconstraints,suchasmaximumtransi4on4meandmaximumcapacitance.Ifyoudonotspecifyadrivingcell(ordrivestrength),thetoolassumesthattheporthasinfinitedrivestrength.IftheclockrootisaninputportwithanI/Opadcell,youmustaccuratelyspecifytheinputtransi4on4meoftheinputport.

Page 20: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

Implemen4ngClockMeshesClockmeshesarehomogeneousshortedgridsofmetalthataredrivenbymanyclockdrivers.Thepurposeofaclockmeshistoreduceclockskewinbothnominaldesignsanddesignsacrossvaria4onssuchason-chipvaria4on,chip-to-chipvaria4on,andlocalpowerfluctua4ons.Aclockmeshreducesskewvaria4onmainlybyshor4ngtheoutputsofmanyclockdrivers.Figureshowsthestructureofaclockmesh.Thenetworkofdriversfromtheclockporttothemeshdriverinputsiscalledthepremeshtree.Thenetworkofshortedclockdriveroutputsiscalledthemesh.

Page 21: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

Implemen4ngClockMeshesUsingclockmeshesprovidesthefollowingbenefits:•Smallskewvaria4on,especiallyforhigh-performancedesigns•Consistentdesignperformanceacrossvaria4ons•PredicableresultsthroughoutboththedesignstageandECOstagelater•Stabilityresul4ngfrommeshgridsbeingclosetoreceiversUsingclockmesheshasthefollowingdisadvantages:•Morerou4ngresourcesarerequiredtocreateclockmeshes•Higherpowerconsump4onduringtransi4onsontheparalleldriversdrivingthemesh

Page 22: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

H-TreesAnH-treeisafractalstructurebuiltbydrawinganHshape,thenrecursivelydrawingHshapesoneachofthever4ces,asshowninFigure.Withenoughrecursions,theH-treecandistributeaclockfromthecentertowithinanarbitrarilyshortdistanceofeverypointonthechipwhilemaintainingexactlyequalwirelengths.Buffersareaddedasnecessarytoserveasrepeaters.Iftheclockloadswereuniformlydistributedaroundthechip,theH-treewouldhavezerosystema4cskew.Moreover,thetreestendtouselesswireandthushavelowercapacitancethangrids.

Page 23: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

SpinesThespinesdrivelength-matchedserpen4newirestoeachsmallgroupofclockedelements.Iftheloadsareuniform,thespineavoidsthesystema4cskewofthegridbymatchingthelengthoftheclockwires.

Page 24: Analyzing Timing - University of California, Berkeleyee290c/sp17/lectures/Lecture25.pdfAnalyzing The Clock Tree Before running clock tree synthesis, analyze each clock tree in your

Pen4um4ClockSpines

Figure(L)showstheglobalclockbuffersdistribu4ngtheclocktothethreespinesonthePen4um4withzerosystema4cskewwhileFigure(R)showsaphotographofthechipannotatedwiththeclockspineloca4ons.


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