001-96748Owner: ABVY (SKRG, OHP, DCN, GHR, DSG, GMRL, JMY) Synchronous SRAM With On-Chip ECC Quick Presentation Rev **Tech Lead: SKRG 1 High-Performance,
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001-96748 Owner: ABVY (SKRG, OHP, DCN, GHR, DSG, GMRL, JMY) Synchronous SRAM With On-Chip ECC Quick PresentationRev ** Tech Lead: SKRG
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High-Performance, Low-Power Synchronous SRAMsWith On-Chip ECC to Improve Reliability 1,000x
Quick Presentation:
Synchronous SRAM With On-Chip ECC
ECC = Error-Correcting Code
Title
001-96748 Owner: ABVY Synchronous SRAM With On-Chip ECC Quick PresentationRev** Tech Lead: SKRG
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Cypress: No. 1 in Flash, SRAM, NVRAMComparison of Competitors’ Memory Product Portfolios
Product Category Cypress Competitors
Performance Advantage MetricsRenesas ISSI Micron Toshiba Winbond Macronix Fujitsu
No. 1 NOR Flash
HyperFlash™ Highest read bandwidth 333 MBps
Serial NOR Flash Highest read bandwidth Fastest program/erase
160 MBps
Parallel NOR Flash Highest read bandwidth
Fastest program/erase90 MBps
No. 1 SRAM
QDR®-IV Synchronous SRAM
Highest RTR (random transaction rate)
2.1 GT/s
Asynchronous SRAM with ECC1 Highest reliability <0.1 FIT2
MicroPower™ SRAM Lowest standby current 1.5 µA
NAND3 Flash
SLC NAND Flash Fastest access time 25 ns
e.MMC NAND Flash Highest reliability 0 FIT2
No. 1 NVRAM
Serial F-RAM™4 Lowest standby current 100 µA
Parallel nvSRAM5 Fastest NVRAM6 20 ns
AGIGARAM®7 Highest-density NVRAM6 16GB
Cypress has the broadest portfolio of high-performance memories for embedded systems
1 Error-correcting code 2 Failures In Time (billion hours) 3 A type of flash memory that offers extremely high densities, low cost and sequential reads
4 Ferroelectric RAM 5 Nonvolatile SRAM
6 Nonvolatile memory that provides direct access to read and write to any memory location in any random order7 A Cypress brand name
Market Positioning
001-96748 Owner: ABVY Synchronous SRAM With On-Chip ECC Quick PresentationRev** Tech Lead: SKRG
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Standard Syncand NoBL®
Standard Sync and NoBL® with ECC2
QDR® -II/DDR-II
QDR-II+/ DDR-II+
QDR-II+X/ DDR-II+X
QDR-IV
Max RTR1: 250 MT/sMax BW: 18 GbpsLatency: 1 CycleFlow-through and Pipeline Modes
Max RTR1: 250 MT/sMax BW: 18 GbpsLatency: 1 CycleFlow-through andPipeline Modes
Max RTR1: 666 MT/sMax BW: 47.9 GbpsLatency: 1.5 Cycles
CIO3 and SIO4
Max RTR1: 666 MT/sMax BW: 79.2 Gbps
Latency: 2 or 2.5 Cycles
CIO3and SIO4, ODT5
Max RTR1: 900 MT/sMax BW: 91.1 Gbps Latency: 2.5 Cycles
SIO4, ODT5
Max RTR1: 2.1 GT/sMax BW: 153.5 Gbps
Latency: 5 or 8 CyclesDual-Port Bidirectional
ODT5
Synchronous SRAM PortfolioHigh Random Transaction Rate (RTR)1 | Low Latency | High Bandwidth
De
ns
ity
Production Development
QQYYQQYYAvailability
Sampling ConceptStatus
CY7C41xKV13144Mb; 667-1066 MHz
1.3 V; x18, x36Burst 2
CY7C147/8xB 72Mb; 133-250 MHz2.5, 3.3 V; x18, x36
CY7C144/6xA 36Mb; 133-250 MHz2.5, 3.3 V; x36, x72
CY7C137/8xD 18Mb; 100-250 MHz3.3 V; x18, x32, x36
CY7C135/6xC 9Mb; 100-250 MHz3.3 V; x18, x32, x36
Auto E7
CY7C134/2xG2,4Mb; 100-250 MHz3.3 V; x18, x32, x36
36Mb with ECC2
133-250 MHz2.5, 3.3 V; x18, x36
Contact Sales
18Mb with ECC2
100-250 MHz2.5, 3.3 V; x18, x36
Contact Sales
CY7C161/2xKV18144Mb; 250-333 MHz
1.8 V; x9, x18, x36Burst 2, 4
CY7C141/2xKV1836Mb; 250-333 MHz
1.8 V; x8, x9, x18, x36Burst 2, 4
CY7C131/2/9xKV1818Mb; 250-333 MHz1.8 V; x8, x18, x36
Burst 2, 4
CY7C1911xKV1818Mb; 250-333 MHz
1.8 V; x9Burst 2, 4
CY7C151/2xKV1872Mb; 250-333 MHz1.8 V; x9, x18, x36
Burst 2, 4
CY7Cx4/5/6/7xKV18144Mb; 300-550 MHz
1.8 V; x18, x36Burst 2, 4
CY7Cx54/5/6/7KV1872Mb; 250-550 MHz
1.8 V; x18, x36RH6; Burst 2, 4
CY7Cx24/5/6/7xKV1836Mb; 400-550 MHz
1.8 V; x18, x36Burst 2, 4
CY7Cx14/5/6/7xKV1818Mb; 400-550 MHz
1.8 V; x18, x36Burst 2, 4
CY7C156/7xXV1872Mb; 366-633 MHz
1.8 V; x18, x36Burst 2, 4
CY7C126/7x36Mb; 366-633 MHz
1.8 V; x18, x36Burst 2, 4
CY7C40xKV1372Mb; 667-1066 MHz
1.3 V; x18, x36Burst 2
72Mb with ECC2
133-250 MHz2.5, 3.3 V; x18, x36, x72
Contact Sales
Random Transaction Rate
NEW
NEW
NEW
NEW
NEW
Roadmap
001-96748 Owner: ABVY Synchronous SRAM With On-Chip ECC Quick PresentationRev** Tech Lead: SKRG
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Standard Sync SRAM WithOn-Chip ECC
Switches and routersRadar and signal processingTest equipmentMilitary and aerospace systems
Applications
Available in two modes: Flow-Through and Pipeline2
Single-cycle (SCD) and double-cycle (DCD)3 deselect optionsBus-width configurations: x18, x36, x72 (72Mb)Two voltage options: 2.5 V and 3.3 VIndustrial and commercial temperature gradesError-correcting code (ECC) to detect and correct single-bit
errorsPackages: 165 BGA and 100 TQFPIndustry-standard, RoHS4-compliant packages
Features
Preliminary Datasheet: Contact Sales
Collateral
Family Table
Sampling: Q2 2015 (36Mb), Q3 2015 (18Mb), Q1 2016 (72Mb)Production: Q2 2015 (36Mb), Q4 2015 (18Mb), Q2 2016 (72Mb)
Availability
Block Diagram
Option Density MPN RTR FIT/Mb1
Standard Sync withOn-Chip ECC Pipeline
183672
MbMbMb
CY7C1370/2KCY7C1440/2KCY7C1470/2K
250 MT/s <0.01
Standard Sync withOn-Chip ECCFlow-Through
183672
MbMbMb
CY7C1371/3KCY7C1441/3KCY7C1471/3K
133 MT/s <0.01
Data Port x18, x36, x72
x19-x21
Chip Enable
Byte Write
AddressBus
Control
Input Register
Output Register (Pipeline)
Control Logic
SRAM Array
JTAG Interface
x2
Clock
OutputEnable
ECC Encoder
ECC Decoder
1 The projected failure rate of a device; one FIT/Mb equals one failure per billion device hours per megabit of data2 Modes of synchronous SRAM operation that optimize either read latency (Flow-Through) or operating frequency (Pipeline) 3 Modes of operation in Pipeline mode where the output driver is tri-stated after either a single cycle (SCD) or dual cycle (DCD) of issuing the deselect command4 A European Union directive intended to eliminate the use of environmentally hazardous material in electronic components
Product Overview
001-96748 Owner: ABVY Synchronous SRAM With On-Chip ECC Quick PresentationRev** Tech Lead: SKRG
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NoBL® SRAM With On-Chip ECC
Switches and routersRadar and signal processingTest equipmentMilitary and aerospace systems
Applications
Available in two modes: Flow-Through and Pipeline2
No Bus Latency™ (NoBL3) architecture for balanced read and write
Bus-width configurations: x18, x36, x72 (72Mb)Two voltage options: 2.5 V and 3.3 VIndustrial and commercial temperature gradesError-correcting code (ECC) to detect and correct single-bit
errorsPackages: 165 BGA and 100 TQFPIndustry-standard, RoHS4-compliant packages
Features
Preliminary Datasheet: Contact Sales
Collateral
Family Table
Sampling: Q2 2015 (36Mb), Q3 2015 (18Mb), Q1 2016 (72Mb)Production: Q2 2015 (36Mb), Q4 2015 (18Mb), Q2 2016 (72Mb)
Availability
Block Diagram
AddressBus
Input Register
Output Register (Pipeline)
SRAM Array
JTAG Interface
Controlx2
Clock
OutputEnable
ECC Encoder
ECC Decoder
Data Port
Chip Enable
Byte Write
Option Density MPN RTR FIT/Mb1
NoBL® with On-Chip ECC Pipeline
183672
MbMbMb
CY7C1380/2KCY7C1460/2KCY7C1480/2K
250 MT/s <0.01
NoBL® with On-Chip ECC Flow-Through
183672
MbMbMb
CY7C1381/3KCY7C1461/3KCY7C1481/3K
133 MT/s <0.01
1 The projected failure rate of a device; one FIT/Mb equals one failure per billion device hours per megabit of data2 Modes of synchronous SRAM operation that optimize either read latency (Flow-Through) or operating frequency (Pipeline) 3 A Synchronous SRAM that transfers data on the rising edge of the clock signal with zero clock cycle delay between read and write operations4 A European Union directive intended to eliminate the use of environmentally hazardous material in electronic components
x19-x21
x18, x36, x72
Product Overview
NoBLLogic
001-96748 Owner: ABVY Synchronous SRAM With On-Chip ECC Quick PresentationRev** Tech Lead: SKRG
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1. Visit the Cypress Synchronous SRAM with ECC web page to learn more
2. Download the Synchronous SRAM Roadmap, which includes the Synchronous SRAM with ECC Product Overview
3. Contact Sales to request a preliminary datasheet
Here’s How to Get Started
Getting Started
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