This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Serial NOR Flash Highest read bandwidth Fastest program/erase
160 MBps
Parallel NOR Flash Highest read bandwidth
Fastest program/erase90 MBps
No. 1 SRAM
QDR®-IV Synchronous SRAM
Highest RTR (random transaction rate)
2.1 GT/s
Asynchronous SRAM with ECC1 Highest reliability <0.1 FIT2
MicroPower™ SRAM Lowest standby current 1.5 µA
NAND3 Flash
SLC NAND Flash Fastest access time 25 ns
e.MMC NAND Flash Highest reliability 0 FIT2
No. 1 NVRAM
Serial F-RAM™4 Lowest standby current 100 µA
Parallel nvSRAM5 Fastest NVRAM6 20 ns
AGIGARAM®7 Highest-density NVRAM6 16GB
Cypress has the broadest portfolio of high-performance memories for embedded systems
1 Error-correcting code 2 Failures In Time (billion hours) 3 A type of flash memory that offers extremely high densities, low cost and sequential reads
4 Ferroelectric RAM 5 Nonvolatile SRAM
6 Nonvolatile memory that provides direct access to read and write to any memory location in any random order7 A Cypress brand name
Switches and routersRadar and signal processingTest equipmentMilitary and aerospace systems
Applications
Available in two modes: Flow-Through and Pipeline2
Single-cycle (SCD) and double-cycle (DCD)3 deselect optionsBus-width configurations: x18, x36, x72 (72Mb)Two voltage options: 2.5 V and 3.3 VIndustrial and commercial temperature gradesError-correcting code (ECC) to detect and correct single-bit
errorsPackages: 165 BGA and 100 TQFPIndustry-standard, RoHS4-compliant packages
1 The projected failure rate of a device; one FIT/Mb equals one failure per billion device hours per megabit of data2 Modes of synchronous SRAM operation that optimize either read latency (Flow-Through) or operating frequency (Pipeline) 3 Modes of operation in Pipeline mode where the output driver is tri-stated after either a single cycle (SCD) or dual cycle (DCD) of issuing the deselect command4 A European Union directive intended to eliminate the use of environmentally hazardous material in electronic components
Switches and routersRadar and signal processingTest equipmentMilitary and aerospace systems
Applications
Available in two modes: Flow-Through and Pipeline2
No Bus Latency™ (NoBL3) architecture for balanced read and write
Bus-width configurations: x18, x36, x72 (72Mb)Two voltage options: 2.5 V and 3.3 VIndustrial and commercial temperature gradesError-correcting code (ECC) to detect and correct single-bit
errorsPackages: 165 BGA and 100 TQFPIndustry-standard, RoHS4-compliant packages
1 The projected failure rate of a device; one FIT/Mb equals one failure per billion device hours per megabit of data2 Modes of synchronous SRAM operation that optimize either read latency (Flow-Through) or operating frequency (Pipeline) 3 A Synchronous SRAM that transfers data on the rising edge of the clock signal with zero clock cycle delay between read and write operations4 A European Union directive intended to eliminate the use of environmentally hazardous material in electronic components