– 1 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Active Filters.

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– 1 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Active Filters

Introduction

– 2 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Filtering: most common linear time-invariant (LTI) signal processing function – selecting the signal bandwidth of interest (in reality neither linear nor time-invariant)…

Categories: continuous time (CT), discrete time (DT)

analog filter, digital filter

(will focus on CT analog filters for this course)

Frequency domain: low-pass (LP), high-pass (HP), band-pass (BP)…

Time domain: impulse response, FIR, IIR…

Simple RC Filter

– 3 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

o

i

1V 1sCH(s)= s = =

1V 1+sRCR +sC

R

CVi Vo

p 0

1s =-ω =-

RC

Continuous-time, 1st-order, one real pole, low-pass

σ

s-plane

0sp=-ω0

Simple RC Filter

– 4 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

H(t)

t

1/τe-t/τ

0

t-τ

0

1h(t)= e for t≥0,

τ1

τ=RC, ω =RC

|H(jω)|

ω0

1

ω0

-20dB/dec-6dB/oct

ÐH(jω)

-45°

ω0

-90°

ω0

Frequency response Impulse response

General Filter Specs

– 5 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

More realistic:• Magnitude response

ωp, ωs, αp, and αs

• Phase response

Ideal LPF:• Non-causal• Infinite complexity

|H(jω)|

ω0

1

ω0

|H(jω)|

0dB

ω0 ωp

αp - passband ripple (< 1dB)

αs - stopband attenuation

ωs

Transition band

Passband

Stopband

Example: 2nd-order VTF

– 6 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

o2

i

V bH(s)= s =

V s +as+b

• Continuous-time

• Where are the poles? (complex conjugate poles for maximum flatness)

• Low-pass, high-pass, or band-pass?

Passive RLC Filter

– 7 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

R

CVi Vo

L

2

1LCH(s)=R 1

s +s +L LC

• No active component (low power)

• Inductors are bulky and expensive to realize in IC’s

• Values of R, L, and C will not track each other

Active OP-RC Filter

– 8 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• It’s active• Inductor-less• Area efficient• Values of R’s and

C’s and their time co.’s won’t track each other – may lead to RC time constant variations of as high as 20%

• RC time constant enters the VTF in product form – can be tuned for accuracy

1 3 A B

2

4 B 2 3 A B

1R R C C

H(s)=-1 1

s +s +R C R R C C

R1

CA

R

R

R3

R4

CB

R2

Vi Vo

Assuming ideal op amps,

Continuous-Time Integrator

– 9 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

C2

Vi Vo

R1

t

o in1 2 -∞

1v t =- v τ dτ

R C

o

i 1 2

V 1 1H s = s =-

V s R C

Assuming ideal op amp,

– 10 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Cascade Filter Design‒ Biquads

Cascade Filter Design

– 11 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

bq1 bq2 sH s =H s H s H s

σ

s-plane

0

For a real-coefficient H(s):

2nd-order 1st-order

22 1 0

bq2 20

0

K s +K s+KH s =-

ωs + s+ω

Q

Biquad:

The leading minus sign in Hbq(s) is only for convenience

Special Cases of Biquad

– 12 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

2 11) If K =K =0 ⇒ LPF

22 1 0

bq2 20

0

K s +K s+KH s =-

ωs + s+ω

Q

0 12) If K =K =0 ⇒ HPF

0 23) If K =K =0 ⇒ BPF

14) If K =0 ⇒ BSF

Q Factor of Poles

– 13 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

2 20 p p pω =s = σ +ω

σ

s-plane

0σp

jωp

ω0

sp

Δp 0

p p

2

p

p

s ωQ= =

2 σ 2 σ

ω1= 1+

2 σ

Signal Flow Graph (SFG) for Biquad

– 14 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

2o 2 1 0

bq2 20i

0

V K s +K s+KH s = =-

ωV s + s+ωQ

0o 1 2 i o 0 m

0m i 0 o

0

ω1V =- K +K s V + V -ω V

s Q

K1V =- V +ω V

s ω

Note: the partition of the biquadratic VTF is not unique

-1/s -1/sVi Vo1 1 1 1 1

Vm

1 -ω0K0/ω0

ω0/Q

ω0

K1+K2s

1

OP-RC Implementation

– 15 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

ω0/K0

CA=1

-1/ω0

Q/ω0

CB=1

Vm

1/ω0

Vi Vo

1/K1

K2

22 1 0

bq2 20

0

K s +K s+KH s =-

ωs + s+ω

Q

Alternative SFG for Biquad

– 16 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

2o 2 1 0

bq2 20i

0

V K s +K s+KH s = =-

ωV s + s+ωQ

o 2 i 0 m

0 1m i 0 o

0 0

1V =- K sV -ω V

s

K K1 sV =- + s V + ω + V

s ω ω Q

-1/s -1/sVi Vo1 1 1 1 1

Vm

1 -ω0K0/ω0+sK1/ω0

ω0+s/Q

K2s

1

Recast Hbq(s):

Alternative OP-R-C Prototype

– 17 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

22 1 0

bq2 20

0

K s +K s+KH s =-

ωs + s+ω

Q

ω0/K0

CA=1

-1/ω0

CB=1

Vm

1/ω0

Vi Vo

K2

1/Q

K1/ω0

Cascade Filter Design

– 18 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

bq1 bq2 sH s =H s H s H s

σ

s-plane

0

For a real-coefficient H(s):

2nd-order 1st-order

• Order of cascade determines the signal dynamic range

• Optimized using engineering rule of thumb or thru simulation

1st-orderSection

Biquad 1(ω01, Q1)

Biquad 2(ω02, Q2)

Biquad Cascade Filter Design

– 19 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• Most flexible arrangement of cascade filter design

• Allow independent, non-interacting control of (ω0, Q) for

pole pairs

• Easy design

• Components need to be scaled for maximum DR and minimum component spread

• Pass-band sensitivity to capacitance variation is finite

→ Ladder filter can achieve zero sensitivity

– 20 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Scaling of Active Filter

Typical Active Multi-Stage Filters

– 21 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Initial component values may not be optimal...

1st-orderSection

Biquad 1(ω01, Q1)

Biquad 2(ω02, Q2)

Ai

S1i

S2i

Fi

V1

V2

Vi Aj

S1j

Sij

Fj

V1

Vj

Vi

Vin Vout

A2

A1

V1

V2

Freq. Response of Internal Nodes

– 22 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• Internal signal swings need to be large to max SNR

• But not too large such that op amps saturate (producing distortion)

0 ωi ωj

V1

Vi

Vj

Vo,max of op amps

ω

|H(jω)|

DR Scaling of ith Integrator (Vi)

– 23 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• First find out the peak value of Vi(ω), mostly done with simulation

• Then find out the ratio ki = Vi,peak/Vo,max

• Multiply all capacitors connecting at Vi by ki: Fi → Fi*ki, Sij → Sij*ki, …

• Divide all resistors connecting at Vi by ki: Fi → Fi*ki, Sij → Sij*ki, …

• Repeat for all internal nodes…

Ai

S1i

S2i

Fi

V1

V2

Vi AjSik

Sij

Sim

Fj

Vj

Vin Vout

A2

A1

V1

V2

After DR Scaling

– 24 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Max internal signal swings all line up to Vo,max

0 ωi ωj

V1 Vi VjVo,max of op amps

ω

|H(jω)|

Scaling for Min. Component Spread

– 25 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• Find out the smallest cap/res connected to Xi – the summing node of Ai

• determine the optimum scaling factor mi to minimize spread

• Multiply all capacitors connected to Xi by mi: Fi → Fi*mi, Sji → Sji*mi, …

• Divide all resistors connected to Xi by mi: Fi → Fi*mi, Sji → Sji*mi, …• Repeat for all integrators…

Ai

S1i

S2i

Fi

V1

V2

Vi AjSik

Sij

Sim

Fj

Vj

Vin Vout

A2

A1

V1

V2

Xi

Scaling of Active Filter

– 26 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• DR and min spread scaling do not take op-amp loading into

account – lots of work if individual op amps are sized to meet

the settling time constraint

• Upon the completion of scaling, simulation needs to be performed on the resulting filter to find out the overall SNR

• If SNR is lower than the spec, capacitors and op amps need to be scaled up and resistors scaled down to meet the SNR spec (think about how integrated output noise behaves)

– 27 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Ladder Filter Design

Motivation

– 28 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• Cascade filter design– Sensitive to component variations, especially high-Q poles

• Ladder filter design– Achieves zero sensitivity to component variations– Discrete CT LC filters with very high-Q poles are built with ladder

structures over the years

Ladder Filter

– 29 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• Doubly terminated reactance two-port network

• Delivers the optimum power matching in the passband

• ∂|Vout|/∂Zi = 0 for all L’s and C’s → low sensitivity

L2

C1 C3

L4

C5

RS

RLVin

V1 V3 V5

I2 I4

Vout

Reactance two-port

State Space of Ladder Filter

– 30 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Pick –V1, -I2, V3 as

the state variables

for synthesis

L2

C1 C3

RS

RLVin

V1 V3

I2

Vout

in 11 2

1 S

2 1 32

33 2

3 L

V -V1-V =- -I (1)

sC R

1-I =- V -V (2)

sL

V1V =- -I (3)

sC R

Signal Flow Graph (SFG)

– 31 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

-1sC1

1Vin

-1sL2

-1sC3

1/RS 1/RL

-V1 V3

-I21/RS 1

-1 -1

in 11 2

1 S

2 1 32

33 2

3 L

V -V1-V =- -I (1)

sC R

1-I =- V -V (2)

sL

V1V =- -I (3)

sC R

CT OP-RC Ladder Filter

– 32 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

C1RS C3 RLL2

11

-1 -1

RS

-V1 V3

-I2Vin

• Three free state variables → three op amps

• A.k.a the leapfrog ladder structure

Transmission Zeros

– 33 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

z2 2

1ω =

L C10

610

7-80

-70

-60

-50

-40

-30

-20

-10

0

10

Freq

dB

Elliptic LPF

L2

C1 C3

RS

RLVin

V1 V3

I2

Vout

C2

Transmission Zeros

– 34 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

2

2

C 2 3 1 2 3 2 1

C 2 1 3 2 1 2 3

I into node 1 =sC V -V =sC V +sC -V

I into node 3 =sC V -V =sC V +sC -V

L2

C1 C3

RS

RLVin

V1 V3

I2

VoutC2 C2

sC2·V3 sC2·V1

C2

V1 V3

IC2 IC2'

Modified SFG with Derivatives

– 35 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

1

-1sL2

-V1 V3

-I2 1

-1 -1

sC2

sC2

-1s(C1+C2)

-1s(C2+C3)

1/RS 1/RL

Vin1/RS

OP-RC Ladder Filter w/ Derivatives

– 36 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• Derivative input paths implemented with capacitors

C1+C2RS C2+C3 RLL2

11

-1 -1

RS

-V1 V3

-I2Vin

C2

C2

– 37 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Other Active Filters

Tow-Thomas Biquad

– 38 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

[1] P. E. Fleischer and J. Tow, "Design formulas for biquad active filters using three operational amplifiers,“ Proceedings of the IEEE, vol. 61, pp. 662-3, issue 5, 1973.

R4

C1

R7

R8

R2

C2

R3

Vin

R1

R6

R5

Vout

• Low sensitivity• Non-interactive

tuning property

Design Equations for Tow-Thomas

– 39 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

2

2

ms +cs+dH s =

s +as+b

28 8 1 8 8

6 1 1 6 4 7 3 5 7 1 2out

2 8in

1 1 2 3 1 2 7

R R R R R1s + - s+

R R C R R R R R R C CVs =-

R1 1V s + s+R C R R C C R

Note: C1, C2, k1, k2, R8 are free parameters

1

1 2 3 41 1 2 2 12 1

15 6 8 7 2 8

2

k1 1 1 1 1R = ,R = ,R = ,R = ,

aC k k k ma-c CbC bC

k b 1R = ,R = R ,R =k R .

dC m

Sallen-Key LPF

– 40 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• OP-RC active filters are ideally insensitive to bottom-plate stray caps

• Sallen-Key is sensitive to bottom-plate parasitics at node A and B

K

C1

C2

R2R1

Vin Vout

A

B

Design Equations for SK LPF

– 41 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

0

1 1 2 2

0

1 1 2 1 2 2

1ω = ,

R C R C

ωQ = ,

1 1 1-K+ +

R C R C R C

G =K.

20

2 200

G ωH s =

ωs + s+ω

Q

K

C1

C2

R2R1

Vin Vout

A

B

Sallen-Key BPF

– 42 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Still sensitive to parasitic capacitance at node A and B

K

C2R1

Vin Vout

A B

R2

R3C1

Design Equations for SK BPF

– 43 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

1 2

03 1 1 2 2

0

1 1 3 1 3 2 2 1

1 1

1 1 3 1 3 2 2 1

R +Rω = ,

R R C R C

ωQ = ,

1 1 1 1-K+ + +

R C R C R C R C

KR C

G = .1 1 1 1-K

+ + +R C R C R C R C

0

2 200

ωG s

QH s =ω

s + s+ωQ

K

C2R1

Vin Vout

A B

R2

R3C1

– 44 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

MOSFET-C Active Filter

MOSFET Resistor

– 45 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• MOSFET in triode region is a variable resistor

• Compact, low parasitics compared to large-value resistors

IDS

G

0 VDS

VDS=VGS-Vth

DS

VGS

DS

VGS

MOSFET Resistor

– 46 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

But the large-signal response is quite nonlinear

2DS ox GS th DS DS

W 1Intrioderegion, I =μC V -V V - V

L 2

DSox GS th DS

DS DS

ox GS th DS

∂I1 WSmallsignal, = =μC V -V -V

R ∂V L

W=μC V -V for V =0

L

A Linear (Diff.) MOSFET Resistor

– 47 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

MOSFET resistor is linear when driven by balanced differential signals!

2DS ox GS th DS DS

2

ox G th 2 1 2 1 2

2iox G th ic i i

ox G th ic i

W 1Intrioderegion, I =μC V -V V - V

L 2

W 1=μC V -V -V V -V - V -V

L 2

VW 1=μC V -V -V + V - V

L 2 2

W=μC V -V -V V

L

VG

V2V1

i i1 ic 2 ic

V VV =V + , V =V -

2 2

Rudell VGA + Mixer

– 48 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

[2] J. C. Rudell et al., “A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications,” IEEE Journal of Solid-State Circuits, vol. 32, pp. 2071-88, issue 12, 1997.

• M9-M15 comprisethe CMFB circuit

• Gain adjustmentby varying IGain

MOSFET-C Integrator

– 49 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• Sources of M1 and M2 are ideally always equal-potential

• Fully differential circuit rejects the 2nd-order harmonic (and all even-order distortions)

• Triode resistance significantly depends on process (threshold, mobility, etc.), temperature, and VDD → Filter response needs tuning

Vi+

Vo-Vi-

Vo+

VCC

M1

M2 C

Vi+

Vo-Vi-

Vo+

C

C=

– 50 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Frequency Tuning

Master-Slave Tuning

– 51 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• M1-M1' and C-C' are

matched devices• Master sets M1-C time

constant to an off-chipreference thru f/b

• Slave integrator timeconstant follows that ofthe master

• Subject to device mismatch between the master and slave

Active filter (slave)

VC C'

M1'

Tuning circuit (master)

VC

CM1

… …

VC

f/bcontrol

Req Matching

– 52 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

[3] R. Geiger, P. Allen, and N. Dinh, “Switched-resistor filters - A continuous time approach to monolithic MOS filter design,” IEEE Transactions on Circuits and Systems, vol. 29, pp. 306-315, issue 5, 1982.

+V

VC

C

CrФ1

Ф2

Ф2

Ф1

R+V

-VVC

C

R

Rr

i1

i2

i

+V

VC

C

R

-Rr

r r

VΔQ =VC = T ⇒ RC =T

R

Req Matching

– 53 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

VC(t)

0 t

Ф1 Ф1Ф2 Ф2

• Charge from R is continuous but discrete from Cr

• VC(t) should be sampled at the end of Ф2 and held before being applied to the MOSFET gate

• LPF can be used instead of ZOH, but error will be introduced

+V

VC

C

CrФ1

Ф2

Ф2

Ф1

R

r r

VΔQ =VC = T ⇒ RC =T

R

Phase Locking

– 54 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

[4] K. R. Rao, et al., “A novel ‘follow the master’ filter,” Proceedings of the IEEE, vol. 65, pp. 1725-6, issue 12, 1977.

[5] R. Geiger, P. Allen, and N. Dinh, “Switched-resistor filters - A continuous time approach to monolithic MOS filter design,” IEEE Transactions on Circuits and Systems, vol. 29, pp. 306-315, issue 5, 1982.

fref

Phaseshift

PD

C

VC

V1

V2

Vp

R

Phase Locking

– 55 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• Phase detector converts the phase difference b/t V1 and V2 into a pulse with bipolar average <Vp>

• The trailing integrator keeps integrating when <Vp> ≠ 0 holds

Vp

V1

V2

Vo1

Vo2

PDt

V1,V2

t

Vo1,Vo2

t<Vp>

Vp

Δφ

Phase Locking

– 56 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• <Vp> = 0 holds for Δφ = 90º, -90º, … In steady state, V2 leads V1 by 90º

• Negative f/b sets the pole freq. of the HPF formed by C & R to ωref

<Vp>

Δφ90o-90o

180o

0o

270o

2

ref

V jωRC=

V 1+jωRC

Phase

ω

90o

-45o

45o

Δφ=90o

Δφ=45o

Δφ=135o

ÐV2

ÐV1

0o

ref

1⇒ RC =

ω

fref

-45o

PD

C

VC

V1

V2

Vp

R Δφ = 90º

CT Ladder Filter Tuning

– 57 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

• 5th-order Chebyshev-I all-pole continuous-time filter• Integrators are realized by Gm-C active structures

L2

C1 C3

L4

C5

RS

RLVin Vout∫

Vout

∫∫ ∫

Vin

Gm-C Active Integrator

– 58 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Vo

C

iVi

VC IC Cm

i T

IiG = =

V 2V

o m

i

V G 1=-

V C s

• Differential input with programmable gain constant Gm/C

Frequency Locking

– 59 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

[6] K.-S. Tan and P. R. Gray, "Fully integrated analog filters using bipolar-JFET technology," IEEE Journal of Solid-State Circuits, vol. SC13, pp. 814-821, issue 6, 1978.

osc 1 2ω = ω ω

VCO

PD ∫∫

R2

R1

-1fref VC

VC

Active filter (slave)

Vout

∫ ∫

Vin

VCO

– 60 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

1 1 2 11 0 2 1 2

1 2

22 1

ω ω R -RV =- V -V =- V -V

s s R +R

ωV =- V

sω1

R2

R1

-1

ω2

V0 V1 V2

1 2 1 1

1 21 2 2 11 1 2

2 1 22

ω R -R ω1+ -

Vs R +R s R -R=0 ⇒ Δ =s + ω s+ω ω =0

V R +Rω1

s

2

1 2 osc 1 2

1 21 2 1 1 2

1 2

s =ω ω ⇒ ω = ω ω ,

R -Rs +s = ω ≥0 ⇒ R ≥R

R +R

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