Documents Chapter 7

Chapter 7 Designing Sequential Logic Circuits Rev 1.0: 05/11/03 1.1: 5/23/03 Sequential Logic Finite State Machine (FSM) Pipelined System 2 storage mechanisms: Positive feedback…

Documents Latch versus Register

Latch versus Register Latch stores data when clock is low D Clk Q D Clk Q Register stores data when clock rises Clk Clk D D Q Q Latches Latch-Based Design N latch is transparent…