Yu. Bocharov , A. Gumenyuk , A. Klyuev , A. Simakov

11-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 200811-th CBM Collaboration Meeting. GSI Darmstadt Feb. 26-29, 2008 11

A New Data Acquisition System A New Data Acquisition System based onbased on

Asynchronous TechniqueAsynchronous Technique

Yu. Bocharov, A. Gumenyuk, A. Klyuev, A. SimakovYu. Bocharov, A. Gumenyuk, A. Klyuev, A. Simakov


To compare architecturesTo compare architecturesAnalog FIFO per channel vs. Dig.FIFO per ADC Analog FIFO per channel vs. Dig.FIFO per ADC

To estimate a data loss for systems based on To estimate a data loss for systems based on architectures compared by a Monte Carlo architectures compared by a Monte Carlo modelingmodeling

To define the ADC specificationsTo define the ADC specifications

ObjectivesObjectives


A New Readout System ArchitectureA New Readout System Architecture

As an example – 2 ADC As an example – 2 ADC per 128 AFE channelsper 128 AFE channelsOther variants – 1, 4 ADCOther variants – 1, 4 ADC

PD – peak detectorPD – peak detector

Main FeatureMain FeatureDigital FIFO per ADCDigital FIFO per ADC

againstagainstAnalog FIFO per channelAnalog FIFO per channel


Step 1Step 1

When a hit occurs in a channel PD locks the this channel in and sends EVENT signal to the control unit


Step 2Step 2

The control unit writes a channel number and a time stamp into a Dual-port Memory/FIFO. Any type of arbiter may be used to prevent conflicts of writing


Step 3Step 3

The High Speed ADC converts the outputs of channels which numbers are stored in FIFO


Step 4Step 4

Converted data conjunctly with a channel number and a time stamp are transmitted to the external memory bus


Step 5Step 5

When the conversion is finished a control unit initializes PD and corresponding MEM content and connects ADC to the next channel or switches it to a shutdown state if FIFO is empty


Structure of the arbitration logic for analog de-randomizer Structure of the arbitration logic for analog de-randomizer (2007)(2007)


Simulation of the synthesized arbitration logicSimulation of the synthesized arbitration logic


Arbitration logic Area Estimation Arbitration logic Area Estimation (Encounter, Faraday standard cells, UMC 0.18)(Encounter, Faraday standard cells, UMC 0.18)


0,0001

0,001

0,01

0,1

1

10

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

0,00001

0,0001

0,001

0,01

0,1

1

10

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

0,00001

0,0001

0,001

0,01

0,1

1

10

100

1 2 3 4 5 6 7 8 9 10 11 12

Total of hits per cycle Total of hits per cycle probability (%) forprobability (%) for128 (a), 64 (b), 32 (c) 128 (a), 64 (b), 32 (c) channel systemchannel systemat 5% channel occupancy at 5% channel occupancy for Poisson processfor Poisson processMean – 6.4, 3.2, 1.6 Mean – 6.4, 3.2, 1.6

a

b

c


0,01

0,1

1

10

100

0 20 40 60 80 100 120 140 160

1 2

%

MSPS

CBM-XYTER data loss as a function of total ADC-channels throughput CBM-XYTER data loss as a function of total ADC-channels throughput at the best (1) and worse (2) – numerical simulationat the best (1) and worse (2) – numerical simulation


1

( ) , ( 20),!

k

k

kDL e k

k

M

λ – Poisson distribution parameter,M – number of channels per ADC,θ – channel occupancy,μ – max number of channels may be A-D converted within one cycle

Analytical estimation of a data loss for a new readout systemAnalytical estimation of a data loss for a new readout system


0,01

0,1

1

10

20 40 60 80 100 120 140 160

1 2 3

%

MSPS

Data loss of a new readout system as function of ADC throughputData loss of a new readout system as function of ADC throughput @ 32 (1), 64(2), 128(3) channels per ADC – analytical and numerical @ 32 (1), 64(2), 128(3) channels per ADC – analytical and numerical


Figure of merit (FOM) commonly usedFigure of merit (FOM) commonly used for ADC characterization for ADC characterization

2d

ADC ENOBs

PFOM

f

PPdd – power dissipation– power dissipation

ENOB – effective number of bitsENOB – effective number of bits

ffss – sampling frequency (ENOB spec) – sampling frequency (ENOB spec)


SummarySummary

CBM-XYTERCBM-XYTER120 MSPS, 128 mW, FOM < 10.7 pJ - 1 AD/chip120 MSPS, 128 mW, FOM < 10.7 pJ - 1 AD/chip60 MSPS, 64 mW, FOM < 10.7 pJ - 2 AD/chip60 MSPS, 64 mW, FOM < 10.7 pJ - 2 AD/chip30 MSPS, 32 mW, FOM < 10.7 pJ - 4 AD/chip30 MSPS, 32 mW, FOM < 10.7 pJ - 4 AD/chipAdvantage – reduced ADC requirements Advantage – reduced ADC requirements

New architectureNew architecture160 MSPS, 128 mW, FOM < 8.0 pJ - 1 AD/chip160 MSPS, 128 mW, FOM < 8.0 pJ - 1 AD/chip105 MSPS, 64 mW, FOM < 6.1 pJ - 2 AD/chip105 MSPS, 64 mW, FOM < 6.1 pJ - 2 AD/chip75 MSPS, 32 mW, FOM < 4.3 pJ - 4 AD/chip75 MSPS, 32 mW, FOM < 4.3 pJ - 4 AD/chipAdvantage – elimination of 512 analog MEM cellsAdvantage – elimination of 512 analog MEM cells

ADC specs @ Pd = 1 mW/channel andADC specs @ Pd = 1 mW/channel andENOB = 6.6 bit (100 quantization levels)ENOB = 6.6 bit (100 quantization levels)Max data loss level = 0.01% Max data loss level = 0.01%

Yu. Bocharov , A. Gumenyuk , A. Klyuev , A. Simakov

Documents

gsi darmstadt

channel pd

channel number

channel occupancy

c channel system

architectures analog

high speed adc

control unit