1 Course Webpage 1 Penn ESE 570 Fall 2021 - Khanna https://www.seas.upenn.edu/~ese570 / 1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 1: September 1, 2021 Introduction and Overview Penn ESE 570 Fall 2021 - Khanna 2 Your First Priority ! Your first priority is your health " You should abide by all health guidelines " Wear a mask " Wash your hands " Don’t touch your face " Maintain social physical distancing " Careful and thoughtful social interaction is encouraged! " Stay home if you’re sick " Part of your health is your mental and emotional health " See https://caps.wellness.upenn.edu/selfhelp/ for help " For more: https://coronavirus.upenn.edu/ Penn ESE 570 Fall 2021 - Khanna 3 3 I want to hear from you… ! Accessibility Survey in Canvas " Submit by Saturday for full HW credit ! Will you be in a different time zone? ! Will you have trouble seeing or hearing video lectures? ! Are there any other accessibility issues I should know about? ! Let me know any concerns -- I will do everything I can to ensure you achieve the learning objectives Penn ESE 570 Fall 2021 - Khanna 4 4 Where I come from ! Analog VLSI Circuit Design (analog design) ! Convex Optimization (system design) " System Hierarchical Optimization ! Biomedical Electronics ! Biometric Data Acquisition (signal processing) " Compressive Sampling ! ADC Design (mixed signal) ! Low Energy Circuits (digital design) " Adiabatic Charging 5 Penn ESE 570 Fall 2021 – Khanna 5 Where I come from ! Analog VLSI Circuit Design (analog design) ! Convex Optimization (system design) " System Hierarchical Optimization ! Biomedical Electronics ! Biometric Data Acquisition (signal processing) " Compressive Sampling ! ADC Design (mixed signal) ! Low Energy Circuits (digital design) " Adiabatic Charging CIRCUITS, CIRCUITS, CIRCUITS 6 Penn ESE 570 Fall 2021 – Khanna 6
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1
Course Webpage
1Penn ESE 570 Fall 2021 - Khanna
https://www.seas.upenn.edu/~ese570/
1
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
Lec 1: September 1, 2021Introduction and Overview
Penn ESE 570 Fall 2021 - Khanna
2
Your First Priority
! Your first priority is your health" You should abide by all health guidelines
" Wear a mask" Wash your hands
" Don’t touch your face" Maintain social physical distancing
" Careful and thoughtful social interaction is encouraged!" Stay home if you’re sick
" Part of your health is your mental and emotional health" See https://caps.wellness.upenn.edu/selfhelp/ for help
" For more: https://coronavirus.upenn.edu/
Penn ESE 570 Fall 2021 - Khanna 3
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I want to hear from you…
! Accessibility Survey in Canvas" Submit by Saturday for full HW credit
! Will you be in a different time zone?! Will you have trouble seeing or hearing video
lectures?! Are there any other accessibility issues I should
know about?
! Let me know any concerns -- I will do everything I can to ensure you achieve the learning objectives
! Course Topics Overview! Learning Objectives! Course Structure! Course Policies! Course Content! Industry Trends ! Design Example
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VLSI Design
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300 mm (12 in.)
Oracle SPARC M7 Processor
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Course Topics Overview
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Design
Implementation/Fabrication
Course Progression
Course Topics
CMOS Fabrication
MOS Transistor, Capacitor and Interconnect Models
Two Transistor Logic Circuits (Inverters)Static Dynamic
Logic Circuits, Gates, Latches
Regular StructuresROMs, RAMs, PLAs
μPs, Custom LogicVLSI Sub-systems
System-Related IssuesReliability
ManufacturabilityTestability
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Learning Objectives
! Apply principles of hierarchical digital CMOS VLSI, from the transistor up to the system level, to the understanding of CMOS circuits and systems that are suitable for CMOS fabrication.
! Apply the models for state-of-the-art(ish) VLSI components, fabrication steps, hierarchical design flow and semiconductor business economics to judge the manufacturability of a design and estimate its manufacturing costs.
! Design digital circuits that are manufacturable in CMOS.! Design simulated experiments using Cadence to verify the integrity of a
CMOS circuit and its layout.! Apply the Cadence VLSI CAD tool suite layout digital circuits for CMOS
fabrication and verify said circuits with layout parasitic elements.! Apply course knowledge and the Cadence VLSI CAD tools in a team based
capstone design project that involves much the same design flow they would encounter in a semiconductor design industrial setting. Capstone project is presented in a formal report due at the end of the semester.
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Learning Objectives
! In other words…
!Design in CADENCE*
*All the way to layout/manufacturability
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What is Cadence?
! Industry standard CAD software for IC design! Schematic capture
! “After 2021, the report forecasts, it will no longer be economically desirable for companies to continue traditional transistor miniaturization in microprocessors.”
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BUT…
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BUT…
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More than Moore # Functional Diversification
! Interacting with the outside world" Electromagnetic/Optical
" Radio-frequency domain up to the THz range" Optical domain from the infrared to the near ultraviolet
! Gate Level Schematic of One-Bit Full Adder Circuit
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VLSI Design Cycle or Flow
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Verilog/SPICE
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Design Specifications:
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Illustrative Circuit Design Example: System Requirements
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1. Propagation Delay Times of SUM and CARRY_Out signals: ≤ 1.2 ns2. Rise and Fall Times of SUM and CARRY_Out signals: ≤ 1.2 ns3. Circuit Die Area: ≤ 1500 um2
4. Dynamic Power Dissipation (@ VDD = 5 V and f max = 20 MHz): ≤ 1 mW
Penn ESE 570 Fall 2021 - Khanna
Functional Specification:
Design Specifications (in 0.8 twin-well CMOS):
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Illustrative Circuit Design Example: VLSI Design
! Transistor Level Schematic of One-Bit Full Adder Circuit
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N1 N2
N1 N2
SUMOUTCOUT
COUT
Penn ESE 570 Fall 2021 - Khanna
Illustrative Circuit Design Example: VLSI Design and Layout
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! Initial Layout of One-Bit Full Adder Circuit
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COUT
Dynamic Power Dissipation (@ VDD = 5V, f max = 20 MHz): = 0.7 mW ≤ 1 mW
≤ 1500 um2
Illustrative Circuit Design Example: VLSI Design and Layout