XLVDSPro Demonstration Boards - Xilinx€¦ · 08/25/03 1.1 Modified J1 through J8 connector names in Figure 1-1, Figure 1-3, Figure 1-4, and Figure 1-5. 09/18/03 1.2 Added new figure,

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XLVDSPro Demonstration Boards

Virtex-II Pro FPGA Family

UG037 (v1.4) June 03, 2004

Product Not Recommended for New Designs

XLVDSPro Demonstration Boards User Guide www.xilinx.com UG037 (v1.4) June 03, 20041-800-255-7778

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The shadow X shown above is a trademark of Xilinx, Inc.

ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, Rocket I/O, SelectI/O, SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACT-Floorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker, XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc.

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All other trademarks are the property of their respective owners.

Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.

Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited.

The contents of this manual are owned and copyrighted by Xilinx. Copyright 1994-2004 Xilinx, Inc. All Rights Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

XLVDSPro Demonstration Boards User Guide UG037 (v1.4) June 03, 2004The following table shows the revision history for this document..

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Date Version Revision

08/01/03 1.0 Initial Xilinx release.

08/25/03 1.1 Modified J1 through J8 connector names in Figure 1-1, Figure 1-3, Figure 1-4, and Figure 1-5.

09/18/03 1.2 Added new figure, Figure 1-2, with mechanical dimensions of LVDS Connector PCB.

10/27/03 1.3Expanded the information shown in the following figures: Figure 1-6, Figure 4-2, Figure 4-3, Figure 4-4, Figure 7-1, Figure 7-2, and Figure 10-1. Added introductory text for Figure 12-4.

06/03/04 1.4Added lists of commercial and free tools to “Some Types of Transmission Lines”. Removed reference to impedance calculator.


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XLVDSPro Demonstration Boards User Guide www.xilinx.com 3UG037 (v1.4) June 03, 2004 1-800-255-7778

Manual Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Part I: Virtex-II Pro XlvdsPro_Fpga Board

Chapter 1: XlvdsPro_Fpga BoardOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17FPGA Board Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18LVDS Loop and Connector Board Schematic Description

(Page 1 of 8 (10)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24LVDS Loop and Connector Board Schematic Description

(Pages 2 and 3 of 8 (10)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27LVDS Loop and Connector Schematic Description (Page 4 of 8 (10)) . . . . . . . . . . . . . 29LVDS Loop and Connector Board Schematic Description

(Pages 5 and 6 of 8 (10)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31LVDS Loop Board Schematic Description (Pages 7 and 8 of 8) . . . . . . . . . . . . . . . . . . 40LVDS Connector Board Schematic Description (Page 7 of 10) . . . . . . . . . . . . . . . . . . . 43LVDS Connector Board Schematic Description (Page 8 of 10) . . . . . . . . . . . . . . . . . . . 43LVDS Connector Board Schematic Description (Page 9 of 10) . . . . . . . . . . . . . . . . . . . 43LVDS Connector Board Schematic Description (Page 10 of 10) . . . . . . . . . . . . . . . . . . 44PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Web References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45UCF Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Chapter 2: PCB Layout GuidelinesGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Square Waves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Why Discuss Transmission Line Theory for a PCB? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50The Ideal Transmission Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Input or Characteristic Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Some Types of Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Signal Return Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Trace Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56PCB Layer Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

PCB Guidelines Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Useful Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table of Contents



4 www.xilinx.com XLVDSPro Demonstration Boards User Guide1-800-255-7778 UG037 (v1.4) June 03, 2004

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Chapter 3: Clock InterfacesGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Clock Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Peripheral Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Design Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Web References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76UCF Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Part II: Virtex-II Pro XlvdsPro_PwrIo Board

Chapter 4: XlvdsPro_PwrIo BoardGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81XlvdsPro_PwrIo Board Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Hardware Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90UCF Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Chapter 5: LED Matrix DisplayGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Display Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Web Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98UCF Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Chapter 6: Ethernet InterfaceGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Ethernet Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Peripheral Device LXT972A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Web Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105UCF Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Chapter 7: JTAG InterfaceGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107JTAG Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111UCF Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112




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Chapter 8: Keypad and ButtonsGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Push-Button Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Keypad Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Web Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119UCF Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Chapter 9: LCD InterfaceGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Display Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Peripheral Device KS0713 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Operation Example of the 64128EFCBC-3LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Read/Write Characteristics (6800 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143UCF Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Chapter 10: Oscillator InterfaceGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145Oscillator Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Peripheral Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Web Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Chapter 11: PS/2 InterfaceGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149PS/2 Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Peripheral Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157Web Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160UCF Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Chapter 12: Power SupplyGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Power Supply Hardware Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162Core Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733F3 Material Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174Web Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175




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Chapter 13: RS232 InterfaceGeneral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177UART Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178Peripheral Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184Web Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185UCF Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185




Figure 1-1: Mechanical Dimensions of LVDS Loop PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 1-2: Mechanical Dimensions of LVDS Connector PCB . . . . . . . . . . . . . . . . . . . . . . 20Figure 1-3: LVDS Loop Board (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 1-4: LVDS Connector Board (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 1-5: Connector Placement (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 1-6: JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 1-7: Temperature Measurement Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 1-8: Differential Crosstalk and Rise Time Parameters . . . . . . . . . . . . . . . . . . . . . . . 27Figure 1-9: Single-Ended Crosstalk and Rise Time Parameters . . . . . . . . . . . . . . . . . . . . . 28

Figure 1-10: Samtec QSE-014-01-L-DP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 1-11: Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 1-12: MGT VCCAUX Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 1-13: MGT VT Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 1-14: Voltage-Follower Op-Amp Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 1-15: PCB Layer Stackup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 1-16: Top Silk Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Figure 1-17: Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 1-18: Third Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 1-19: Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 1-20: Bottom Silk Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Figure 1-21: Transmission Line Calculator (Microstrip Tab). . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 1-23: Transmission Line Calculator (Stripline Tab) . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 1-22: Si6000-Controlled Impedance Quick Solver (Surface Microchip) . . . . . . . . 41

Figure 1-24: Si6000-Controlled Impedance Quick Solver (Edge-Coupled Surface Microstrip) 42Figure 1-25: Transmission Line Calculator (Microstrip Tab), Differential Impedance . 42

Figure 1-26: Power Connectors J5 (J6) and J7 (J8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Figure 1-27: Banking Connector J1 (J2) Connects to J32 of the PowerIO Board. . . . . . . . 46

Figure 1-28: Banking Connector J3 (J4) Connects to J16 of the PowerIO Board. . . . . . . . 47Figure 2-1: Simple Electrical Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 2-2: Ideal Transmission Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Figure 2-3: Simplified Transmission Line Model (Lossless) . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 2-4: Microstrip Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 2-5: Strip Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 2-6: Design without FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Figure 2-7: Design with FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 2-8: PCB Layer Stackup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Figure 3-1: Clock Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 3-2: Clock Board Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Figure 3-3: Single-Ended Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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Figure 3-4: SAW Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Figure 3-5: VCO/VCXO Oscillator (Example 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 3-6: VCO/VCXO Oscillator (Example 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Figure 3-7: ICS Clock Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 3-8: Serial Configuration Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Figure 3-9: External Differential Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 3-10: External Single-Ended Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Figure 4-1: Power Board Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 4-2: Device Placement (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Figure 4-3: Device Placement (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 4-4: Jumper, Switch, and LED Schematic Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Figure 4-5: PCB Layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 4-6: Additional High-Speed Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Figure 4-7: Keypad Interface Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 4-8: Power Connectors J17 and J34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Figure 4-9: Banking Connector J32 Connects to J1 (J2) of the FPGA Board . . . . . . . . . . . 91

Figure 4-10: Banking Connector J16 Connects to J3 (J4) of the FPGA Board . . . . . . . . . . 92Figure 5-1: LED Schematic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 5-2: Complete Character Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Figure 5-3: Basic Character Matrix Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 5-4: Matrix LED Display Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Figure 5-5: Matrix LED Connections (Bank 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 6-1: Ethernet Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Figure 6-2: LXT972A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 6-3: “FastJack” Connector Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Figure 6-4: Ethernet Connections (Bank 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 7-1: JTAG Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Figure 7-2: JTAG Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 7-3: JTAG Connector Configuration (Banks 1 and 4) . . . . . . . . . . . . . . . . . . . . . . . 111Figure 8-1: Keypad Dimensions (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 8-2: Keypad Dimensions (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Figure 8-3: Keypad Schematic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 8-4: Debouncing Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Figure 8-5: Keypad Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 8-6: Button and Keypad Connections (Bank 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Figure 9-1: Display Schematic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 9-2: KS0713 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Figure 9-3: 64128EFCBC-XLP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 9-4: 64128EFCBC-XLP Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124Figure 9-5: Power Supply Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 9-6: LCD Controller Initialization Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Figure 9-7: Read/Write Timing Waveforms (6800 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 9-8: General Block Diagram of Panel in Full Graphics Mode . . . . . . . . . . . . . . . 139




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Figure 9-9: ASCII Character Representations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140Figure 9-10: Block SelectRAM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 9-11: LCD Character Generator Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142Figure 9-12: LCD Connections (Bank 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 10-1: Oscillation Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Figure 10-2: Clock Connections (Bank 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 11-1: PS/2 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Figure 11-2: Female and Male Mini-DIN 6-Pin Connectors . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 11-3: Typical Data and Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152Figure 11-4: PS/2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 11-5: Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Figure 11-6: Sample Transmission (Combined) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 11-7: Sample Transmission (Host and Device Waveform Separation) . . . . . . . . 156Figure 11-8: PS/2 Connections (Bank 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 12-1: Power Supply Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162Figure 12-2: Supply Test Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 12-3: Molex Receptacle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Figure 12-4: Molex Header (6-Position Style Header) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 12-5: Ferrite Core Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173Figure 12-6: Sheet Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 13-1: UART Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178Figure 13-2: SP3243EH Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 13-3: Handshake Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181Figure 13-4: RS232 DB9 PC Loopback Test Plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 13-5: PC Interconnection without Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . 182Figure 13-6: PC Interconnection with Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 13-7: RS232 Communications using a Monitoring PC . . . . . . . . . . . . . . . . . . . . . . 183Figure 13-8: UART Connections (Bank 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185




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Table 1-1: Location of the FPGA Clock Inputs and the MGTs . . . . . . . . . . . . . . . . . . . . . . 31

Table 1-2: Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Table 1-3: Op Amp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 3-1: FPGA Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 3-2: ICS and MICREL Synthesizer Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 3-3: M[8:0] Frequency Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Table 3-4: Test Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 8-1: Keypad Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Table 9-1: Display Controller Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 9-2: LCD Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125Table 9-3: KS0713 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 9-4: Display Controller Initialization (RESETB is Low) . . . . . . . . . . . . . . . . . . . . . 132Table 9-5: Resistor Value Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 9-6: Reference Voltage Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Table 9-7: Display Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 9-8: Read/Write Characteristics in 6800 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Table 10-1: Low-Jitter Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 11-1: PS/2 Mini-DIN Connector Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151Table 11-2: PS/2 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 11-3: Set 2 Make and Break Code Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157Table 11-4: Mouse Movement Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 12-1: Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165Table 13-1: SP3223EH Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 13-2: SP3243EH Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180Table 13-3: RS232 Pin Assignments (DB9 PC Signal Set) . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Schedule of Tables




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Preface

About This Manual

This manual is separated into two parts. The first part describes the XlvdsPro_Fpga board, and the second part describes the XlvdsPro_PwrIo board. Plugging the XlvdsPro_Fpga board into the XlvdsPro_PwrIo board provides a vehicle for testing the LVDS capabilities of the Virtex™-II FPGA family of devices.

Manual ContentsThis manual contains the following parts and chapters:

• “Part I: Virtex-II Pro XlvdsPro_Fpga Board”♦ Chapter 1, “XlvdsPro_Fpga Board”

♦ Chapter 2, “PCB Layout Guidelines”

♦ Chapter 3, “Clock Interfaces”

• “Part II: Virtex-II Pro XlvdsPro_PwrIo Board”

♦ Chapter 4, “XlvdsPro_PwrIo Board”

♦ Chapter 5, “LED Matrix Display”

♦ Chapter 6, “Ethernet Interface”

♦ Chapter 7, “JTAG Interface”

♦ Chapter 8, “Keypad and Buttons”

♦ Chapter 9, “LCD Interface”

♦ Chapter 10, “Oscillator Interface”

♦ Chapter 11, “PS/2 Interface”

♦ Chapter 12, “Power Supply”

♦ Chapter 13, “RS232 Interface”




Preface: About This ManualR

Additional ResourcesFor additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this web site. You can also directly access these resources using the provided URLs.

Resource Description/URL

Tutorials Tutorials covering Xilinx design flows, from design entry to verification and debugging

http://support.xilinx.com/support/techsup/tutorials/index.htm

Answer Browser Database of Xilinx solution records

http://support.xilinx.com/xlnx/xil_ans_browser.jsp

Application Notes Descriptions of device-specific design techniques and approaches

http://support.xilinx.com/apps/appsweb.htm

Data Book Pages from The Programmable Logic Data Book, which contains device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging

http://support.xilinx.com/partinfo/databook.htm

Problem Solvers Interactive tools that allow you to troubleshoot your design issues

http://support.xilinx.com/support/troubleshoot/psolvers.htm

Tech Tips Latest news, design tips, and patch information for the Xilinx design environment

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Part I: Virtex-II Pro XlvdsPro_Fpga Board

This section describes the Virtex-II Pro XlvdsPro_Fpga board, its components, and its clock interfaces. This section also provides guidelines for PCB design. The XlvdsPro_Fpga board demonstrates the low-voltage differential signaling (LVDS) capabilities and Multi-Gigabit Transceiver (MGT) capabilities of Virtex-II Pro devices. This board, which contains FPGA circuitry and connectors, plugs directly into the XlvdsPro_PwrIo board, which is described in Part II.




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Chapter 1

XlvdsPro_Fpga Board

OverviewThe XlvdsPro_Fpga board demonstrates the low-voltage differential signaling (LVDS) capabilities of Virtex™-II Pro devices. Two board types exist:

• LVDS channels are looped on board from one side to the other side of the FPGA• LVDS channels are at TX- and RX-side routed to QSE connectors

The specifications for the XlvdsPro_Fpga board are summarized below:

• Compatible with three Xilinx FPGAs: XC2VP7, XC2VP20, or XC2VP30 in an FF896 BGA package

The XC2VP7 has no spare I/O left for extra peripherals, while both the XC2VP20 and XC2VP30 have I/O left for extra peripherals through the array connectors

• Four clock-source connectors with low-jitter LVDS clock signals routed to the XC2VPxx FPGA

• Two Tektronix P6880 probes for LVDS eye-pattern measurements• A precision, low-noise power supply for 2 x 4 MGT high-speed balanced serial links

• A precision, low-noise, adjustable VT-TX and VT-RX for 2 x 4 MGTs

• Four MGTs with MMCX 6 GHz RF connectors• Four MGTs with an on-board loop

• Balanced external oscillator input via two SMA RF connectors

• FPGA mode DIP switch• Circuitry for core-temperature measurement

• LVDS loop board

♦ 64-bit LVDS

Loop with clock and sync signals

♦ One balanced LVDS test output at two SMA RF connectors

• LVDS connector board

♦ 64-bit LVDS

Clock and sync signals taken to a set of connectors

♦ Two balanced LVDS test outputs at two SMA RF connectors

♦ Four differential test traces

All peripherals are available when the FPGA board is plugged onto the XlvdsPro_PwrIo board. Four other I/O banks are routed as an LVDS "highway" or to QSE connectors on the FPGA board.




Chapter 1: XlvdsPro_Fpga BoardR

FPGA Board Hardware DesignThe XlvdsPro_Fpga board section of this user guide outlines the different options and modules of the board, referencing the schematic diagrams detailed in the following sections. Six schematics are identical for both boards (1 through 6):

• Schematic 1 (page 24): FPGA power connections and configuration• Schematic 2 (page 27): Array connector bank 0 and bank 1 and power connector 1

• Schematic 3 (page 27): Array connector bank 4 and bank 5 and power connector 2

• Schematic 4 (page 29): FPGA I/O banks 0, 1, 4, and 5• Schematic 5 (page 31): MGT circuitry MGT 1 to 4

• Schematic 6 (page 31): MGT circuitry MGT 5 to 8

Two additional loop board schematics are listed:

• Schematic 7 (page 40): LVDS data loop Bank 2 to Bank 7

• Schematic 8 (page 40): LVDS data loop Bank 3 to Bank 6

Four additional connector board schematics are listed:

• Schematic 7 (page 43): LVDS receiver, 32-bit clock/synchronous and a 6-bit spare• Schematic 8 (page 43): LVDS receiver, 26-bit clock/synchronous and test traces

• Schematic 9 (page 43): LVDS transmitter, 32-bit clock/synchronous and a 6-bit spare

• Schematic 10 (page 44): LVDS transmitter, 26-bit clock/synchronous

There are eight schematics for the LVDS loop board and ten schematics for the LVDS connector board. PDF files of the schematics are available in zipped format.

The XlvdsPro_Fpga board must plug onto an XlvdsPro_PwrIo board. Basically the XlvdsPro_Fpga board only contains the FPGA circuitry and connectors. The XlvdsPro_PwrIo board provides all necessary power supplies and a set of standard peripherals. The power supply concept and peripherals are discussed in detail in Part II of this document.

All FPGA I/Os are routed to two array connectors, and as a set of 68 LVDS channels in a loop or to QSE connectors from one side of the FPGA to the other side (fewer channels are available when using an XC2VP7).

The array connectors are available for extra peripherals. Spare I/Os are available on each connector. When an XlvdsPro_PwrIo peripheral is disconnected through a DIP switch, I/O is available a spare I/O.

Power and I/O array connectors are placed and populated for optimum placement of the different sized mezzanine cards. One mezzanine card design can be used twice on the FPGA board because the connector setup is mirrored.

Hardware Schematic DiagramThis section includes the following information on the FPGA board:

• The mechanical dimensions of the LVDS Loop PCB (Figure 1-1) and the LVDS Connector PCB (Figure 1-2)

• The placement of connectors, solder jumpers, and ICs on the LVDS loop board (top side of the PCB, Figure 1-3)




FPGA Board Hardware DesignR

• The placement of connectors, solder jumpers, and ICs on the LVDS connector board (top side of the PCB, Figure 1-4)

• The placement of connectors (bottom side of the PCB, Figure 1-5)

Figure 1-1: Mechanical Dimensions of LVDS Loop PCB

J3/J4

J7/J8

J1/J2

J5/J6

180.4

90.2 . 90.2

45.145.1

80 5.15.1 80

45.145.1

180.

4

170.

25.

1

ug037_c1_25_082203





Figure 1-2: Mechanical Dimensions of LVDS Connector PCB

50.6

90.2

102.6154.6

180.3

45.145.1

77.9129.9

45.1

25.8

51.440 42

2

1

2

1

2

1

2

1

2

1

1 191

200

2

1 39 41

40 42

39 41

4042

3941

4042

3941

4042

39 10200

1191

41

40 42

39

80

79

80

79

80

79

80

79

80

79

41

45.1

90.280.0

5.1

25.5

170.

2

191

191

291

1010

020

030

0

180.

312

.1

10.9

65.4

25.4

80.05.1

191

191291

10100

200300





Figure 1-3: LVDS Loop Board (Top View)

SamArray10x20

Tektronix Pattern

Sam

Array

10x30Tektronix Pattern

XC2VP7

XC2VP20

FF896

Sam

Arr

ay10

x30

SamArray

10x20

DIP1 DIP2

Osc EnaMode

J7/J8 MGT5 & 6MGT7 & 8

ADJDNA DNA

PSU Noise

1.5V2.5V

XTO3

XTO4

TP5TP11TP10

PWRDWN_B2V5_872V5_65

J3/J4

VT_TX16 - 18VT_RX16 - 18VT_TX19 - 21VT_RX19 - 21

VT_TX4 - 6

VT_TX7 - 9

TP8TP9TP4

2V5_012V5_23HSWAP_EN

J5/J6

J1/J2

DONE

Res

etU

biR

st

Rst

Spa

re

MGT3 & 4MGT1 & 2

ADJDNA DNA

TP3 TP2

TP6 TP7JMP2 JMP1

GAIN NUL

XT01

XT02

VT_RX4 - 6

VT_RX7 - 9

J10

J9

SMA

SMA

UG037_c1_02_082203





Figure 1-4: LVDS Connector Board (Top View)

SamArray10x20

Tektronix Pattern

Sam

Array

10x30Tektronix Pattern

XC2VP7

XC2VP20

FF896

Sam

Arr

ay10

x30

SamArray10x20

DIP1 DIP2

Osc EnaMode

J7/J8 MGT5 & 6MGT7 & 8

ADJDNA DNA

PSU Noise1.5V

2.5V

XTO3

XTO4

TP5TP11TP10

PWRDWN_B2V5_872V5_65

J3/J4

VT_TX16 - 18VT_RX16 - 18VT_TX19 - 21VT_RX19 - 21

VT_TX4 - 6

VT_TX7 - 9

TP8TP9TP4

2V5_012V5_23HSWAP_EN

J5/J6

J1/J2

DONE

Res

etU

biR

st

Rst

Spa

re

MGT3 & 4MGT1 & 2

ADJDNA DNA

TP3 TP2

TP6 TP7JMP2 JMP1

GAIN NUL

XT01

XT02

VT_RX4 - 6

VT_RX7 - 9

J10

J9

SMA

SMA

100 Ω differential stripline

50 Ω

str

iplin

e

Embedded, Asymmetric

50 Ω

Em

bedd

ed s

trip

line

LVDS Balanced Test 100Ω differential stripline

LVDS Front Left LVDS Front Middle LVDS Front Right

LVDS Rear RightLVDS Rear MiddleLVDS Rear Left

UG037_c1_03_082203





Figure 1-5: Connector Placement (Bottom View)

SamArray10x20

Sam

Array

10x30

Sam

Arr

ay10

x30

SamArray

10x20

J7/J8

J3/J4

J5/J6

J1/J2

UG037_c1_04_082203





LVDS Loop and Connector Board Schematic Description (Page 1 of 8 (10))

Configuration and FPGA Power Connections

• All power and ground pins, except those of the Multi-Gigabit Transceivers (MGTs), are listed.

• The configuration mode of the FPGA can be set with the MODE DIP switch. The fourth switch in the DIP switch bank is used as an extra fixed input to the FPGA.

• The configuration part of the connectors J1 (J2) and J3 (J4) are shown. The cable connections are made on the XlvdsPro_PwrIo board. Through these connections the FPGA can be programmed in JTAG, SelectMap, or serial mode.

Only the J3 (J4) connector has all the configuration capabilities routed. The J1 (J2) connector has only a feed through for JTAG programming. Figure 1-6 shows the JTAG chain setup.

• Connections for serial and SelectMap configuration are routed as a signal bus to the schematic on sheet four (4 of 8 (10)).

• A second connector for the XlvdsPro_PwrIo board is placed as shown in Figure 1-6.

• The HSWAP_EN, PWRDWN, VBATT, DXP, and DXN pins all end at a test point. VBATT also connects through the array-power connector to a battery backup located on the XlvdsPro_PwrIo board. Dedicated pins DXP and DXN include a small feature for

Figure 1-6: JTAG Chain





temperature measurement. Solder jumpers must be placed to use the temperature measurement function.

This small circuit gives a linear output voltage depending on the measured temperature of the die.

The two FPGA temperature output sensor pins (DXP, DXN) are used as the source of a small op-amp design shown in Figure 1-7.

• Circuit calculations

The first op amp, OP1, is used a voltage follower. Using the voltage follower corrects possible errors and adjustments (resulting in heavy calculations and use of precision resistors) by providing a stable 2.495V for the FPGA temperature sense diode and second op-amp circuit.

Because characteristics of the FPGA temperature sensing diodes are not given, this design assumes the characteristics of a commercially available diode sensor:

♦ Low Temperature = 700mV Output

♦ High Temperature = 350mV Output

Use a required forward current of 2 mA.

The resistor needed to get 2 mA in the diode is calculated as follows:

The design uses the combined resistor values of 1 KΩ and 220 Ω .

The second op amp, OP2, is set as differential input amplifier with a 5V output at the highest temperature and a 0V output at the lowest temperature.

The transfer function of a linear op amp is limited to the equation of a straight line:

Solving the equation for Y with the following parameters:

Figure 1-7: Temperature Measurement Circuit

_+_

+••

• •

• •

• • • • •

• •

• •

•

••

• • •

DXPDXN

TP11TP6

• • JMP1

JMP2

LM431ACM3

OPAMPTS922IPT

Null

Gain

Temp +

Temp -

+5V

FPGA

OP1

OP2

RG

RD

R2R1

RF

VREFZREF

VIN

••

ug037_c1_02_071103

RD2.5V2mA------------ 1250Ω= =

Y mX b+=

0 m0.7 b+=

5 m0.35 b+=





giving the equation of the op-amp circuit as:

The op-amp equation is:

Solving this equation results in different resistor values:

RF = 315 KΩ , RG = 22 KΩ , R1 = 35 KΩ , R2 = 100 KΩ

Because the FPGA’s temperature sensing diode specifications are not known, the circuit cannot be made with fixed resistor values. The RF and R1 resistors are variable (potentiometer). Because of the possibility of circuit instabilities, the value of the potentiometers cannot be too large. Using a value of one-third of the calculated resistor value in series with the remaining resistor is appropriate.

VOUT 14.3V– IN 10+=

VOUT VINRFRG--------

⎝ ⎠⎜ ⎟⎛ ⎞

– VREFR1

R1 R2+--------------------

⎝ ⎠⎜ ⎟⎛ ⎞ RF RG–

RG---------------------

⎝ ⎠⎜ ⎟⎛ ⎞

+=

m b





LVDS Loop and Connector Board Schematic Description (Pages 2 and 3 of 8 (10))

Power and I/O Array Connectors

Both schematics show the organization of the power and I/O array connectors.

These connectors are selected with following criteria in mind:

• High pin count per square area• Surface mount

• High current per pin (one amp for 160 pins and a temperature rise of 20 °C)

• Low level of contact resistance (average: 7.8 mΩ)• Availability

• Excellent crosstalk parameters (differential and single ended). Consult the manufacturer’s test data. Figure 1-8 and Figure 1-9 show differential and single-ended crosstalk and rise-time parameters, respectively.

Figure 1-8: Differential Crosstalk and Rise Time Parameters

Differential Crosstalk

G = GroundD = Signal pairM = Measurement pair

D1

G

M1 M2

D2

G G G

G G G G

G G G G

G

G

G

G

D1

G

M1 M2D2

G G G

G G G

G

G

G

G

GG

G

G

G

G

0.01%0.04%0.58%FEXT

0.02%0.08%0.17%NEXT

500 ps100 ps30 psSignal Rise Time

0.04%0.17%0.41%FEXT

UD0.05%0.15%NEXT


ug037_1_03_121002





The array connectors used for FPGA I/O signal routing have every signal pin surrounded by ground pins. This practice ensures:

• A very good ground plane connection between the two boards

Simulations showed connections that are as good if not better than when the design was routed on a single PCB

• The guidelines for crosstalk, current-per-pin, and so forth are respected

Compactness of design and cost (area, layers, money) are key reasons for this approach.

A single PCB with the same functionality would:

• Cost more than twice the size of the two PCBs used now

• Keep signals as short as possible• Require more layers, up to 12

♦ The Power I/O board is a four-layer PCB

♦ The FPGA board is a ten-layer PCB

This approach enables use of a low-cost PCB (few layers) over a high-end PCB (many layers).

The two schematic drawings are organized as follows:

• The I/O array connectors are 10 by 30 pins. For the schematic organization the connector is divided in columns (from A to AD).

• On the schematic, the connector numbering starts at the right and first takes bank 0 or bank 4. A “Y” or “A” indicates that the connector continues with bank 1 or bank 5. This part of the drawing ends in a “Z” or “B”.

• The array connector of bank 0 and bank 1 (connector J1/J2) continues on sheet one showing the JTAG connections.

• The array connector of bank 4 and bank 5 (connector J3/J4) continues and ends on sheet one showing the JTAG, Serial, and SelectMap connections.

• The power connectors all have the same pinout.

• Decoupling capacitors are placed close to the connectors.

The graphical setup of these connectors is shown in “Array Connector Numbering”.

Figure 1-9: Single-Ended Crosstalk and Rise Time Parameters

Single-Ended Crosstalk

G = GroundD = Signal pairM = Measurement pair

D

G

G

G M G

G G G G

GG

D

G

GG

G G G

G G G

G

G

M

G

G

0.11%0.40%0.95%FEXT

0.32%1.24%2.12%NEXT


0.06%0.22%0.74%FEXT

0.32%0.18%0.52%NEXT


ug037_1_08_072403





LVDS Loop and Connector Schematic Description (Page 4 of 8 (10))

Main I/O and Clock

This schematic shows the four I/O banks used for peripheral connections. All the I/O shown here is routed to the two array connectors placed on the top and bottom of the PCB.

• The board can be used with an XC2VP7, an XC2VP20, or an XC2VP30 Virtex-II Pro FPGA in an FF896 package. When an XC2VP7 is mounted on the board, all peripherals can be used. When an XC2VP20 or XC2VP30 is used, extra I/O in the array connectors is available.

The connection differences between the two FPGAs are shaded on the schematic.

• Every device has dynamic-controlled impedance (DCI) resistors.• SelectMap and serial configuration pins are dedicated for these functions.

The clock connections on the board were designed to be flexible. The Virtex-II Pro devices have 16 single-ended clock inputs, eight differential clock inputs, or any combination of these.

These clock inputs can be used several ways:

• Two clock traces coming from the array connectors are used as single-ended clock inputs

The clock signals are differential LVDS signals from the array connectors. They convert to single-ended signals, close to the FPGA, using high-quality LVDS receivers. This way a very good and stable clock signal is distributed to the FPGA through the connector.

When the Xlvds_Fpga board is plugged onto the XlvdsPro_PwrIo board, these clock inputs are connected to two oscillators (125 MHz and 156.25 MHz) mounted on the clock board. Read Chapter 10, “Oscillator Interface,” in the XlvdsPro_PwrIo board section for more information.

• Two other clock inputs are routed to on-board SMA connectors. Inputs are either single ended or differential, but must be fed from an external lab generator.

• Eight clock inputs are used as four differential clock inputs. These FPGA clock inputs are routed on the PCB to a set of high-speed connectors.

The connectors also have inputs for power (5V), four control inputs coming from the FPGA I/O, and an enable signal from a DIP switch. This shows the enormous flexibility available for clock sources. For more information on clock possibilities, read Chapter 3, “Clock Interfaces.” Figure 1-10 shows the clock connector pinout.





• The remaining four clock inputs are used as differential LVDS clock inputs for the LVDS tracks routed on the PCB.

Figure 1-10: Samtec QSE-014-01-L-DP

UG037_C2_01_022603

+5V

Enable

Output

Control

Control

Gnd

Gnd

Gnd

Gnd

Gnd

Gnd

Gnd

Gnd

Gnd

Gnd

1

240

39

LoopFB

nc





LVDS Loop and Connector Board Schematic Description (Pages 5 and 6 of 8 (10))

This schematic contains four MGTs, a part of the Virtex-II PRO FPGAs. It also contains the power supply for these MGTs.

Two MGTs, at each side of the FPGA, are supplied with MMCX RF connectors. The reference design uses balanced 50 Ω equipment. The other MGT pair on that side is directly coupled to create a loop link.

The power supply is designed carefully for low noise and good RF suppression. The 2.5V used in the MGT core uses an ADP3338 device. This device is a very stable with high speed and low noise. Filtering with ferrite beads performs the RF suppression.

An ultra low-noise, ultra low-dropout linear regulator (LP2985) supplies VT_TX and VT_RX as a reference voltage. Simple potentiometer dividers create the desired voltage. An 80 mA op-amp buffer supplies the power to the MGT VT_TX or VT_RX.

RF is suppressed by good filtering techniques using a ferrite bead and different capacitors to ensure low ESR over the frequency range starting from ~700 KHz. This MGT power supply method saves board area resources.

Calculations and the design of the power supplies are provided in the “Power Supply Calculations” section.

The location of the clock inputs of the FPGA and their relationship to the MGTs is shown in Table 1-1.

Table 1-1: Location of the FPGA Clock Inputs and the MGTs

Board Side

Bank Signal NamePin

NumberClock Type

Clock Source

Top

Bank_0

IO_L74N_0/GCLK_7P C16

IO_L74P_0/GCLK_6S B16

IO_L75N_0/GCLK_5P G16BREFCLK

To Clock ConnectorIO_L75P_0/GCLK_4S F16

Bank_1

IO_L75N_1/GCLK_3P F15BREFCLK2

To Clock ConnectorIO_L75P_1/GCLK_2S G15

IO_L74N_1/GCLK_1P B15 EXTOSC1

EXTOSC2IO_L74P_1/GCLK_0S C15

Bottom

Bank_4

IO_L74N_4/GCLK_3S AF15 X_CLK1

X_CLK2IO_L74P_4/GCLK_2P AG15

IO_L75N_4/GCLK_1S AH15BREFCLK2

To Clock ConnectorIO_L75P_4/GCLK_0P AJ15

Bank_5

IO_L75N_5/GCLK_7S AJ16BREFCLK

To Clock ConnectorIO_L75P_5/GCLK_6P AH16

IO_L74N_5/GCLK_5S AG16

IO_L74P_5/GCLK_4P AF16





MGT Power Supply Design

The entire power supply consists of separate supplies: the switched mode power supply delivering all power for the demonstration development system and small separate power supplies for each MGT device. A top-level diagram of the power supply is shown in Figure 1-11.

This section focuses on the MGT power supply and PCB layout of the power supply.

Hardware Schematic Diagram

Figure 1-12 shows the schematics of MGT VCCAUX power supply. Figure 1-13 shows the schematics of the MGT VT power supply.

Figure 1-11: Power Supply

7V – 25V DC

SMPS

LTC1628C

5V

3.3V

Linear Regulators

2.5V

1.5V

2 X LM1117DTX

4 X LM1117DTX3200 mA Max.

1600 mA Max.

4000 mA Max.

4000 mA Max.

Linear Regulators

1.6V - 2.6V

2.5V

TS922IPTLP298x

ADP3338

Peripherals

FPGAVCCCORE

FPGAMGT VCCAUX

FPGAMGT VT

FPGAVCCIO

ug037_1_06_060403

Figure 1-12: MGT VCCAUX Power Supply

22nF1µF/10V10nF220pF

VCCAUX FIL

DNA(4.7nF NPO)

47µ/16VTant

100nF100nF

47µ/16VLow ESR

ADP3338-2V5

InOut

Adj

DNA

DNA

0Ω

DNA

3.3VThe regulator can deliver 1A andcan be used by four MGT devices.

Per FPGA MGT input of VCCAUXthe capacitor and ferrite beadcircuit must be designed.

DNA (Do Not Assemble)components can be designed on the PCB to make the VCCAUX supply adjustable if necessary. ug037_1_07_060403





Power Supply Calculations

VCCATX and VCCARX Regulator

These supplies are derived from the 3.3V supply using a low-dropout linear regulator. High-quality input and output capacitors to the regulator (ADP3338) reduce the input voltage ripple (



Table 1-2 lists the characteristics of the regulator.

VT_TX and VT_RX Regulator

This power supply must be a high-quality power supply, providing a noise-free and very stable output. Therefore the power supply is designed as a high-precision ADC/DAC reference supply. These circuits typically are made with good-quality, high-output current op-amp devices.

Each MGT circuit needs a typical ITTX of 30 mA (AC coupled device).

The used op amp must be able to supply double the current at worst case. A good candidate is the TS922 device from STMicroelectronics. This device has a rail-to-rail input and output. It provides latch-up immunity. Table 1-3 summarizes the specifications for the op amp.

A stable, clean 3.3V reference voltage is obtained using an LP2985 circuit. This regulator does not need to deliver any current other than the one needed for four voltage dividers (~25 mA).

The LP298 output is fed to a voltage-follower op-amp circuit. Two op amps are available per package: one for building a circuit for VT_TX and the other for VT_RX. Each op amp can supply 80 mA. The circuit is shown in Figure 1-14.

Table 1-2: Regulator Characteristics

Parameter Value

Accuracy over line and load variations 1.4%

Maximum output current 1 A

Line regulation 0.04mV/V

Load regulation 0.006mV/mA

Ground current 0.9 mA at 100 mA load

Table 1-3: Op Amp Characteristics

Parameter Value

Low noise

Low distortion 0.005% (THD)

High output current 80 mA (able to drive 32Ω loads)

High speed 4 MHz, 1.3V/µs

Operating voltage range 2.7V to 12V

Low input offset voltage 900 µV maximum

ESD internal protection 2kV

Capacitive load stability 500 pF maximum

9nV Hz⁄





A low-pass filter, C1R1, filters noise from the reference and op-amp buffer. The -3 dB corner frequency of the filter is .

Possible DC errors and noise can be caused by the R2 resistor due to the small amount of bias current flowing. The R2 value should be kept fairly low. The value of R1 should be between 10Ω and 50Ω . R1 is in the feedback loop, and any current, due to the leakage current of the capacitor C1, flows through it (the voltage dropped across R1 is divided by the loop gain). The value of C1 is the parallel circuit of all capacitors at the output; large capacitive loads can be driven due to the output resistor (R1) and feedback resistor (R2). Only one capacitor is important, C12. One regulator circuit drives two loads; thus two C12 capacitors must be taken in parallel for the calculation.

When a corner frequency of ~3 KHz is wanted, values for C1 and R1 are chosen as:

C1 = 2 µF and R1 = 22Ω

C1 = 2 × C12, thus C12 = 1 µF

If C2 is 5% of C1, then the value of R2 is determined with the formula C2R2 = 2C1R1 (approximation of the transfer function). The other capacitors eliminate extra high frequencies. The placement of each capacitor with respect to the MGT is determined by the value and frequency of the capacitor.

MGT PCB Layout

The layout of the MGT signaling and power supply traces is on the top and bottom layers of the PCB. An inner layer distributes power supply tracks. All other layers have ground planes in the MGT area. All ground planes are firmly coupled by strategically placed vias.

When using normal FPGA I/Os together with the MGT, routing through, above, and under MGT tracks is nearly impossible due to signal integrity issues. Some guidelines for creating a possible PCB stackup are listed below:

Figure 1-14: Voltage-Follower Op-Amp Circuit

−

+

FIL

220pF 10nF 1µF

1µF

22nF

C12

C1

R1

R2

C2

VREF

R1 = 22ΩC2 = 220pFR2 = 2.2KΩRF1 = 82ΩRPOT = 200Ω RF2 = 270Ω

FIL

220pF 10nF 22nF

FIL

C12

RF1

RF2

RPOT

ug037_1_09_072903

12πC1R1-------------------





• Top and bottom layers are used for MGT signaling and power supply chip interconnections (connections between regulators, op amps, resistors, and capacitors)

• The second layers (Top-1 and Bottom+1) are used as ground planes for the entire PCB. This ground plane CANNOT be used for something else.

• The third layers (Top-2 and Bottom +2) can be used for high speed and other signaling traces. When used for signaling traces, the space occupied by these traces must not have copper placed in the layer under (counting from the top) or the layer above (counting from the bottom).

• The fourth layers (Top-3 and Bottom+3) can be used for signaling and VCC. The high-speed signal areas on the third layer must not have a copper surface.

• The fifth layers (Top-4 and Bottom+4) are used for VCC and GND routing for the LVDS signals routed in the third layers (Top-2 and Bottom-2).

An example of the PCB layer stackup is shown in Figure 1-15.

Figure 1-15: PCB Layer Stackup

Top Layer : SignalsLVDS + MGT signal

Bot Layer : SignalsLVDS + MGT power

2nd Top Layer : Ground

2nd Bottom Layer : Ground

3rd Top Layer : Signals

4th Top Layer : Signals

4th Bottom Layer : Signals

5th Top Layer : GND + 1V5

5th Bottom Layer : 2V5 + 3V3

Some LVDS + Clocks

3rd Bottom Layer : SignalsSome LVDS

Cleared for 3rd Top LVDS

Cleared for 3rd Bot LVDS

18µ100µ 100µ 35µ

200µ core

200µ core

200µ core

200µ core

35µ

Standard 10ML

100µ 100µ 35µ

35µ 100µ 100µ 35µ

35µ 100µ 100µ 35µ

35µ 100µ 100µ 18µ

GND for 3rd Top LVDS

GND for 3rd Bot LVDS

LVDS Routing

7.0mil

5.5mil

7.0mil

45mil

2125 prepreg2125 prepreg





Single ended trace: 13mil → 50Ω/7 mil→ 69Ω

5mil + 6.25mil + 5 mil → 113Ω

Differential trace:7mil + 5.5mil + 7mil → 109Ω → 69ΩSE

ug037_1_15_060403





PCB routing cut-out figures of the MGT design are shown in Figure 1-16 through Figure 1-20. All other layers have a ground plane in this area.

Figure 1-16: Top Silk Screen

Figure 1-17: Top Layer

ug037_c1_10_071103

ug037_1_11_121002





Figure 1-18: Third Top Layer

ug037_1_12_121002

Figure 1-19: Bottom Layer

ug037_1_13_121002





Figure 1-20: Bottom Silk Screen

ug037_1_14_121002





LVDS Loop Board Schematic Description (Pages 7 and 8 of 8)This schematic contains part of a 64-bit LVDS high-speed loop. Basically, this loop transmits on I/O bank 2 and I/O bank 3, and receives at I/O bank 7 and I/O bank 6. This loop is based on LVDS 100 Ω signaling on a 2.5V FPGA. In each loop, a Tektronix P6880 probe can be attached to the board.

This connector can show “Clock”, “Sync” and six regular loop data signals. The seventh signal is for proving influences in measuring method via SMA connectors.

Note: The Tektronix pads have virtually no influence in signal transmission; however, routing via a connector does influence the signal transmission.

Inner pads on the banks are not used, which provides space for decoupling capacitors and vias for the Xilinx FPGA core.

Figure 1-21 and Figure 1-22 give information on calculation and layout of single-ended tracks. The calculation program uses TXline and Polar Si9000.

Figure 1-21: Transmission Line Calculator (Microstrip Tab)





The impedance between the top layer (signals) referenced to the second top layer (GND plane) is 50Ω @ 11 mil (shown in Figure 1-23). This is true for single-ended signals.

Figure 1-22: Si6000-Controlled Impedance Quick Solver (Surface Microchip)

Figure 1-23: Transmission Line Calculator (Stripline Tab)





The impedance between the third top signals referenced to the second top (GND plane) and the fourth top (GND + Power) is 50Ω @ 5.5 mil (shown in Figure 1-24).

The differential impedance between the top layer referenced to the second top (GND plane) is 100 Ω @ 5.6 mil - gap of 3.4 mil - 5.6 mil (shown in Figure 1-25). The single-ended impedance is about 66 Ω.

Figure 1-24: Si6000-Controlled Impedance Quick Solver (Edge-Coupled Surface Microstrip)

Figure 1-25: Transmission Line Calculator (Microstrip Tab), Differential Impedance





LVDS Connector Board Schematic Description (Page 7 of 10)On this board, the LVDS loop is broken. This schematic shows the receiver side on I/O bank 7. A 32-data, clock, and sync bus is routed from two high-speed differential Samtec QSE connectors to the FPGA. Six extra data channels go from these connectors to I/O bank 6.

The DCI inputs of this bank are free and available on test PCB pads, which helps to provide LVDS DCI termination. Remove the discrete termination resistor when using DCI.

Connector Setup

There are two LVDS connectors on the LVDS Connector board:

• QSE-RX3 Front Right (J37)

LVDS data channels 38 to 63, 26-bit data, clock and sync

• QSE-RX2 Front Middle (J38)LVDS data channels 32 to 37

Together these connectors form a 32-bit LVDS data bus.

Six LVDS spare data channels are routed to Bank 6. These can extend the 32-bit bus to 38 bits.

These connectors have 5V, 3.3V, and 2.5V power supply connections.

LVDS Connector Board Schematic Description (Page 8 of 10)All pins of this connector (QSE-RX1) are routed to I/O bank 6 to form a 26-bit LVDS data, clock and sync bus.

The DCI inputs of this bank are free and available on test PCB pads to allow LVDS DCI termination. Remove the discrete termination resistor when using DCI.

This schematic also contains the differential measurement and test traces.

• 50 cm differential (on top layer) striplineSMA connectors J39, J40, J41, and J42 (termination at J39, J40)

• 50 cm differential embedded asymmetric stripline

SMA connectors J43, J44, J45, and J46 (termination at J43, J44)

• Single-ended (on top layer) stripline

SMA connectors J48 and J50

• Single-ended embedded asymmetric striplineSMA connectors J47 and J49

LVDS Connector Board Schematic Description (Page 9 of 10)The schematic contains the transmit side of the LVDS channels. I/O bank 3 is routed to a set of two connectors forming a 32-bit data, clock, and sync LVDS bus.

Connector QSE_TX1 (rear left) is routed as a 26-bit data, clock, and sync bus, while QSE-TX2 (rear middle) contains the extra data bits, forming a 32-bit data LVDS bus.

In connector QSE_TX2, there are six spare LVDS data channels coming from I/O bank 2. This same connector has 5V, 3.3V, and 2.5V power supply connections.





LVDS Connector Board Schematic Description (Page 10 of 10)I/O bank 2 is routed to connector QSE_TX3 (rear right), forming a 26-bit LVDS data, clock, and sync bus.

PCB LayoutRefer to Chapter 2, “PCB Layout Guidelines,” for PCB layout guidelines and in the Excel spreadsheet in the reference design file called Impedance Calculator.xls. The PCB material used is FR4 (Dielectricum Er = 4.7).

During design and layout, special attention was made to the complete PCB and to special areas, the LVDS loop and MGTs. These areas are explained in more detail in subsequent chapters in this user guide.

Web References

Connectors

http://www.samtec.com/search/series.asp

Select in the pull down list: QSE-DP

LVDS

http://www.national.com/search/search.cgi/main?keywords=DS90&GO.x=7&GO.y=10

Voltage Regulators

http://www.national.com/pf/LP/LP2985.html

http://products.analog.com/products/info.asp?product=ADP3338

Op Amps

http://us.st.com/stonline/books/toc/ds/391.htm


http://www.xilinx.comhttp://www.samtec.com/search/series.asphttp://www.national.com/search/search.cgi/main?keywords=DS90&GO.x=7&GO.y=10http://www.national.com/pf/LP/LP2985.htmlhttp://products.analog.com/products/info.asp?product=ADP3338http://us.st.com/stonline/books/toc/ds/391.htm



Array Connector NumberingFigure 1-26, Figure 1-27, and Figure 1-28 have the global pinout of the different array connectors on the XlvdsPro_Fpga board.

Figure 1-26: Power Connectors J5 (J6) and J7 (J8)

A B C D E F G H I J K L M N O P Q R S T

10

9

8

7

6

5

4

3

2

1

Ground 5V

1.5V VRough = Input voltage

2.5V VBAT

3.3V

ug037_1_22_060403





Figure 1-27: Banking Connector J1 (J2) Connects to J32 of the PowerIO Board

Bank 0 Bank 1

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD

10

9

8

7

6

5

4

3

2

1

nu (Not Used) PS2 Interface Clock connections

Ground Ethernet Spare IO for a XC2VP20

LCD Display UARTs

Keypad Matrix LED

LED System Configuration

3.3V 5V

ug037_c1_27_070603





UCF InformationThe master UCF document is available for viewing in the following formats:

• DOS text format

• MS-Excel format

Figure 1-28: Banking Connector J3 (J4) Connects to J16 of the PowerIO Board

Bank 4 Bank 5

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD

10

9

8

7

6

5

4

3

2

1

nu (Not Used) PS2 Interface Clock connections

Ground Ethernet Spare IO for an XC2VP7

Spare IO when an XC2VP20is mounted

LCD Display UARTs

Keypad Matrix LED

LED System Configuration

3.3V 5V

ug037_c3_09_070603




R

Chapter 2

PCB Layout Guidelines

GeneralThis chapter is not intended to be a complete PCB design guide (several hundred pages would be needed), but it can make the PCB designer aware of several design points and increase the efficiency of the design. Remember that PCB design is not just putting traces on a piece of hard material in order to make electronic components do something meaningful.

Square WavesThis section provides an introduction to square waves, frequencies, and rise times.

Currently FPGAs are fast to very fast devices. Board designers take care of those high-speed clock and signal routes on the PCB. But what about slow-running signals? Very often designers overlook these slow signals during layout. Important considerations to take during a design are:

• Take care of the fast clocks• Take care of the fast switching signal lines

• Take care of all fast differential signals

• Put the slow signals where space is available

In nearly all cases these so-called slow signals have the same rise times as the fast switching signals because the same FPGA I/Os are producing them. What makes them slow, in the eyes of a not so careful designer, is the frequency of operation.

In most cases, the signals are controller signals running at a derivative of the system frequency, but they are still square-wave signals with a rise and fall time of the high-speed switching signals.

A square wave is a composition of many harmonic sinusoidal signals. The relationship between the sinusoidal signals and the square wave can be expressed as:

This equation shows that relatively slow switching signals can have very high, strong harmonics. These harmonics are the frequencies with which we need to work.

Another main component here is the rise time of these signals. The signals are generated with

XLVDSPro Demonstration Boards - Xilinx€¦ · 08/25/03 1.1 Modified J1 through J8 connector names in Figure 1-1, Figure 1-3, Figure 1-4, and Figure 1-5. 09/18/03 1.2 Added new figure,

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