1. Create a new projectChyISEDesign Suite .Chn "New project"...
- in tn v th mc cha project. mc TOP-LEVEL SOURCE TYPE chnHDL. Sau nhn NEXT.
Chn thit b, mc device v Family cc bn chn lit v dng kit FPGA mnh ang s dng. Cc mc cn li cc bn chn nh hnh.Sau nhn NEXT.
2. Add the top-level fileClick phi v chn "New Source"...
- Chn "Verilog Module" nu bn s dng ngn ng verilog lp trnh sau t tn cho module.
Sau nhn NEXT.
n y chng ta c th bt u phn lp trnh verilog. Ch nh va lp trnh va SAVE phong mt in
3. Assign the pinsClick vo project mi to v chn "New Source".
Chn "Implementation Contraints File", v t tn...
V g code nh hnh.
Ch : Cc cng vo-ra u phi c gn chn.
4. Set the programming propertiesChn "ledblink" top level, sau chn process properties
5. Generate the FPGA programming fileNhn chut phi vo Generate programming v chn RUN kim tra chng trnh.
Lm tip tc vi cc mc SYNTHESIZE, IMPLEMENT DESIGN...
