Xilinx XAPP596 4K2K Up-Converter Reference Design reference designs are up-converter, frame rate converter, and mosaic (multi-window). This docu ment addresses the first reference
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Summary In the digital display market, the next innovation wave—ultra-high definition (UHD) 4K2K—is now emerging. Getting to market faster than the competition with 4K2K viewing experiences is the challenge for product development designers. Xilinx® Kintex®-7 FPGA Display Targeted Reference Designs give designers immediate access to the power efficiency and price-performance of 28 nm 7 series FPGA devices for efficiently managing increased bandwidth and algorithm complexity. Xilinx provides three reference designs enabling customers to concentrate on product differentiation by providing basic infrastructure for 4K2K digital display signal processing. These reference designs are up-converter, frame rate converter, and mosaic (multi-window). This document addresses the first reference design, the up-converter.
Introduction This high definition (HDTV) to 4K2K up-converter reference design enables up-conversion from 1080p HDTV to 4K2K progressive images. The up-conversion results in showing HDTV content, which is very popular in broadcasting and packaged media, on a 4K x 2K flat panel display.
The reference design is built from the following LogiCORE™ IP in the Xilinx Video and Image Processing Pack (VIPP):
• Video Scaler
• On-screen Display (OSD)
This reference design has two display modes. One is the up-converter mode, which shows an HDTV image on 4K2K flat display panels in various sizes, enabling zoom up to twice the original sizes. The other is the mosaic mode, which shows the same HDTV input images on each quadrant of a 4K2K screen, in live motion pictures or still images.
This document contains the following contents that enable designers to use the reference design as the basis of their 4K2K digital display product development:
• Reference design demonstration setup
• Reference design overview
• Build an HDTV to 4K2K reference design project
The advantage for application designers is that they can use this reference design for the basis of their own 4K2K up-converters, enabling them to concentrate on picture quality tuning. The picture quality of 4K2K up-converters is key to the market growth of 4K2K display products, which then enables the utilization of the large volume of HDTV (1080p @60 Hz) content available in the market today.
The demonstration involves both hardware and software setups. To quickly bring up the demonstration, the EDK project ships with a pre-built file in the EDK/implementation directory (file name: download.bit).
Hardware Inventory
The hardware required for the demonstration includes:
• Inrevium Kintex-7 FPGA ACDC1.0 base board (TB-7K-325T-IMG)
Connect the signal source and monitor as shown in Figure 1.
1. (1) Connect HDMI input cables.
2. (5)–(8) Connect HDMI output cables.
3. (9) Connect AC/DC adaptor cables.
4. (10) Connect download cable.
5. (15) Connect UART cable. For UART configuration, see Figure 3.
HDMI input/output positions are shown in the top left of Figure 1.
Data Downloading
1. (11) Turn the power switch on and download the FPGA program (download.bit in the EDK/implementation directory), using the program cable and the IMPACT downloading tool.
2. When the FPGA configuration is complete, (14) LED24 (red) turns off and LED23 (green) turns on.
3. (13) Set DIP switches and (12) press the Reset switch.
4. Wait for initialization to finish (writing the OSD logo from flash memory takes about 25 seconds).
Demonstration
1. Wait for the UART display screen, as shown in Figure 4.
2. Reset the HDMI 1.4 TX board.
3. Execute the 4K2K up-converter/demonstration mode by UART using the a command.
Figure 5 shows the data flow when the combined demo sequence of the mosaic and up-converter modes is initiated by the a command on the UART screen. In Figure 5, the red arrows show the data flow throughout the input from the HDMI Rx board to the HDMI Tx board.
The data flow and timing for each operational mode is described in Operational Mode, page 24.
Memory bandwidth and utilization calculations shown in Figure 5 are further described in Table 2. The memory utilization of this design is 38.9%, allowing additional memory data access for additional functionality.
4K2K Up-Converter Reference Design
Overview
This function can output 4K2K at 60 frames per second (fps) by inputting one 1080p 60 and performing scaling and OSD processing. The video processing IP in this design are the scaler and the OSD, which come from the Xilinx Video and Image Processing Pack. The external DDR3-SDRAM operates in 1600 Mb/s, 64 bits of the video IP, and performs AXI4-Stream data communication. The following provides a cursory description of video IP.
X-Ref Target - Figure 5
Figure 5: Data Flow
(Not used incurrent design)
xsvi_to_axi4s
axi_7series_ddrx
DDR3-SDRAM 1600M (x64 bit = 12,800 MB/s)
axi_scaler
axi_osd
MicroBlaze Processoraxi_intc
XAPP596_05_013113
S_AXI
axi_vtc
RX
RX
x4
64-bit
AXI4_InterConnect
xsvi_mux_tx
M_AXI
axi_vdma_deint
M_A
XIS
axi_vdma_scaler axi_vdma_osd
AXI4LITE_InterConnect
hdmi_rx
TB
-FM
CH
-HD
MI2-R
XH
DM
I1.4
xsvi_mux_rx
hdmi_tx
TB
-FM
CH
-HD
MI2-T
XH
DM
I1.4axi_uartlite
TX
TX
x4
x4 x4 x4
x4
x4 x4 x4
x4
2 3 4 51
Table 2: Memory Calculations
Memory Bandwidth 1
Memory Bandwidth 2
Memory Bandwidth 3
Memory Bandwidth 4
Memory Bandwidth 5 Total
Frame buffer size(H x V x bits) N/A 1920 *1080 *32 1920 *1080 *32 3840 *2160 *32 1920*1080 *32
fps N/A 60 15 15 60
Channels N/A 1 4 4 4
Memory bandwidth (MB/s) 0 498 498 1991 1991 4978
DDR3 SDRAM memory bandwidth (MB/s) 1600M x 64 bits 12800
Figure 6 shows the functional block diagram of the FPGA. This system converts a 1080p @60 fps image into a 4K2K @60 fps image using the Xilinx scaler IP cores with OSD overlaying.
1080p HDMI input is fed to a sxvi_axi4s block through input signal reception blocks.
The output of the sxvi_axi4s is fed into the scaler through the AXI4 interconnect.
X-Ref Target - Figure 6
Figure 6: Functional Block Diagram
xsvi_to_axi4s
axi_7series_ddrx
DDR3-SDRAM 1600M (x 64 bit = 12,800 Mb/s)
axi_scaler
axi_osdMicroBlazeaxi_intc
Progressive
RGB444 30 bit
1920xc1080x60pClock:
148.5 MHz
Progressive
RGB444 30 bit1920xc1080x60p
Clock:148.5 MHz
XAPP596_06_012133
S_AXI
axi_vtc
RX
RX
x4
64 bit
AXI4_InterConnect
xsvi_mux_tx
M_AXI
axi_vdma_deint
M_A
XIS
axi_vdma_scaler axi_vdma_osd
AXI4LITE_InterConnect
hdmi_rx
TB
-FM
CH
-HD
MI2-R
XH
DM
I1.4
xsvi_mux_rx
hdmi_tx
TB
-FM
CH
-HD
MI2-T
XH
DM
I1.4
axi_uartlite
TX
TX
x4
x4 x4
x4
x4 x4 x4
x4
AXI4-Lite Protocol Bus AXI4 Protocol Bus AXI4-S Protocol Bus XSVI Protocol Bus
The Xilinx scaler can achieve an output of 3840 x 2160p (4K2K) @24 fps (see DS840, LogiCORE IP Video Scaler v4.0). This reference design uses four Xilinx scaler cores in four-frame sequential multiplexing, resulting in up-conversion into 4K2K @60 fps (15 fps * 4). This sequence is shown in Figure 7. The timing of this sequence is described in Figure 16 in Operational Mode, page 24.
The output of the scaler goes to the OSD module so that on-screen display characters for the demonstration can be added.
X-Ref Target - Figure 7
Figure 7: 4K2K Up-Converter Time Multiplex Use of Scaler
Figure 8 shows an FPGA clock generation diagram. A 200 MHz input clock is fed to clock generation blocks and the DDR user clock, HDMI TX clock, and 50 MHz system clocks are generated. HDMI RX clocks are buffered and supplied to the system.
Figure 9 shows a reset generation diagram. Several reset signals are generated in synchronization to the clocks by proc_sys_reset block from the original reset input.
Functional Descriptions of Each Block
When the user opens the EDK project file, a listing of the blocks that are on the block diagram appears, as shown in Figure 6, page 9. Figure 10 shows the screen shot of the directory listing shown when you open the EDK project. The red marked area shows the block list. (Not all the blocks in Figure 6 are shown in this screen shot.)
In mosaic mode, one channel input is supported. Live output images or memory-stored images (still or motion) are mapped on the 4K2K screen with some characters added by OSD.
Figure 13 shows the data flow in mosaic mode. The Input full HD image signal comes from the RX0 input of the HDMI card (on LPC2 FMC connector) and is fed to the xsvi_axi4s module. This image signal is fed into DDR3-SDRAM through the AXI4_InterConnect as four source images to make up the mosaic image (datapath (2)).
Four output images from memory are fed to axi_osd module (datapath (5)). These four images are T/L (top left), T/R (top right), B/L (bottom left), and B/R (bottom right), which corresponds to the quadrant position of the 4K2K display screen. In the demonstration of this reference design, live picture, still picture, and the combination from the memory can be shown.
In the axi_osd module, some characters and graphics such as the Xilinx logo from xsvi_mux_tx are overlaid. Output images from the axi_osd module are transferred to HDMI Tx card and output from Tx0, Tx1 port of 2 HDMI FMC card on HPC1, and HPC2 FMC connectors.
Figure 14 shows mosaic mode timing. HDMI RX0 Input (60 fps) is written into a DDR3 frame buffer. Frame buffering is used to show a still image in mosaic mode and to maintain the modularity of the system. Readout from the frame buffer starts after one frame period. As a result, the output of the mosaic image is delayed one frame period (approximately 16 ms) from the input image.
Up-Converter Mode
In up-converter mode, 1ch 1080p input is supported. The pass-through output (1920 x 1080) goes to the scaler and the scalar IP upscales the image to 4K2K (3840 x 2160), and characters are added and output by the OSD.
Figure 15 shows the data flow in up-converter mode. The input full HD image signal coming from RX0 input of HDMI card (on LPC2 FMC connector) is fed to the xsvi_axi4s module. This image signal is fed into DDR3-SDRAM through AXI4_InterConnect (datapath (2)).
Four sequential frames are read out in parallel in 15 fps (4X slower than the input frame rate) and fed to axi_scaler module (datapath (3)). In the axi_scaler module, the image signal processing to increase the pixel density to 4K2K is executed. Outputs from axi_scaler module
are written back to the frame buffer (datapath (4)). These images are read out as four 4K2K image stream quadrants in 60 fps and fed to the axi_osd module (datapath (5)).
In the axi_osd module, some characters and graphics such as the Xilinx logo from xsvi_mux_tx are overlaid. Output images from the axi_osd module are transferred to HDMI Tx card and output from Tx0, Tx1 port of 2 HDMI FMC card on HPC1, and HPC2 FMC connectors.
Figure 16 shows the up-converter mode timing. The HDMI RX0 Input is written to a frame buffer through the AXI4_InterConnect (datapath (2)). Four sequential frames are read out in parallel and fed to axi_scaler module in 15 fps. Outputs from axi_scaler module come out right after the Frame3 input to the frame buffer (datapath (4)). As a result, a 4K2K image in 60 fps comes out approximately eight frames after the input.
4 Channels [Scaler] are working independently to write frames to the external memory.4 Channels [HDMI TX/OSD] are working independently to read frames from the external memory.
In mosaic mode, four OSDs independently output the input images from the xsvi_to_axi4s.
Figure 18 shows the relationship between the output image from the xsvi_to_axi4s and the images from each OSD.
The mosaic mode has two types: Live mode and still mode. The live mode provides real-time output of the input images and the still mode provides still images, without updating them.
In up-converter mode, input images (1920*1080p) are scaled 1/2 to 2.0 larger (960*540 to 3840*2160) by the scaler. The scaling factor can be varied frame by frame resulting in smooth zooming. The scaled picture is mapped on the frame with 3840 * 2160 resolution and 1/4 pictures (1920*1080) are output by each OSD.
Figure 20 shows the relationship between the scaler output and the OSD output.
Up-converter mode provides real-time effectiveness of zoom by changing the scaler and OSD parameters. The parameters change at the occurrence of an OSD VDMA interrupt signal. The software calculates parameters by the OSD VDMA interrupt handling function, and sets the parameters to scaler, VDMA, and OSD.
Figure 21 shows the control flow in up-converter mode.
The general mode provides a combined demonstration by continuously switching the mosaic and up-converter modes. Figure 22 shows the control flow in general mode.
The reference design utilization summary is listed in Table 11.
Conclusion This HDTV to 4K2K up-converter reference design is part of the Kintex-7 FPGA-based Display Targeted Design Platform. This design enables easily accessible HDTV content to be shown on a 4K2K monitor or 4K2K flat panel, providing design engineers with the base for their product designs. With this base addressing the mandatory up-conversion, engineers can focus their efforts on differentiating their 4K2K digital TVs, displays, and projectors.
Revision History
The following table shows the revision history for this document.
Test bench used for functional and timing simulations N/A
Test bench format N/A
Simulator software/ version used N/A
SPICE/IBIS simulations N/A
Implementation
Synthesis software tools/version used ISE® Design Suite 14.3
Implementation software tools/versions used ISE Design Suite 14.3
Static timing analysis performed Yes
Hardware Verification
Hardware verified Yes
Hardware platform used for verification ACDC 1.0 Base Board
Table 11: Resource Utilization
Parameters Specification/ Details
Maximum frequency (by speed grade) -1 200 MHz
Device utilization without test bench (mandatory)
Slices 50525
GCLK buffers 11
Block RAM 361
GTX transceivers 0
HDL language support Verilog and VHDL
Table 10: Reference Design Checklist (Cont’d)
Parameter Description
Date Version Description of Revisions
03/01/2013 1.0 Initial Xilinx release.
04/02/2013 1.0.1 Updated the link in Reference Design, page 37.
06/28/2013 1.0.2 Removed two references to XAPP597.
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