Virtex-6 FPGA GTH Transceivers SFP+ Electrical Specification Characterization Report RPT136 (v1.0) June 10, 2011
Virtex-6 FPGA GTH Transceivers SFP+ Electrical SpecificationCharacterization Report
RPT136 (v1.0) June 10, 2011
Virtex-6 FPGA GTH Transceivers SFP+ Electrical www.xilinx.com RPT136 (v1.0) June 10, 2011
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Revision HistoryThe following table shows the revision history for this document.
Date Version Revision
06/10/2011 1.0 Initial Xilinx release.
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Virtex-6 FPGA GTH Transceivers SFP+ Electrical SpecificationIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Transceiver Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Summary of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7SFP+ Electrical Characterization Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Transmitter Near-End Output Eye . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Transmitter Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transmitter Output Differential Amplitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Transmitter Output Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Transmitter Differential and Common Mode Output Return Loss . . . . . . . . . . . . 16Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Receiver Input Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Receiver Differential and Common Mode Input Return Loss. . . . . . . . . . . . . . . . . 29Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Virtex-6 FPGA GTH Transceivers SFP+ Electrical www.xilinx.com 3RPT136 (v1.0) June 10, 2011
4 www.xilinx.com Virtex-6 FPGA GTH Transceivers SFP+ ElectricalRPT136 (v1.0) June 10, 2011
Virtex-6 FPGA GTH Transceivers SFP+ Electrical Specification
IntroductionThis characterization report compares the electrical performance of the Virtex®-6 FPGA GTH transceiver against the SFP+ (SFI) SFF-8431 electrical specification. The characterization is performed as per SFF-8431 specification at a line rate of 10.3125 Gb/s, 11.1 Gb/s across voltage, temperature, and process corners.
The following tests are included in this report:
• Transmitter Near-End Output Eye, page 8
• Transmitter Output Jitter, page 11
• Transmitter Output Differential Amplitudes, page 14
• Transmitter Output Rise and Fall Times, page 15
• Transmitter Differential and Common Mode Output Return Loss, page 16
• Receiver Input Jitter Tolerance, page 20
• Receiver Differential and Common Mode Input Return Loss, page 29
Virtex-6 FPGA GTH Transceivers SFP+ Electrical www.xilinx.com 5RPT136 (v1.0) June 10, 2011
Test Conditions
Test ConditionsTable 1 and Table 2 show the supply voltage and temperature conditions, respectively.
Transceiver SelectionXilinx first performs volume generic transceiver characterization across process, voltage, and temperature. Protocol-specific characterization is subsequently performed using representative transceivers from generic characterization.
Table 1: Supply Voltage Test Conditions
ConditionMGTHAVCC
(V)MGTHAVCCRX
(V)MGTHAVTT
(V)MGTHAVCCPLL
(V)
VMIN 1.075 1.075 1.140 1.710
VMAX 1.125 1.125 1.260 1.890
Note: Other FPGA voltages stay at their nominal values.
Table 2: Temperature Test Conditions
Condition Temperature (°C)
T–40 –40
T0 0
T100 100
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Summary of Results
Summary of ResultsThe summary in Table 3 shows a comparison of the Virtex-6 FPGA GTH transceiver against the SFP+ SFF-8431 specifications. Data reported in Table 3 represents the worst-case voltage, temperature, and process corner tested.
Table 3: SFP+ Characterization Summary of Results
Test Parameter SpecificationWorst-CaseTest Result
Units Compliant
Transmitter Output Jitter at 10.3125 Gb/s
TJ 0.28 0.251 UI (p-p)(1) Yes
DDJ 0.1 0.0950 UI (p-p) Yes
DDPWS 0.055 0.0285 UI (p-p) Yes
UJ 0.023 0.008 UI (RMS) Yes
Transmitter Output Jitter at 11.1 Gb/s
TJ 0.28 0.234 UI (p-p) Yes
DDJ 0.1 0.0915 UI (p-p) Yes
DDPWS 0.055 0.0146 UI (p-p) Yes
UJ 0.023 0.0102 UI (RMS) Yes
Transmitter Output Differential Amplitude
Min 190 Programmable (2) mV Yes
Max 700 Programmable (2) mV Yes
Transmitter Output Rise and Fall Times
Rise >24 33.9 ps Yes
Fall >24 33 ps Yes
Transmitter Differential Output Return Loss
Frequency Profile See Figure 6, page 17 dB Note (4)
Transmitter Common Mode Output Return Loss
Frequency Profile See Figure 7, page 18 dB Note (4)
Receiver Input Jitter Tolerance at 10.3125 Gb/s
TJ(not including SJ)
0.70 >0.72(3) UI Yes
SJ = 40 MHz 0.05 0.064 UI Yes
Receiver Input Jitter Tolerance at 11.1 Gb/s
TJ (not including SJ)
0.70 >0.72(3) UI Yes
SJ = 40 MHz 0.05 0.064 UI Yes
Receiver Differential Input Return Loss
Frequency Profile See Figure 15, page 26 dB Note (4)
Receiver Common Mode Input Loss
Frequency Profile See Figure 16, page 27 dB N/A
Notes: 1. Peak-to-peak.2. The programmable transmitter output amplitude settings can be found in the TX Configurable Driver section of UG371,
Virtex-6 FPGA GTH Transceivers User Guide.3. Specification required baseline jitter for jitter tolerance testing. The value in the test result column is the amount of jitter injected by
the test setup.4. Return loss is compliant over most of the frequency ranges. Although some frequency ranges are marginal with the frequency
profile, the transmitter and receiver jitter performance shows that the Virtex-6 FPGA GTH transceiver meets or exceeds SFF-8431.
Virtex-6 FPGA GTH Transceivers SFP+ Electrical www.xilinx.com 7RPT136 (v1.0) June 10, 2011
SFP+ Electrical Characterization Details
SFP+ Electrical Characterization DetailsThis section contains the detailed SFP+ test methodology and test results for each test summarized in Table 3, page 7. The GTH transceiver is configured using the Virtex-6 FPGA GTH transceiver Wizard v1.7, including attribute settings. GTH transceiver attribute settings that differ from the GTH transceiver Wizard default setting are identified in the test setup and conditions table for each test.
Table 4 shows the PLL settings used for the characterization.
Transmitter Near-End Output Eye
Test MethodologyThe device is configured to transmit a PRBS15 pattern on each of the TX data pins, and the resulting eye is captured using an Agilent 86100C Infiniium DCA-J wideband oscilloscope for 1000 samples at nominal voltage and T0 conditions. The test setup and conditions are defined in Table 5.
Table 4: PLL Settings
Data Rate(Gb/s)
PLL Frequency (Gb/s)
REFCLK Frequency (MHz)
PLL_CFG0[5:0](N–1)
TXRATE / RXRATE
10.3125 5.15625 156.25 32 2'b00
11.1 5.550 173.4375 31 2'b00
Table 5: Transmitter Near-End Output Eye Test Setup and Conditions
Parameter Value
Measurement Instrument Agilent 86100C DCA-J wideband oscilloscope with Agilent 86108A precision waveform analyzer plug-in module
TX Coupling AC coupled using DC blocks
Voltage Nominal
Temperature T0
Pattern PRBS15
Load Board ML627 characterization platform, Revision B(FF1155)
TX Amplitude GTH attributes:
• TX_CFG0_LANE<n>[6:3] = 4'b0111 • TX_PREEMPH_LANE<n>[7:4] is set to 4'b1010 • TX_PREEMPH_LANE<n>[3:0] is set to 4'b0001
REFCLK Sourced from Agilent N4903A:
• 156.25 MHz for 10.3125 Gb/s• 173.4375 MHz for 11.1 Gb/s
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Transmitter Near-End Output Eye
Test ResultsFigure 1 shows the transmitter near-end output eye at 10.3125 Gb/s. Figure 1 is provided as a representative diagram, and does not quantify device performance. X-Ref Target - Figure 1
Figure 1: Transmitter Near-End Output Eye (10.3125 Gb/s with 156.25 MHz REFCLK)
RPT136_01_040911
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Transmitter Near-End Output Eye
Figure 2 shows the transmitter near-end output eye at 11.1 Gb/s. Figure 2 is provided as a representative diagram, and does not quantify device performance. X-Ref Target - Figure 2
Figure 2: Transmitter Near-End Output Eye (11.1 Gb/s with 173.4375 MHz REFCLK)
RPT136_02_040911
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Transmitter Output Jitter
Transmitter Output Jitter
Test MethodologyTransmitter output jitter was measured using the bench setup shown in Figure 3. The DCA-J/DCA-X is used with the Agilent 86108A precision waveform analyzer to measure the output jitter. The Agilent 86108A contains a hardware clock recovery unit with adjustable loop bandwidth which is set to 4 MHz as required by the specifications.
The measurement is taken with ~3 to 4 inches of channel length between the TXP/TXN FPGA pins and the SMA connectors on the ML627 characterization platform.
X-Ref Target - Figure 3
Figure 3: Transmitter Output Jitter Test Setup Block Diagram
Display
Markers
Channels On/Off
Virtex-6HX380T
FFG1155
On-boardPowerModule
Display
Agilent J-BERT N4903A – 12.5 Gb/s
Infiniium DCA-J 86100C ML627 Rev BVirtex-6 HX380T Board
Agilent 86108A 33 GHz BW
Legend
AutoScale
Run Stop/Single
ClearDisplay
Eye/MaskMode
TDR/TDTMode
OscilloscopeMode
JitterMode
QuickMeasure
SyncInput
RecoverdClk Out
SyncOutput
TriggerLevel
Channel1
Channel2
Jitter Spectrum/Phase Noise
GND
ON/OFF
RXP RXN
CLKP
CLKN
TXP TXNExternalTime Ref In
SMA Matched Pair Cablesfor GTX Clock
SMA Matched Pair Cablesfor GTX Transmitter
DC Blocks
50 Ohm Termination
RPT136_03_050311
Keyboard andMiscellaneous Buttons
Pattern GeneratorTrigger Sub ClkAUX
INERROR
ADD OUT OUT OUT OUT
AutoAlign
PatternSetup
PG EDSetup
Jitter
Analysis/Results
Clk DataCLKIN OUT OUT OUT OUT
DELAYCTRL IN
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Transmitter Output Jitter
Table 6 defines the test setup and conditions for the transmitter output jitter.
Test ResultsFigure 4 shows the transmitter output jitter test results at 10.3125 Gb/s with a PRBS31 pattern and a BER of 10–12.
Note for Figure 4:
1. 10.3125 Gb/s, PRBS31, BER = 10–12.
Table 6: Transmitter Output Jitter Test Setup and Conditions
Parameter Value
Measurement Instrument Agilent 86100C DCA-J/DCA-X wideband oscilloscope with Agilent 86108A precision waveform analyzer plug-in module
TX Coupling AC coupled using DC blocks
Voltage VMIN, VMAX
Temperature T–40, T0, T100
Pattern PRBS31
BER 10–12
Load Board ML627 characterization platform, Revision B(FF1155)
TX Amplitude/ Emphasis GTH Attributes:
• TX_CFG0_LANE<n>[6:3] = 4'b0111• TX_PREEMPH_LANE<n>[7:4] is set to 4'b1010 • TX_PREEMPH_LANE<n>[3:0] is set to 4'b0001
REFCLK Sourced from Agilent N4903A:
• 156.25 MHz for 10.3125 Gb/s• 173.4375 MHz for 11.1 Gb/s
X-Ref Target - Figure 4
Figure 4: Jitter Test Results for 10.3125 Gb/s
0
10
8
6
4
2
12
14
16
18
20
0.15
0.17
0.19
0.21
0.23
0.25
0.27
TJ (BER=1E-12)
0.29
0.16
0.18
0.20
0.22
0.24
0.26
0.28
0.30
0.31
0.32
0.33
0.34
0.35
RPT136_04_040911TJ (UI)
Num
ber
of D
ata
Poi
nts
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Transmitter Output Jitter
Table 7 shows the maximum transmitter output jitter test result with PRBS patterns and a BER of 10-12.
Figure 5 shows the transmitter output jitter test results at 11.1 Gb/s with a PRBS31 pattern and a BER of 10–12.
Note for Figure 5:
1. 11.1 Gb/s, PRBS31, BER = 10–12.
Table 8 shows the maximum transmitter output jitter test result with PRBS patterns and a BER of 10–12.
Table 7: Transmitter Output Jitter Test Results for 10.3125 Gb/s
Parameter Pattern BERTJ
(UI p-p) (1)RJ
(fs RMS)DDJ
(UI p-p)DDPWS(UI p-p)
UJ(UI RMS)
Maximum Transmitter Output Jitter
PRBS31 10–12 0.251 565 N/A N/A N/A
PRBS9 10–12 N/A N/A 0.095 0.0285 0.0077
Notes: 1. Peak-to-peak.
X-Ref Target - Figure 5
Figure 5: Jitter Test Results for 11.1 Gb/s
Table 8: Transmitter Output Jitter Test Results for 11.1 Gb/s
Parameter Pattern BERTJ
(UI p-p)(1)RJ
(fs RMS)DDJ
(UI p-p)DDPWS(UI p-p)
UJ(UI RMS)
Maximum Transmitter Output Jitter
PRBS31 10–12 0.234 516 N/A N/A N/A
PRBS9 10–12 N/A N/A 0.0915 0.0146 0.0102
Notes: 1. Peak-to-peak.
0
10
8
6
4
2
12
14
16
18
20
0.15
0.17
0.19
0.21
0.23
0.25
0.27
TJ (BER=1E-12)
0.29
0.16
0.18
0.20
0.22
0.24
0.26
0.28
0.30
0.31
0.32
0.33
0.34
0.35
RPT136_05_040911
TJ (UI)
Num
ber
of D
ata
Poi
nts
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Transmitter Output Differential Amplitudes
Transmitter Output Differential Amplitudes
Test MethodologySFF-8431 defines the transmitter output differential amplitude to be between 190 mV and 700 mV. The transmitter output differential amplitudes are measured using the same test setup as in Transmitter Output Jitter, page 11. Table 9 defines the test setup and conditions.
Test ResultsTransmitter output differential amplitude test results are shown in Table 10.
Table 9: Output Differential Amplitude Test Setup and Conditions
Parameter Value
Measurement Instrument Agilent 86100C DCA-J/DCA-X wideband oscilloscope with Agilent 86108A precision waveform analyzer plug-in module
TX Coupling AC coupled using DC blocks
Voltage VMIN, VMAX
Temperature T–40, T0, T100
Pattern Five 1s and five 0s clock pattern (...11000001111100...) generated internally in the fabric of the FPGA
Load Board ML627 characterization platform, Revision B(FF1155)
TX Amplitude/Post-Emphasis
GTH attributes:
• TX_CFG0_LANE<n>[6:3] = 4'b0111 • TX_PREEMPH_LANE<n>[7:4] is set to 4'b1010 • TX_PREEMPH_LANE<n>[3:0] is set to 4'b0001
REFCLK Sourced from Agilent N4903A:
• 156.25 MHz for 10.3125 Gb/s• 173.4375 MHz for 11.1 Gb/s
Table 10: Transmitter Output Differential Amplitude Test Results
Parameters Min Max Units
Differential Amplitude at 10.3125 Gb/s 410 525 mV
Differential Amplitude at 11.1 Gb/s 404 515 mV
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Transmitter Output Rise and Fall Times
Transmitter Output Rise and Fall Times
Test MethodologySFF-8431 defines the minimum transmitter output rise and fall times as 24 ps. Transmitter output rise and fall times are measured using the same test setup as in Transmitter Output Jitter, page 11. Table 11 defines the test setup and conditions.
Test ResultsThe transmitter output rise and fall time test results are shown in Table 12.
Table 11: Output Rise and Fall Time Test Setup and Conditions
Parameter Value
Measurement Instrument Agilent 86100C DCA-J/DCA-X wideband oscilloscope with Agilent 86108A precision waveform analyzer plug-in module
TX Coupling AC coupled using DC blocks
Voltage VMIN, VMAX
Temperature T–40, T0, T100
Pattern Five 1s and five 0s clock pattern (...11000001111100...) generated internally in the fabric of the FPGA
Load Board ML627 characterization platform, Revision B(FF1155)
TX Amplitude/Post-Emphasis
GTH attributes:
• TX_CFG0_LANE<n>[6:3] = 4'b0111 • TX_PREEMPH_LANE<n>[7:4] is set to 4'b1010 • TX_PREEMPH_LANE<n>[3:0] is set to 4'b0001
REFCLK Sourced from Agilent N4903A:
• 156.25 MHz for 10.3125 Gb/s• 173.4375 MHz for 11.1 Gb/s
Table 12: Transmitter Output Rise and Fall Time Test Results
ParametersRise Time
(Min)Fall Time
(Min)Units
Differential Amplitude at 10.3125 Gb/s 34.5 33.2 ps
Differential Amplitude at 11.1 Gb/s 33.9 33.0 ps
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Transmitter Differential and Common Mode Output Return Loss
Transmitter Differential and Common Mode Output Return Loss
Test MethodologySFF-8431 defines the differential output return loss measurement as –12 dB or better between 10 MHz and 2.8 GHz. The differential output return loss measurement between 2.8 GHz and 11.1 GHz is defined by the equation of –8.15 + 13.33log10(f/5.5) where f is frequency in GHz. Differential return loss includes contributions from on-chip circuitry, chip packaging, and any off-chip components related to the driver. This output impedance requirement applies to all valid output levels. The reference impedance for differential return loss measurements is 100.
The transmit common mode output return loss measurement is defined as –9 dB or better between 100 MHz and 4.74 GHz. The common mode output return loss measurement between 4.74 GHz and 11.1 GHz is defined by the equation of –8.15 + 13.33log10(f/5.5), where f is frequency in GHz.
The vector network analyzer (VNA) interfaces to the host PC through the GPIB. After the measurement parameters are set, calibration begins. Four cables are included in the calibration process. VNA measurements are independent of voltage and are accurate up to 16 GHz. A digital multimeter (DVM) confirms the differential resistance is 100 before the measurement.
The measurement is taken with ~1 to 4 inches of channel length between the TXP/TXN FPGA pins and the SMA connectors on the ML627 characterization platform. Table 13 defines the test setup and conditions.
Table 13: Differential and Common Mode Output Return Loss Test Setup and Conditions
Parameter Value
Measurement Instrument HP8720ES vector network analyzer
TX Coupling/Termination Differential, DC coupled into 50 to GND
Voltage Typical voltage
Temperature Room temperature
Frequency Sweep 50 MHz to 16 GHz (10 MHz steps)
Load Board ML627 characterization platform, Revision B(FF1155)
REFCLK Not available
Source Power 0 dBm
Averaging Calibration 1
Intermediate Frequency (IF) 100 Hz
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Transmitter Differential and Common Mode Output Return Loss
Figure 6 shows the setup for the return loss measurement. X-Ref Target - Figure 6
Figure 6: Return Loss Test Setup Block Diagram
34401A
FF1155
ML627
20 GHz
2 ft Green Cable
RX-Pair
TX-Pair
1
2
3
4
VectorNetworkAnalyzer
PCChipScope
GPIBUSB Serial
E2
E1
DVM
ACE
PROG
1VVCCINT
2.5VVCCO 2.5VVCCAUX
GND
DONE
INIT
RX0
RX1116TX1
120TX1 RX1
124TX1 RX1
124TX0 RX0
120RX0 TX0
RX0 TX0122
TX1 RX1122
RX0 TX0126
RX1 TX1126
DIFF
RX0112TX0
RX1112TX1
RX1114TX1
RX0118TX0
50MHz
116 TX0TX1
OFF
Plug
ON5V5VDCSwitch
118 RX1
RX0 114 TX0
122
X0Y1
126
X0Y0
118
X0Y2
114
X0Y3
112
X0Y4
116
X0Y5
120
X0Y6
124
X0Y7
PC4
GP
IB
GP
IBI
V+com
RPT136_06_051011
+
+
+
+
–
DIFF
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Transmitter Differential and Common Mode Output Return Loss
Test ResultsFigure 7 shows the transmitter differential output return loss measurement without de-embedding the channel. X-Ref Target - Figure 7
Figure 7: Transmitter Differential Output Return Loss Measurement
TX[SDD22] versus Frequency
Frequency (GHz)
0.0
0.0
-5.0
-15.0
-25.0
-10.0
-20.0
-30.00.1 1.0 10.0 100.0
RPT136_07_050411
Channel 0
Channel 1
Channel 2
Channel 3
SFP+ SDD22
Pow
er <
dB>
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Transmitter Differential and Common Mode Output Return Loss
Figure 8 shows the transmitter common mode output return loss measurement without de-embedding the channel. X-Ref Target - Figure 8
Figure 8: Transmitter Common Mode Output Return Loss Measurement
Pow
er <
dB>
Frequency (GHz)
TX [SCC22] versus Frequency
Channel 0
Channel 1
Channel 2
Channel 3
SFP+ SCC22
-30.0
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
0.0
0.1
1.0
10.0
100.
0
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Receiver Input Jitter Tolerance
Receiver Input Jitter Tolerance
Test MethodologyReceiver input jitter tolerance is measured using the test setup shown in Figure 9. The J-BERT pattern generator generates a PRBS31 pattern. Random jitter (RJ) and bounded uncorrelated jitter (BUJ) are injected to meet the target value as per specification requirements for SFP+. DJ in the form of ISI is added with 10.75 x 13 inches of board trace (6.75 x 9 inches of which are from a BERTScope ISI test board). Sinusoidal jitter (SJ) is swept from 40 kHz to 40 MHz. The GTH transceiver under test recovers the data and transmits the pattern back to the error detector input of the J-BERT, where bit errors are measured. The test is performed with a +200 and –200 PPM offset between the J-BERT data generator and the reference clock provided to the GTH transceiver under test.
X-Ref Target - Figure 9
Figure 9: Receiver Jitter Tolerance Setup Block Diagram
PRBS & Clock Option
Display
Miscellaneous Buttons forPattern Generator and
Error Detector
Virtex-6HX380T
FFG 1155
AC Power/GPIB/RS-232/ Chassis
Ground Inputs
Keyboard andMiscellaneous Buttons
Pattern Generator
J20 - Interference Channel
Error Detector
Time Base REFCLKOutputs
Trigger Sub ClkAUXIN
ERRORADD OUT OUT OUT OUT
Agilent J-BERT N4903B – 12.5 Gb/s Legend
Stanford Research SystemsCG635 – 2.05 GHz SynthesizedClock Generator
ML627 Rev B Virtex-6 HX380T Board
AutoAlign
PatternSetup
PG EDSetup
Jitter
Analysis/Results
Clk Data
Data
10 MHz Ref Out
CLKIN OUT OUT OUT OUT
DELAYCTRL IN
ERROUT
TRIGOUT CLK
INAUXOUT IN IN
GATEIN
(TX PLL)
(RX PLL)
PRBS PRBSCLK CLK
10 MHz In 10 MHz Out
Quad 1Channel 1TXP TXN
RXP RXN
Quad 2Channel 1TXP TXN
RXP RXN
Quad 1Refclk
On-boardPowerModule
CLKN
CLKP
Quad 2Refclk
CLKN
CLKP
P1
BERTScope ISI Test Board
6.75 / 9 Inches of FR4
P1 P2 P2
SMA Matched Pair Cables forGTX ReceiverSMA Matched Pair Cables forGTX TransmitterSMA Matched Pair Cables forGTX ClocksCable for 10 MHz Reference ClockCable for Clock betweenJ-BERT Pattern Generator and Error Detector
DC Blocks
50 Ohm Termination
RPT136_09_050311
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Receiver Input Jitter Tolerance
Figure 10 shows a scope capture of the jitter injected to the GTH transceiver under test for 10.3125 Gb/s SFP+ testing. In addition to J2 and DDPWS, SJ is applied during the test.
Note for Figure 10:
1. PRBS31 is used for the actual measurement.
X-Ref Target - Figure 10
Figure 10: 10.3125 Gb/s—Stressed Eye Jitter Tolerance Setup using PRBS15 Data Pattern
RPT136_10_040911
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Receiver Input Jitter Tolerance
Figure 11 shows a scope capture of the stressed eye input to the GTH transceiver under test for 10.3125 Gb/s SFP+ testing.
Note for Figure 11:
1. PRBS31 is used for the actual measurement.
X-Ref Target - Figure 11
Figure 11: 10.3125 Gb/s—Stressed Eye Jitter Tolerance with SFP+ Eye Mask Using PRBS15 Data Pattern
RPT136_11_040911
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Receiver Input Jitter Tolerance
Figure 12 shows a scope capture of the jitter injected to the GTH transceiver under test for 11.1 Gb/s SFP+ testing. In addition to J2 and DDPWS, SJ is applied during the test.
Note for Figure 12:
1. PRBS31 is used for the actual measurement.
X-Ref Target - Figure 12
Figure 12: 11.1 Gb/s—Stressed Eye Jitter Tolerance Setup using PRBS15 Data Pattern
RPT136_12_040911
Virtex-6 FPGA GTH Transceivers SFP+ Electrical www.xilinx.com 23RPT136 (v1.0) June 10, 2011
Receiver Input Jitter Tolerance
Figure 13 shows a scope capture of the stressed eye input to the GTH transceiver under test for 11.1 Gb/s SFP+ testing.
Note for Figure 13:
1. PRBS31 is used for the actual measurement.
Table 14 defines the test setup and conditions for the receiver jitter tolerance.
X-Ref Target - Figure 13
Figure 13: 11.1 Gb/s - Stressed Eye Jitter Tolerance with SFP+ Eye Mask using PRBS15 Data Pattern
RPT136_13_040911
Table 14: Receiver Jitter Tolerance Test Setup and Conditions
Parameter Value
Measurement Instrument Agilent J-BERT N4903B
RX Coupling AC coupled using DC blocks
Voltage VMIN, VMAX
Temperature T–40, T0, T100
Pattern PRBS31
24 www.xilinx.com Virtex-6 FPGA GTH Transceivers SFP+ ElectricalRPT136 (v1.0) June 10, 2011
Receiver Input Jitter Tolerance
Injected Jitter SFP+ at 10.3125 Gb/s:
• TJ = 0.720 UI (p-p) (1)
• J2 = 0.410 UI (p-p) • DDPWS = 0.350 UI (p-p) • SJ = Tested to failure; Frequency sweep = {40 kHz–40 MHz}
SFP+ at 11.1 Gb/s:
• TJ = 0.720 UI (p-p) • J2 = 0.420 UI (p-p)• DDPWS = 0.330 UI (p-p)• SJ = Tested to failure; Frequency sweep = {40 kHz–40 MHz}
J-Bert Output Amplitude Setting
10.3125 Gb/s with 9 inches external FR4:
• 960 mV (p-p differential)
11.1 Gb/s with 6.75 inches external FR4:
• 960 mV (p-p differential)
BER 10–12 (measured at 10–9, extrapolated to 10–12)
Load Board ML627 characterization platform, Revision B(FF1155)
Attributes GTH transceiver attributes for 10.3125 Gb/s:(2)
• RX_CTLE_CTRL = 16'h00EF • RX_AGC_CTRL = 16'h0000 • RX_AEQ_VAL0 = 16'h03C0 • RX_AEQ_VAL1 = 16'h0000
GTH transceiver attributes for 11.1 Gb/s:(3)
• RX_CTLE_CTRL = 16'h00CF • RX_AGC_CTRL = 16'h0000 • RX_AEQ_VAL0 = 16'h03C0 • RX_AEQ_VAL1 = 16'h0000
REFCLK Sourced from Agilent J-BERT N4903B:
• 156.25 MHz for 10.3125 Gb/s• 173.4375 MHz for 11.1 Gb/s
Sourced from CG635 Stanford Research synthesized clock generator:
• 156.25 MHz ±200 ppm offset for 10.3125 Gb/s• 173.4375 MHz ±200 ppm offset for 11.1 Gb/s
Notes: 1. Peak-to-peak.2. AGC is set in AUTO mode. DFE is set in AUTO mode. CTLE is set to a decimal value of 14.3. AGC is set in AUTO mode. DFE is set in AUTO mode. CTLE is set to a decimal value of 12.
Table 14: Receiver Jitter Tolerance Test Setup and Conditions (Cont’d)
Parameter Value
Virtex-6 FPGA GTH Transceivers SFP+ Electrical www.xilinx.com 25RPT136 (v1.0) June 10, 2011
Receiver Input Jitter Tolerance
Test ResultsFigure 14 shows the receiver jitter tolerance SJ sweep results for SFP+ at 10.3125 Gb/s. SJ is applied in addition to specified jitter components as defined in Table 14, page 24.
Note for Figure 14:
1. PRBS31, BER = 10–12.
Figure 15 shows the SJ tolerance at SJ frequency of 40 MHz for SFP+ at 10.3125 Gb/s. SJ is applied in addition to specified jitter components as defined in Table 14, page 24.
X-Ref Target - Figure 14
Figure 14: Receiver Jitter Tolerance SJ Sweep Test Results at 10.3125 Gb/s
X-Ref Target - Figure 15
Figure 15: Receiver Sinusoidal Jitter Tolerance at 40 MHz Test Results
40000 400000 4000000 40000000
Am
plitu
de (
UI)
Frequency (Hz)
0.01
0.1
1
10
100
1000
RPT136_14_040911
0.03
0.05
0.07
0.09
0.11
0.13
0.15
0.17
0.19
0.21
0.23
0.25
0.27
0.29
0.31
Num
ber
of D
atap
oint
s
SJ at 40Mhz (UI)
SJ tolerance at SJ Freq = 40Mhz
0
2
4
6
8
10
12
14
16
18
20
RPT136_15_040911
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Receiver Input Jitter Tolerance
Note for Figure 15:
1. PRBS31, BER = 10–12.
Table 15 shows the minimum receiver SJ tolerance at 40 MHz for SFP+. SJ is applied in addition to specified jitter components as defined in Table 14, page 24.
Figure 16 shows the receiver jitter tolerance SJ sweep results for SFP+ at 11.1 Gb/s. SJ is applied in addition to specified jitter components as defined in Table 14, page 24.
Note for Figure 16:
1. PRBS31, BER = 10–12.
Table 15: Receiver Jitter Tolerance Test Results
Parameter Test Condition BERMin SJ
ToleranceUnits
Receiver Jitter Tolerance at 10.3125 Gb/s
SJ = 40 MHz 10–12 0.064 UI
X-Ref Target - Figure 16
Figure 16: SJ Sweep Test Results at 11.1 Gb/s
40000 400000 4000000 40000000
Am
plitu
de (
UI)
Frequency (Hz)
0.01
0.1
1
10
100
1000
RPT136_16_040911
Virtex-6 FPGA GTH Transceivers SFP+ Electrical www.xilinx.com 27RPT136 (v1.0) June 10, 2011
Receiver Input Jitter Tolerance
Figure 17 shows the SJ at 40 MHz for SFP+ at 11.1 Gb/s. SJ is applied in addition to specified jitter components as defined in Table 14, page 24.
Note for Figure 17:
1. PRBS31, BER = 10–12.
Table 16 shows the minimum receiver SJ tolerance for 40 MHz for SFP+. SJ is applied in addition to specified jitter components as defined in Table 15, page 27.
X-Ref Target - Figure 17
Figure 17: Receiver Sinusoidal Jitter Tolerance at 40 MHz Test Results
Table 16: Receiver Jitter Tolerance Test Results
Parameter Test Condition BERMin SJ
ToleranceUnits
Receiver Jitter Tolerance at 11.1 Gb/s SJ = 40 MHz 10–12 0.064 UI
0.03
0.05
0.07
0.09
0.11
0.13
0.15
0.17
0.19
0.21
0.23
0.25
0.27
0.29
0.31
Num
ber
of D
atap
oint
s
SJ at 40Mhz (UI)
SJ tolerance at SJ Freq = 40Mhz
0
2
4
6
8
10
12
14
16
18
20
RPT136_17_040911
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Receiver Differential and Common Mode Input Return Loss
Receiver Differential and Common Mode Input Return Loss
Test MethodologyReceiver input differential and common mode return loss specification and setup are the same as in Transmitter Differential and Common Mode Output Return Loss, page 16. The measurement is taken with ~1 to 4 inches of channel length between the RXP/RXN FPGA pins and the SMA connectors on the ML627 characterization platform. Table 17 defines the test setup and conditions.
Table 17: Receiver Differential and Common Mode Input Return Loss Test Setup and Conditions
Parameter Value
Measurement Instrument HP8720ES vector network analyzer
RX Configuration/Amplitude RX is configured for 100 differential termination (center tap to GND), and AC coupled using both internal and external capacitors.
Voltage Typical voltage
Temperature Room temperature
Frequency Sweep 50 MHz to 16 GHz (10 MHz steps)
Test Fixture ML627 characterization platform, Revision B(FF1155)
REFCLK Not available
Source Power 0 dBm
Averaging Calibration 1
Intermediate Frequency (IF) 100 Hz
Virtex-6 FPGA GTH Transceivers SFP+ Electrical www.xilinx.com 29RPT136 (v1.0) June 10, 2011
Receiver Differential and Common Mode Input Return Loss
Test ResultsFigure 18 shows the receiver differential input return loss measurement without de-embedding of the channel. X-Ref Target - Figure 18
Figure 18: Receiver Differential Input Return Loss Measurement
Pow
er <
dB>
Frequency (GHz)
RX [SDD11] versus Frequency
Channel 0
Channel 1
Channel 2
Channel 3
SFP+ SDD11
0.0
0.1
1.0
10.0
100.
0
-30.0
-25.0
-20.0
-15.0
-10.0
RPT136_18_040911
-5.0
0.0
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Receiver Differential and Common Mode Input Return Loss
Figure 19 shows the receiver common mode input return loss measurement without de-embedding of the channel. X-Ref Target - Figure 19
Figure 19: Receiver Common Mode Input Return Loss Measurement
Pow
er <
dB>
Frequency (GHz)
RX [SCC11] versus Frequency
Channel 0
Channel 1
Channel 2
Channel 3
-30
-25
-20
-15
-10
-5
0
0.01 0.1 1 10 100
RPT136_19_040911
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