Xilinx ISE 6.2.02i – Tutorial - Brigham Young …emp.byui.edu/FisherR/Downloads/Xilinx_ISE6.2.02i_tut.pdf · This tutorial provides a streamlined introduction to the Xilinx Integrated

Department of Electrical and Computer Engineering University of Colorado at Colorado Springs

Tutorial Notes ISE 6.2.02i - 1

"Engineering for the Future"

Xilinx ISE 6.2.02i – Tutorial

Michael D. Ciletti [email protected]

rev 04-06-2005

Outline of Contents Topic Page 1. Getting Started 2 2. Xilinx ISE Design Project 4

2.1. Option #1: Adding an Existing Source Code File 8 2.2. Option #2: Creating a New Source Code File 14

3. Project Navigator – ISE Design Flow 20

3.1. Add Existing Source 22 3.2. Create New Source 22 3.3. Design Entry Utilities 22 3.4. User constraints 22 3.5. Synthesize – XST 23

3.5.1. Check syntax 23 3.5.2. View RTL Schematic 24 3.5.3. View Synthesis Report 25

3.6. Implement Design 25 3.6.1. Place & Route Report 26 3.6.2. Pad Report 26 3.6.3. Static Timing Analysis 26 3.6.4. Floorplanning – Placement 26

4. Generate Programming File 30 Appendix A: Synthesis Report 31 Appendix B: Mapping Report 39 Appendix C: Place & Route Report 44 Appendix D: Pad Report 47 Appendix E: Post-Route Text-Based Timing Analysis Report 55 Appendix F: Programming File Generation Report 57 Note: This tutorial has been developed for use by the Department of Electrical and Computer Engineering at the University of Colorado at Colorado Springs. Other tutorials are available from Xilinx at http:// support.xilinx.com/support/techsup/index.htm



"Engineering for the Future" Introduction This tutorial provides a streamlined introduction to the Xilinx Integrated Software Environment (ISE) for modeling and synthesizing designs for implementation in a Xilinx field programmable gate array (FPGA). As a work in progress, the tutorial will be expanded and improved in the future – please report any errors and/or suggestions for improvement to Dr. Ciletti. Additional Xilinx documentation can be downloaded from www.xilinx.com. Online documentation is located at http://www.support.xilinx.com. Also see the Xilinx University Resource Center located at http://xup.msu.edu. Prototyping boards are available from www.digilent.us. 1. GETTING STARTED Before starting your work, create a folder (e.g. My_Xilinx_Projects) that will be used as a repository for files created by the ISE tool. 1 Within the folder create a subfolder bearing the name of the given project, e.g., ALU_machine_4_bit. It is recommended that you locate the project within your file structure on the network - not within the program files folder. Do not leave files on the lab machines. Launch the Xilinx ISE 6.2 tool with the shortcut icon shown in Fig 1. This action will activate Project Navigator and display the window shown in Fig. 2.

Figure 1. Xilinx ISE: desktop icon.

1 The name of a file or folder must not contain a space.

http://www.support.xilinx.com/

http://xup.msu.edu/




Figure 2. Xilinx ISE: Project Navigator window before projects are defined.



"Engineering for the Future" 2. XILINX ISE DESIGN PROJECT

The files associated with a design are referred to as a project.

• At the menu bar, click on File, and select New Project ... from the drop-down menu. The New Project dialogue window will appear (see Figure 3) displaying fields for entering the name and location of the project.

• Enter the name of the project and use the browser button to open the ISE browser

window, then navigate to the location of the project folder (e.g., C:\My_Xilinx_Projects\ALU_machine_4_bit), and click OK.

• In the New Project dialogue window select the type (HDL) of the top-level module for

the project, then click Next >.

• The New Project dialogue window will now display fields for selecting the device and design flow for the project. Anticipating the Digilent D2 board hosting the Spartan II xc2s200-5pq208 device, enter the information shown in Figure 4, then click Next >.

• The New Project dialogue window will be configured to Create a New Source, as shown

in Figure 5. At this point in the design flow there are two options for associating Verilog source code with the project. The first option (Click Next >) adds an existing Verilog source code file to the project; the second (Click New Source ...) partially creates the code for a new source file by defining a module name and declaring the ports. The remaining definition of the module can be added later.




Figure 3. Xilinx ISE: New Project dialogue window for naming and locating a project.




Figure 4. Xilinx ISE: New Project dialogue window for selecting device and design flow.




Figure 5. Xilinx ISE: New Project dialogue window for source file selection.



"Engineering for the Future" 2.1 Option #1: Adding an Existing Source Code File

Use this option to add an existing Verilog source code file2 to a project. The file can be copied to the project folder, or it can be referenced from another location.

• In the New Project window, click Next > and observe that the dialogue banner is changed to Add Existing Sources3, as shown in Figure 6.

• Click the Add Source ... button to open the Add Existing Sources browser window.

• Using the ISE browser, select the source code file to be added to the project (see

Figure 8).

• If the suffix (i.e., filename extension) is ambiguous the tool will display the Choose Source Type dialogue window shown in Figure 9. Select Verilog Design File and click OK.

• The above actions will display the name and type of the file in the Add Existing

Sources dialogue window (see Figure 10).

Note: The window includes a field for copying the source file into the project folder, rather than using the file that was selected. Be aware that editing the copied file does not edit the original file. This process of adding files can be repeated. Each file will be listed in the dialogue window.

• After adding all of the project files to the project, click Next > to display the New

Project Information shown in Figure 11.

• Click Finish to complete the creation of the project.4 This action creates the project and displays the Project Navigator (Figure 12) with the design hierarchy i.e., Source in the Project,5 and the processes that can be executed.

2 Do not include the test bench in the file. This tutorial will not discuss ISE 6.2.02i support for simulation. 3 Do not click the New Source button; it is used with the second option. 4 Note that a project is not created until this step is executed. 5 If this window is not displayed, it can be selected from the drop-down menu activated by the View command on the toolbar.




Figure 6. Xilinx ISE: "New Project" dialogue window for adding existing source code files to a project.

Figure 7. Xilinx ISE: New Project browser window for adding existing source code




Figure 8. Xilinx ISE: New Project browser window displaying a source file to be added to a project..

Figure 9. Xilinx ISE: New Project dialogue window for designating the type of the included file.




Figure 10. Xilinx ISE: New Project dialogue window displaying a source file that has been added to the project.




Figure 11. Xilinx ISE: New Project window displaying project information.




Figure 12. Xilinx ISE: Project Navigator displayed after adding an existing source code file to the project.




2.2 Option #2: Creating a New Source Code File

Use this option to create a source file with the built-in text editor, and include the file in the project.

• In the Create a New Source dialogue window (see Figure 13) click the New Source... button to display the browser window showing the options in Figure 14. These options specify the type, name, and location of the file that will be created with the built-in editor.

• Click on Verilog Module.

• Provide the name of the source file to be created (e.g., ALU_Option_2, and click the browser

button (...) to launch the Browse for Folder window. Then select the location where the file is to be saved after it is created.

• Using the browser, navigate to the location where the created file is to be saved, then click OK.

• The New Source dialogue window now shows the name and location of the file to be created.

Click Next > to display the Define Verilog Source dialogue window.

• Enter the port names and direction (mode), and the indices of any busses, as shown in Figure 15.

• Click Next > to display the New Source Information window (Figure 16) summarizing the information entered in the previous steps.

• Click Finish > to return to the New Project (Create a New Source) dialogue window (Figure 17).

It will list the newly created file and its type.6

• Click Next > to return to the New Project (Add Existing Sources) dialogue window.

• Click Next > again to display the New Project Information window (Figure 18).

• Click Finish to display the Project Navigator. This action opens a window listing the source code that was defined in the previous steps and launches the editor for completing the description of the model (Figure 19).

6 Additional files can be created by repeating the previous steps.




Figure 13. Xilinx ISE: New Project dialogue window for creating a new source file.




Figure 14. Xilinx ISE: New Source browser window for declaring the type, providing a name, and specifying the location of a new source file.

Figure 15. Xilinx ISE: Define Verilog Source dialogue window for declaring ports of the top-level module in a new source file.




Figure 16. Xilinx ISE: New Source Information describing the top-level module defined in the new source file.




Figure 17. Xilinx ISE: Listing of new project file created with option #2.

Figure 18. Xilinx ISE: Listing of new project information.




Figure 19. Xilinx ISE: Project Navigator with window displaying the created source code.




3. PROJECT NAVIGATOR - ISE DESIGN FLOW After a project has been created, the Project Navigator menu bar displays the path to the project and the source file. The windows of the Project Navigator display (1) the design modules in the design hierarchy (2) the source file containing each design module and (5) the processes that may be launched in the design flow. The following top-level processes are displayed in the Processes for Source window and constitute the design flow that may be executed on the selected (highlighted) module:

• Add Existing Source • Create New source • Design Entry Utilities • User Constraints • Synthesize – XST • Implement Design • Generate Programming File

Each process may have sub processes. A check mark (√) beside a module name in the listing of Sources in Project (see Figure 20) indicates that the associated source file contains a description of the module (double click on a module to display the associated source code and launch the built-in editor).7 A question mark (?) beside a module name indicates that the location of the source file for the module has not been given (right click on the module name to open a browser window for locating the source file). This situation rises when the source code that was added to the project references a module that is not declared in the files that have already been added to the project. Note: The design flow can be launched incrementally for any selected module and its underlying hierarchy, or on the entire design. In either case, the selected module and its child modules must be free of syntax errors. Incrementally synthesized modules cannot, however, be linked to form a synthesis result for the entire design.

7 If the edited file contains a syntax error the Console Window (at the bottom of the Project Navigator window)will display an error message when the file is saved.




Figure 20. Xilinx ISE: Project Navigator showing project files.




3.1 Add Existing Source Additional source files can be added to a project by double-clicking Add Existing Source command in the displayed Processes for Source window. This action opens the Add Existing Sources browser window (see Figure 7 above). Use the browser to select a file to add to the project. 3.2 Create New source The built-in editor can be used to create and add a new source file to the project. Double-clicking Create New Source command in the displayed Processes for Source window. This action opens the New Source browser window (see Figure 14 above). Use the browser to select a file to add to the project. Proceed as described in Option 2 above. 3.3 Design Entry Utilities The design entry utilities are used to create a schematic symbol for a selected module, view the command line log file, and view the Verilog instantiation template.8 3.4 User Constraints The User Constraints sub process is used to (1) create timing constraints (e.g., clock period), (2) assign package pins to the selected device), (3) create area constraints, and (4) edit the constraints. A User Constraints File (UCF) must be added to the project. An empty UCF is automatically created in the project directory, but it is not automatically added to the project. At the main menu bar, click Project and select Add Source ... from the drop-down menu. Then double-click Assign Package Pins in the User Constraints process of the design flow hierarchy to launch the constraints editor window (see Figure 21). Note that the Design Object List automatically lists the ports of the design (name and mode of each). The package pins of the architecture are color-coded to distinguish their arrangement in banks around the edge of the die, and the reserved/fixed pins are identified. Note: The assignment of pins must be compatible with the designated/fixed pins (e.g., GND) of the selected device and with the external environment of the host board. For example, careful attention must be paid to assigning pins of the Digilent D2 board so that it mates correctly to the I/O board in the DIO2 configuration.9

8 This tutorial does not discuss schematic entry. 9 Download the pin mapping for the DIO2 configuration from the Digilent website: http://digilent.us.




Figure 21 Constraints editor window. 3.5 Synthesize – XST The Synthesize-XST process checks the syntax of the source code, displays an RTL schematic symbol of the design, and generates a synthesis report.10 Click on the expander symbol (+) to view the sub processes of the Synthesize – XST process. The first step in the flow is to verify that the source code satisfies the syntax of the language. If the code has no syntax errors the design flow can then generate an RTL schematic, a step which synthesizes the source code into a description that can be compiled into the targeted FPGA. The synthesis report describes the synthesis process and reports any errors. 3.5.1 Check Syntax After expanding the design flow of the Synthesize – XST process, double-click Check Syntax to launch a syntax checker and determine whether the source code conforms to the Verilog standard syntax. If so, a green check mark will appear beside the process label. Otherwise a red X mark will appear. The status of the syntax check will be reported in the Console window. All syntax errors must be removed before proceeding in the design flow. The Console window will indicate whether the syntax check succeeded, or whether it failed. Do not proceed in the design flow until the entire source code has been provided for the entire design and is free of syntax errors.

10 Modules can be synthesized incrementally, provided that all child modules are defined.



"Engineering for the Future" 3.5.2 View RTL Schematic After all syntax errors have been removed, double-click the View RTL Schematic command. This action converts the entire description of the selected module into an equivalent RTL description11 and generates a schematic symbol. If the synthesis process fails (i.e., non-synthesizable constructs were used), an error message will appear in the Console window. The synthesis report will contain a description of the error. All errors have been removed from the example shown in Figure22.

Figure 22 Top-level RTL schematic symbol generated by ISE 6.2.021.

11 In general, a design may be composed of structural elements (i.e., schematics) and other elements as well as functional descriptions.



"Engineering for the Future" 3.5.3 View Synthesis Report The synthesis report contains information describing the progress and results of synthesis. Use this report to determine how to debug a design that failed to synthesize. To launch the synthesis report generator, double-click the View Synthesis Report command. The progress of the synthesis engine will be reported in the Console window (an example is given in Appendix A). 3.6 Implement Design The Implement Design process creates a hardware implementation from the synthesized Verilog description of the design. The process to implement a design includes the following sub processes:

Translate Map Place & Route

Note: Each sub process is launched by double-clicking an appropriately-named command to generate a report. The Translate command creates an internal database of the design. In general, the description of a design may include a variety of formats (e.g., Verilog models, EDIF netlists, and more). These must all be translated and merged into a single internal netlist in a proprietary format used by the Xilinx tool.

• To launch the translation sub process, double-click the Translation Report command in the design flow.12

The Map command maps the logic of the previously generated generic description into the hardware resources (CLBs and IOBs ) of the FPGA. This step also optimizes the logic, removes unused logic, and performs physical design rule checks. The MAP command also generates a report (see Appendix B) containing warnings and error messages generated during the logic optimization and the mapping of logic to physical resources. It also lists logic that has been removed (e.g., logic having no source or no load), logic that has been added or expanded to optimize speed, and reports the utilization of CLBs, IOBs, flip-flops, and latches. If the selected chip includes global buffers or boundary scan logic they will be included in the report.

• To launch the mapping sub process, double-click the Map Report command. The Place and Route step assigns logic to specific CLBs and IOBs located on the physical die, and routes the interconnection paths. If timing constraints have been specified, they will guide the placement of logic so that the constraints are met by the worst-case timing paths, if possible. The tool can relocate logic to other CLBs and/or select faster interconnect paths from the available resources.13

• To launch the place and route sub process, double-click the Place & Route Report command in the design flow.

12 Xilinx ISE 6.2.02i supports manual floorplanning of the design. We will not consider this feature. 13 We will not consider manual place and route.




Note: The routing of the design will ultimately be constrained by the placement of pins to conform to the host board, but it can be helpful to make a first pass allowing the router to work freely, i.e., unconstrained by pin placement. This will give a best-case timing of the design. If the best-case (unconstrained) timing does not meeting timing specifications, the pin-constrained routing will not improve the situation; a faster part must be used. 3.6.1 Place & Route Report The Place & Route sub process produces a report indicating the quality of the routing, a timing summary (see Appendix C) and any signals that have not been successfully routed. This report is very useful in developing large, complex designs. 3.6.2 Pad Report The Pad Report lists the pins of the target device and indicates their status. If a pin is used the signal attached to it will be identified (see appendix D). 3.6.3 Static Timing Analysis ISE 6.2.02i will perform a static timing analysis of the design and generate a post-route report (see Appendix E).14 3.6.4 Floorplanning – Placement The placement of the design can be displayed and manually edited, as necessary to explore alternative placements and to reduce bottlenecks15 (see Figure 23). The "ratsnest" shown in Figure 24 displays point-point nets to reveal congestion and to identify nets that are routed between physically distant CLBs. The actual routing can also be displayed (see Figure 25).

14 It can also generate a netlist for the Synopsys Primetime static timing analyzer. 15 This tutorial will not consider editing.




Figure 23 Placement of CLBs and IOBs on the die.




Figure 24 Pin-to-pin (ratsnest) display of nets.




Figure 25 Display of routed nets.



"Engineering for the Future" 3.7 Generate Programming File The last major step in the design flow is to create the programming file containing the bit stream that will configure the selected device.

a. Double-click the Generate Programming File command. The progress of the process will be displayed in the Console window, and a report will be generated (see Appendix F). The file containing the bitstream is created in the project directory.16

b. To launch the download process to configure the device, double-click the Configure Device (iMPACT) command. The Configure Devices dialogue window will appear.

c. With the Boundary-Scan Mode selected, click Next > to display the Boundary-Scan Mode Selection dialogue box. With Automatically connect ... selected, click Finish.

d. The Cable Connection Summary and the Boundary-Scan Chain Contents Summary will appear while the system checks for the JTAG cable connecting to the board. The system seems to snag here, reporting (erroneously) that it cannot make the connection. The school-of-hard-knocks work-around is to unplug the board before attempting this step, or cycle the JTAG switch on the board (preferred method). Click OK.

e. iMPACT will display the Assign New Configuration File dialogue box, listing bitstream files. Select the appropriate file.

f. Ignore the warning about the Startup clock and click OK. g. Right-click the device icon and select Program. h. Keep your fingers crossed until the Program Succeeded message appears. i. Press the reset button and watch your machine run.

16 The extension of the file name will be .bit.



"Engineering for the Future" Appendix A: Synthesis Report Release 6.2.02i - xst G.30 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s --> Reading design: ALU_machine_4_bit.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : ALU_machine_4_bit.prj Input Format : mixed Ignore Synthesis Constraint File : NO Verilog Include Directory : ---- Target Parameters Output File Name : ALU_machine_4_bit Output Format : NGC Target Device : xc2s200-5-pq208 ---- Source Options Top Module Name : ALU_machine_4_bit Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes ROM Style : Auto Mux Extraction : YES Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES



"Engineering for the Future" XOR Collapsing : YES Resource Sharing : YES Multiplier Style : lut Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 100 Add Generic Clock Buffer(BUFG) : 4 Register Duplication : YES Equivalent register Removal : YES Slice Packing : YES Pack IO Registers into IOBs : auto ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes Write Timing Constraints : NO Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5 ---- Other Options lso : ALU_machine_4_bit.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES Optimize Instantiated Primitives : NO tristate2logic : No ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling source file "ALU_machine_4_bit.v" Module <ALU_4_bit> compiled Module <Register> compiled Module <ALU_machine_4_bit> compiled Compiling source file "/../../My_Verilog_Models_H/Toggle_Button/Toggle_button.v" Module <Toggle_Button> compiled No errors in compilation Analysis of file <ALU_machine_4_bit.prj> succeeded. ========================================================================= * HDL Analysis * =========================================================================



"Engineering for the Future" Analyzing top module <ALU_machine_4_bit>. Module <ALU_machine_4_bit> is correct for synthesis. Analyzing module <ALU_4_bit>. Module <ALU_4_bit> is correct for synthesis. Analyzing module <Register>. Module <Register> is correct for synthesis. Analyzing module <Toggle_Button>. Module <Toggle_Button> is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit <Toggle_Button>. Related source file is /../../My_Verilog_Models_H/Toggle_Button/Toggle_button.v. Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 7 | | Inputs | 1 | | Outputs | 4 | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset type | synchronous | | Reset State | 0001 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit <Toggle_Button> synthesized. Synthesizing Unit <Register>. Related source file is ALU_machine_4_bit.v. Found 4-bit register for signal <Reg_out>. Summary: inferred 4 D-type flip-flop(s). Unit <Register> synthesized. Synthesizing Unit <ALU_4_bit>. Related source file is ALU_machine_4_bit.v. Found 5-bit 8-to-1 multiplexer for signal <Alu_out>. Found 5-bit adder for signal <$n0002>. Found 4-bit adder carry out for signal <$n0019> created at line 17. Summary: inferred 2 Adder/Subtracter(s). inferred 5 Multiplexer(s). Unit <ALU_4_bit> synthesized.



"Engineering for the Future" Synthesizing Unit <ALU_machine_4_bit>. Related source file is ALU_machine_4_bit.v. Unit <ALU_machine_4_bit> synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Selecting encoding for FSM_0 ... Optimizing FSM <FSM_0> on signal <state> with one-hot encoding. Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Adders/Subtractors : 2 5-bit adder : 1 4-bit adder carry out : 1 # Registers : 5 4-bit register : 1 1-bit register : 4 # Multiplexers : 1 5-bit 8-to-1 multiplexer : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit <ALU_machine_4_bit> ... Optimizing unit <ALU_4_bit> ... Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block ALU_machine_4_bit, actual ratio is 1. FlipFlop M3_state_FFd4 has been replicated 1 time(s) to handle iob=true attribute. ========================================================================= * Final Report * ========================================================================= Final Results



"Engineering for the Future" RTL Top Level Output File Name : ALU_machine_4_bit.ngr Top Level Output File Name : ALU_machine_4_bit Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 18 Macro Statistics : # Registers : 1 # 4-bit register : 1 # Multiplexers : 1 # 5-bit 8-to-1 multiplexer : 1 # Adders/Subtractors : 2 # 4-bit adder carry out : 1 # 5-bit adder : 1 Cell Usage : # BELS : 59 # GND : 1 # LUT2 : 8 # LUT2_L : 1 # LUT3 : 13 # LUT3_L : 2 # LUT4 : 3 # MUXCY : 8 # MUXF5 : 9 # MUXF6 : 5 # VCC : 1 # XORCY : 8 # FlipFlops/Latches : 9 # FDR : 2 # FDRE : 4 # FDRS : 1 # FDSE : 2 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 17 # IBUF : 9 # OBUF : 8 ========================================================================= Device utilization summary: --------------------------- Selected Device : 2s200pq208-5 Number of Slices: 20 out of 2352 0% Number of Slice Flip Flops: 9 out of 4704 0% Number of 4 input LUTs: 27 out of 4704 0% Number of bonded IOBs: 17 out of 144 11% Number of GCLKs: 1 out of 4 25%



"Engineering for the Future" ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 9 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -5 Minimum period: 4.178ns (Maximum Frequency: 239.349MHz) Minimum input arrival time before clock: 4.070ns Maximum output required time after clock: 14.490ns Maximum combinational path delay: 14.222ns Timing Detail: -------------- All values displayed in nanoseconds (ns) ------------------------------------------------------------------------- Timing constraint: Default period analysis for Clock 'clk' Delay: 4.178ns (Levels of Logic = 1) Source: M3_state_FFd2 (FF) Destination: M3_state_FFd2 (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: M3_state_FFd2 to M3_state_FFd2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDRS:C->Q 3 1.292 1.480 M3_state_FFd2 (M3_state_FFd2) LUT3_L:I2->LO 1 0.653 0.000 M3_state_FFd1-In1 (M3_state_FFd1-In) FDR:D 0.753 M3_state_FFd1 ---------------------------------------- Total 4.178ns (2.698ns logic, 1.480ns route) (64.6% logic, 35.4% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Offset: 4.070ns (Levels of Logic = 2) Source: Go (PAD) Destination: M3_state_FFd2 (FF) Destination Clock: clk rising



"Engineering for the Future" Data Path: Go to M3_state_FFd2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 5 0.924 1.740 Go_IBUF (Go_IBUF) LUT3_L:I0->LO 1 0.653 0.000 M3_state_FFd3-In1 (M3_state_FFd3-In) FDR:D 0.753 M3_state_FFd3 ---------------------------------------- Total 4.070ns (2.330ns logic, 1.740ns route) (57.2% logic, 42.8% route) ------------------------------------------------------------------------- Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Offset: 14.490ns (Levels of Logic = 10) Source: M2_Reg_out_0 (FF) Destination: Alu_out<4> (PAD) Source Clock: clk rising Data Path: M2_Reg_out_0 to Alu_out<4> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDRE:C->Q 6 1.292 1.850 M2_Reg_out_0 (M2_Reg_out_0) LUT2:I1->O 1 0.653 0.000 M1_Madd__n0002_inst_lut2_01 (M1_Madd__n0002_inst_lut2_0) MUXCY:S->O 1 0.784 0.000 M1_Madd__n0002_inst_cy_0 (M1_Madd__n0002_inst_cy_0) MUXCY:CI->O 1 0.050 0.000 M1_Madd__n0002_inst_cy_1 (M1_Madd__n0002_inst_cy_1) MUXCY:CI->O 1 0.050 0.000 M1_Madd__n0002_inst_cy_2 (M1_Madd__n0002_inst_cy_2) MUXCY:CI->O 0 0.050 0.000 M1_Madd__n0002_inst_cy_3 (M1_Madd__n0002_inst_cy_3) XORCY:CI->O 1 0.500 1.150 M1_Madd__n0002_inst_sum_4 (M1__n0020<9>) LUT3:I2->O 1 0.653 0.000 M1_Mmux_Alu_out_inst_lut3_161 (M1_Mmux_Alu_out__net28) MUXF5:I0->O 1 0.375 0.000 M1_Mmux_Alu_out_inst_mux_f5_8 (M1_Mmux_Alu_out__net30) MUXF6:I0->O 1 0.376 1.150 M1_Mmux_Alu_out_inst_mux_f6_4 (Alu_out_4_OBUF) OBUF:I->O 5.557 Alu_out_4_OBUF (Alu_out<4>) ---------------------------------------- Total 14.490ns (10.340ns logic, 4.150ns route) (71.4% logic, 28.6% route) ------------------------------------------------------------------------- Timing constraint: Default path analysis Delay: 14.222ns (Levels of Logic = 11) Source: Data<0> (PAD) Destination: Alu_out<4> (PAD) Data Path: Data<0> to Alu_out<4> Gate Net



"Engineering for the Future" Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 7 0.924 1.950 Data_0_IBUF (Data_0_IBUF) LUT2:I0->O 1 0.653 0.000 M1_Madd__n0002_inst_lut2_01 (M1_Madd__n0002_inst_lut2_0) MUXCY:S->O 1 0.784 0.000 M1_Madd__n0002_inst_cy_0 (M1_Madd__n0002_inst_cy_0) MUXCY:CI->O 1 0.050 0.000 M1_Madd__n0002_inst_cy_1 (M1_Madd__n0002_inst_cy_1) MUXCY:CI->O 1 0.050 0.000 M1_Madd__n0002_inst_cy_2 (M1_Madd__n0002_inst_cy_2) MUXCY:CI->O 0 0.050 0.000 M1_Madd__n0002_inst_cy_3 (M1_Madd__n0002_inst_cy_3) XORCY:CI->O 1 0.500 1.150 M1_Madd__n0002_inst_sum_4 (M1__n0020<9>) LUT3:I2->O 1 0.653 0.000 M1_Mmux_Alu_out_inst_lut3_161 (M1_Mmux_Alu_out__net28) MUXF5:I0->O 1 0.375 0.000 M1_Mmux_Alu_out_inst_mux_f5_8 (M1_Mmux_Alu_out__net30) MUXF6:I0->O 1 0.376 1.150 M1_Mmux_Alu_out_inst_mux_f6_4 (Alu_out_4_OBUF) OBUF:I->O 5.557 Alu_out_4_OBUF (Alu_out<4>) ---------------------------------------- Total 14.222ns (9.972ns logic, 4.250ns route) (70.1% logic, 29.9% route) ========================================================================= CPU : 2.44 / 3.13 s | Elapsed : 2.00 / 3.00 s --> Total memory usage is 59016 kilobytes



"Engineering for the Future" Appendix B: Mapping Report Release 6.2.02i Map G.30 Xilinx Mapping Report File for Design 'ALU_machine_4_bit' Design Information ------------------ Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o ALU_machine_4_bit_map.ncd ALU_machine_4_bit.ngd ALU_machine_4_bit.pcf Target Device : x2s200 Target Package : pq208 Target Speed : -5 Mapper Version : spartan2 -- $Revision: 1.16.8.1 $ Mapped Date : Tue Feb 08 15:50:07 2005 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 4,704 1% Number of 4 input LUTs: 27 out of 4,704 1% Logic Distribution: Number of occupied Slices: 20 out of 2,352 1% Number of Slices containing only related logic: 20 out of 20 100% Number of Slices containing unrelated logic: 0 out of 20 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 27 out of 4,704 1% Number of bonded IOBs: 17 out of 140 12% IOB Flip Flops: 5 Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25% Total equivalent gate count for design: 327 Additional JTAG gate count for IOBs: 864 Peak Memory Usage: 61 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely



"Engineering for the Future" utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group Summary Section 10 - Modular Design Summary Section 11 - Timing Report Section 12 - Configuration String Information Section 13 - Additional Device Resource Counts Section 1 - Errors ------------------ Section 2 - Warnings -------------------- Section 3 - Informational ------------------------- INFO:LIT:95 - All of the external outputs in this design are using slew rate limited output drivers. The delay on speed critical outputs can be dramatically reduced by designating them as fast outputs in the schematic. INFO:MapLib:562 - No environment variables are currently set. Section 4 - Removed Logic Summary --------------------------------- 2 block(s) optimized away Section 5 - Removed Logic ------------------------- Optimized Block(s): TYPE BLOCK GND XST_GND VCC XST_VCC To enable printing of redundant blocks removed and signals merged, set the detailed map report option and rerun map. Section 6 - IOB Properties -------------------------- +------------------------------------------------------------------------------------------------------------------------+



"Engineering for the Future" | IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Strength | Rate | | | Delay | +------------------------------------------------------------------------------------------------------------------------+ | clk | GCLKIOB | INPUT | LVTTL | | | | | | | Alu_out<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | Alu_out<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | Alu_out<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | Alu_out<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | Alu_out<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | Data<0> | IOB | INPUT | LVTTL | | | INFF | | IFD | | Data<1> | IOB | INPUT | LVTTL | | | INFF | | IFD | | Data<2> | IOB | INPUT | LVTTL | | | INFF | | IFD | | Data<3> | IOB | INPUT | LVTTL | | | INFF | | IFD | | Go | IOB | INPUT | LVTTL | | | | | | | Led_idle | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | | | Led_rdy | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | Led_wait | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | Opcode<0> | IOB | INPUT | LVTTL | | | | | | | Opcode<1> | IOB | INPUT | LVTTL | | | | | | | Opcode<2> | IOB | INPUT | LVTTL | | | | | | | reset | IOB | INPUT | LVTTL | | | | | | +------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group Summary ------------------------------ No area groups were found in this design.



"Engineering for the Future" Section 10 - Modular Design Summary ----------------------------------- Modular Design not used for this design. Section 11 - Timing Report -------------------------- This design was not run using timing mode. Section 12 - Configuration String Details ----------------------------------------- Use the "-detail" map option to print out Configuration Strings Section 13 - Additional Device Resource Counts ---------------------------------------------- Number of JTAG Gates for IOBs = 18 Number of Equivalent Gates for Design = 327 Number of RPM Macros = 0 Number of Hard Macros = 0 PCI IOBs = 0 PCI LOGICs = 0 CAPTUREs = 0 BSCANs = 0 STARTUPs = 0 DLLs = 0 GCLKIOBs = 1 GCLKs = 1 Block RAMs = 0 TBUFs = 0 Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 6 IOB Latches not driven by LUTs = 0 IOB Latches = 0 IOB Flip Flops not driven by LUTs = 5 IOB Flip Flops = 5 Unbonded IOBs = 0 Bonded IOBs = 17 Shift Registers = 0 Static Shift Registers = 0 Dynamic Shift Registers = 0 16x1 ROMs = 0 16x1 RAMs = 0 32x1 RAMs = 0 Dual Port RAMs = 0 MULTANDs = 0 MUXF5s + MUXF6s = 15 4 input LUTs used as Route-Thrus = 0 4 input LUTs = 27 Slice Latches not driven by LUTs = 0 Slice Latches = 0 Slice Flip Flops not driven by LUTs = 1 Slice Flip Flops = 4 Slices = 20 Number of LUT signals with 4 loads = 0 Number of LUT signals with 3 loads = 0 Number of LUT signals with 2 loads = 7



"Engineering for the Future" Number of LUT signals with 1 load = 20 NGM Average fanout of LUT = 1.26 NGM Maximum fanout of LUT = 2 NGM Average fanin for LUT = 2.7778 Number of LUT symbols = 27 Number of IPAD symbols = 10 Number of IBUF symbols = 9



"Engineering for the Future" Appendix C: Place & Route Report Release 6.2.02i Par G.30 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. EN225-01:: Tue Feb 08 15:52:33 2005 C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 ALU_machine_4_bit_map.ncd ALU_machine_4_bit.ncd ALU_machine_4_bit.pcf Constraints file: ALU_machine_4_bit.pcf Loading device database for application Par from file "ALU_machine_4_bit_map.ncd". "ALU_machine_4_bit" is an NCD, version 2.38, device xc2s200, package pq208, speed -5 Loading device for application Par from file 'v200.nph' in environment C:/Xilinx. Device speed data version: PRODUCTION 1.27 2003-12-13. Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 17 out of 140 12% Number of LOCed External IOBs 0 out of 17 0% Number of SLICEs 20 out of 2352 1% Number of GCLKs 1 out of 4 25% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:989758) REAL time: 0 secs Phase 2.23 Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8



"Engineering for the Future" . Phase 5.8 (Checksum:9967ad) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file ALU_machine_4_bit.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 128 unrouted; REAL time: 0 secs Phase 2: 120 unrouted; REAL time: 0 secs Phase 3: 16 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +----------------------------+----------+--------+------------+-------------+ | Clock Net | Resource | Fanout |Net Skew(ns)|Max Delay(ns)| +----------------------------+----------+--------+------------+-------------+ | clk_BUFGP | Global | 8 | 0.112 | 0.662 | +----------------------------+----------+--------+------------+-------------+ The Delay Summary Report The SCORE FOR THIS DESIGN is: 265 The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for this design is: 1.940 The MAXIMUM PIN DELAY IS: 5.641 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 3.571 Listing Pin Delays by value: (nsec) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 6.00 d >= 6.00 --------- --------- --------- --------- --------- --------- 32 46 17 25 8 0



"Engineering for the Future" Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 0 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage: 51 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file ALU_machine_4_bit.ncd. PAR done.



"Engineering for the Future" Appendix D: Pad Report Release 6.2.02i - Par G.30 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Tue Feb 08 15:52:34 2005 INPUT FILE: ALU_machine_4_bit_map.ncd OUTPUT FILE: ALU_machine_4_bit_pad.txt PART TYPE: xc2s200 SPEED GRADE: -5 PACKAGE: pq208 Pinout by Pin Number: ----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- | Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint| P1 | | |GND | | | | | | | | | | P2 | | |TMS | | | | | | | | | | P3 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P4 | |IOB |IO_VREF_7 |UNUSED | |(0,7)*** | | | | | | | P5 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P6 | |IOB |IO_VREF_7 |UNUSED | |(0,7)*** | | | | | | | P7 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P8 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P9 | |IOB |IO_VREF_7 |UNUSED | |(0,7)*** | | | | | | | P10 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P11 | | |GND | | | | | | | | | | P12 | | |VCCO | | |0 | | | | |na | | P13 | | |VCCINT | | | | | | | |2.5 | | P14 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P15 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P16 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P17 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P18 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P19 | | |GND | | | | | | | | | | P20 | |IOB |IO_VREF_7 |UNUSED | |(0,7)*** | | | | | | |



"Engineering for the Future" P21 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P22 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P23 | |IOB | |UNUSED | |(0,7)*** | | | | | | | P24 | |PCIIOB |IO_IRDY |UNUSED | |(0,7)*** | | | | | | | P25 | | |GND | | | | | | | | | | P26 | | |VCCO | | |0 | | | | |na | | P27 | |PCIIOB |IO_TRDY |UNUSED | |(0,6)*** | | | | | | | P28 | | |VCCINT | | | | | | | |2.5 | | P29 | |IOB | |UNUSED | |(0,6)*** | | | | | | | P30 | |IOB | |UNUSED | |(0,6)*** | | | | | | | P31 | |IOB |IO_VREF_6 |UNUSED | |(0,6)*** | | | | | | | P32 | | |GND | | | | | | | | | | P33 | |IOB | |UNUSED | |(0,6)*** | | | | | | | P34 | |IOB | |UNUSED | |(0,6)*** | | | | | | | P35 | |IOB | |UNUSED | |(0,6)*** | | | | | | | P36 | |IOB | |UNUSED | |(0,6)*** | | | | | | | P37 | |IOB | |UNUSED | |(0,6)*** | | | | | | | P38 | | |VCCINT | | | | | | | |2.5 | | P39 | | |VCCO | | |0 | | | | |na | | P40 | | |GND | | | | | | | | | | P41 | |IOB | |UNUSED | |(0,6)*** | | | | | | | P42 | |IOB |IO_VREF_6 |UNUSED | |(0,6)*** | | | | | | | P43 |Opcode<0> |IOB | |INPUT |LVTTL |(0,6)*** | | | |NONE | | | P44 | |IOB | |UNUSED | |(0,6)*** | | | | | | | P45 |Opcode<1> |IOB |IO_VREF_6 |INPUT |LVTTL |(0,6)*** | | | |NONE | | | P46 |Alu_out<4> |IOB | |OUTPUT |LVTTL |(0,6)*** |12 |SLOW |NONE** | | | | P47 |Alu_out<3> |IOB |IO_VREF_6 |OUTPUT |LVTTL |(0,6)*** |12 |SLOW |NONE** | | | | P48 |Alu_out<1> |IOB | |OUTPUT |LVTTL |(0,6)*** |12 |SLOW |NONE** | | | | P49 |Alu_out<2> |IOB | |OUTPUT |LVTTL |(0,6)*** |12 |SLOW |NONE** | | | | P50 | | |M1 | | | | | | | | | |



"Engineering for the Future" P51 | | |GND | | | | | | | | | | P52 | | |M0 | | | | | | | | | | P53 | | |VCCO | | |0 | | | | |na | | P54 | | |M2 | | | | | | | | | | P55 | | |NC | | | | | | | | | | P56 | | |NC | | | | | | | | | | P57 |Opcode<2> |IOB |IO_VREF_5 |INPUT |LVTTL |(0,5)*** | | | |NONE | | | P58 | |IOB | |UNUSED | |(0,5)*** | | | | | | | P59 | |IOB |IO_VREF_5 |UNUSED | |(0,5)*** | | | | | | | P60 | |IOB | |UNUSED | |(0,5)*** | | | | | | | P61 | |IOB | |UNUSED | |(0,5)*** | | | | | | | P62 | |IOB |IO_VREF_5 |UNUSED | |(0,5)*** | | | | | | | P63 | |IOB | |UNUSED | |(0,5)*** | | | | | | | P64 | | |GND | | | | | | | | | | P65 | | |VCCO | | |0 | | | | |na | | P66 | | |VCCINT | | | | | | | |2.5 | | P67 |Alu_out<0> |IOB | |OUTPUT |LVTTL |(0,5)*** |12 |SLOW |NONE** | | | | P68 | |IOB | |UNUSED | |(0,5)*** | | | | | | | P69 |Data<1> |IOB | |INPUT |LVTTL |(0,5)*** | | | |IFD | | | P70 |Data<0> |IOB | |INPUT |LVTTL |(0,5)*** | | | |IFD | | | P71 |Data<3> |IOB | |INPUT |LVTTL |(0,5)*** | | | |IFD | | | P72 | | |GND | | | | | | | | | | P73 |Data<2> |IOB |IO_VREF_5 |INPUT |LVTTL |(0,5)*** | | | |IFD | | | P74 | |IOB | |UNUSED | |(0,5)*** | | | | | | | P75 | |IOB | |UNUSED | |(0,5)*** | | | | | | | P76 | | |VCCINT | | | | | | | |2.5 | | P77 |clk |GCLKIOB |GCK1 |INPUT |LVTTL |(0,5)*** | | | | | | | P78 | | |VCCO | | |0 | | | | |na | | P79 | | |GND | | | | | | | | | | P80 | |GCLKIOB |GCK0 |UNUSED | |(0,4)*** | | | | | | |



"Engineering for the Future" P81 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P82 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P83 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P84 | |IOB |IO_VREF_4 |UNUSED | |(0,4)*** | | | | | | | P85 | | |GND | | | | | | | | | | P86 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P87 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P88 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P89 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P90 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P91 | | |VCCINT | | | | | | | |2.5 | | P92 | | |VCCO | | |0 | | | | |na | | P93 | | |GND | | | | | | | | | | P94 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P95 | |IOB |IO_VREF_4 |UNUSED | |(0,4)*** | | | | | | | P96 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P97 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P98 | |IOB |IO_VREF_4 |UNUSED | |(0,4)*** | | | | | | | P99 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P100 | |IOB |IO_VREF_4 |UNUSED | |(0,4)*** | | | | | | | P101 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P102 | |IOB | |UNUSED | |(0,4)*** | | | | | | | P103 | | |GND | | | | | | | | | | P104 | | |DONE | | | | | | | | | | P105 | | |VCCO | | |0 | | | | |na | | P106 | | |PROGRAM | | | | | | | | | | P107 | |IOB |IO_INIT |UNUSED | |(0,3)*** | | | | | | | P108 | |IOB |IO_D7 |UNUSED | |(0,3)*** | | | | | | | P109 | |IOB |IO_VREF_3 |UNUSED | |(0,3)*** | | | | | | | P110 | |IOB | |UNUSED | |(0,3)*** | | | | | | |



"Engineering for the Future" P111 | |IOB |IO_VREF_3 |UNUSED | |(0,3)*** | | | | | | | P112 | |IOB | |UNUSED | |(0,3)*** | | | | | | | P113 | |IOB | |UNUSED | |(0,3)*** | | | | | | | P114 | |IOB |IO_VREF_3 |UNUSED | |(0,3)*** | | | | | | | P115 | |IOB |IO_D6 |UNUSED | |(0,3)*** | | | | | | | P116 | | |GND | | | | | | | | | | P117 | | |VCCO | | |0 | | | | |na | | P118 | | |VCCINT | | | | | | | |2.5 | | P119 | |IOB |IO_D5 |UNUSED | |(0,3)*** | | | | | | | P120 | |IOB | |UNUSED | |(0,3)*** | | | | | | | P121 | |IOB | |UNUSED | |(0,3)*** | | | | | | | P122 | |IOB | |UNUSED | |(0,3)*** | | | | | | | P123 | |IOB | |UNUSED | |(0,3)*** | | | | | | | P124 | | |GND | | | | | | | | | | P125 | |IOB |IO_VREF_3 |UNUSED | |(0,3)*** | | | | | | | P126 | |IOB |IO_D4 |UNUSED | |(0,3)*** | | | | | | | P127 | |IOB | |UNUSED | |(0,3)*** | | | | | | | P128 | | |VCCINT | | | | | | | |2.5 | | P129 | |PCIIOB |IO_TRDY |UNUSED | |(0,3)*** | | | | | | | P130 | | |VCCO | | |0 | | | | |na | | P131 | | |GND | | | | | | | | | | P132 | |PCIIOB |IO_IRDY |UNUSED | |(0,2)*** | | | | | | | P133 | |IOB | |UNUSED | |(0,2)*** | | | | | | | P134 | |IOB | |UNUSED | |(0,2)*** | | | | | | | P135 | |IOB |IO_D3 |UNUSED | |(0,2)*** | | | | | | | P136 | |IOB |IO_VREF_2 |UNUSED | |(0,2)*** | | | | | | | P137 | | |GND | | | | | | | | | | P138 | |IOB | |UNUSED | |(0,2)*** | | | | | | | P139 | |IOB | |UNUSED | |(0,2)*** | | | | | | | P140 |Led_rdy |IOB | |OUTPUT |LVTTL |(0,2)*** |12 |SLOW |NONE** | | | |



"Engineering for the Future" P141 | |IOB | |UNUSED | |(0,2)*** | | | | | | | P142 | |IOB |IO_D2 |UNUSED | |(0,2)*** | | | | | | | P143 | | |VCCINT | | | | | | | |2.5 | | P144 | | |VCCO | | |0 | | | | |na | | P145 | | |GND | | | | | | | | | | P146 |reset |IOB |IO_D1 |INPUT |LVTTL |(0,2)*** | | | |NONE | | | P147 |Led_wait |IOB |IO_VREF_2 |OUTPUT |LVTTL |(0,2)*** |12 |SLOW |NONE** | | | | P148 | |IOB | |UNUSED | |(0,2)*** | | | | | | | P149 |Led_idle |IOB | |OUTPUT |LVTTL |(0,2)*** |12 |SLOW |NONE** | | | | P150 |Go |IOB |IO_VREF_2 |INPUT |LVTTL |(0,2)*** | | | |NONE | | | P151 | |IOB | |UNUSED | |(0,2)*** | | | | | | | P152 | |IOB |IO_VREF_2 |UNUSED | |(0,2)*** | | | | | | | P153 | |IOB |IO_DIN_D0 |UNUSED | |(0,2)*** | | | | | | | P154 | |IOB |IO_DOUT_BUSY|UNUSED | |(0,2)*** | | | | | | | P155 | | |CCLK | | | | | | | | | | P156 | | |VCCO | | |0 | | | | |na | | P157 | | |TDO | | | | | | | | | | P158 | | |GND | | | | | | | | | | P159 | | |TDI | | | | | | | | | | P160 | |IOB |IO_CS |UNUSED | |(0,1)*** | | | | | | | P161 | |IOB |IO_WRITE |UNUSED | |(0,1)*** | | | | | | | P162 | |IOB |IO_VREF_1 |UNUSED | |(0,1)*** | | | | | | | P163 | |IOB | |UNUSED | |(0,1)*** | | | | | | | P164 | |IOB |IO_VREF_1 |UNUSED | |(0,1)*** | | | | | | | P165 | |IOB | |UNUSED | |(0,1)*** | | | | | | | P166 | |IOB | |UNUSED | |(0,1)*** | | | | | | | P167 | |IOB |IO_VREF_1 |UNUSED | |(0,1)*** | | | | | | | P168 | |IOB | |UNUSED | |(0,1)*** | | | | | | | P169 | | |GND | | | | | | | | | | P170 | | |VCCO | | |0 | | | | |na | |



"Engineering for the Future" P171 | | |VCCINT | | | | | | | |2.5 | | P172 | |IOB | |UNUSED | |(0,1)*** | | | | | | | P173 | |IOB | |UNUSED | |(0,1)*** | | | | | | | P174 | |IOB | |UNUSED | |(0,1)*** | | | | | | | P175 | |IOB | |UNUSED | |(0,1)*** | | | | | | | P176 | |IOB | |UNUSED | |(0,1)*** | | | | | | | P177 | | |GND | | | | | | | | | | P178 | |IOB |IO_VREF_1 |UNUSED | |(0,1)*** | | | | | | | P179 | |IOB | |UNUSED | |(0,1)*** | | | | | | | P180 | |IOB | |UNUSED | |(0,1)*** | | | | | | | P181 | |IOB | |UNUSED | |(0,1)*** | | | | | | | P182 | |GCLKIOB |GCK2 |UNUSED | |(0,1)*** | | | | | | | P183 | | |GND | | | | | | | | | | P184 | | |VCCO | | |0 | | | | |na | | P185 | |GCLKIOB |GCK3 |UNUSED | |0 | | | | | | | P186 | | |VCCINT | | | | | | | |2.5 | | P187 | |IOB | |UNUSED | |0 | | | | | | | P188 | |IOB | |UNUSED | |0 | | | | | | | P189 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | P190 | | |GND | | | | | | | | | | P191 | |IOB | |UNUSED | |0 | | | | | | | P192 | |IOB | |UNUSED | |0 | | | | | | | P193 | |IOB | |UNUSED | |0 | | | | | | | P194 | |IOB | |UNUSED | |0 | | | | | | | P195 | |IOB | |UNUSED | |0 | | | | | | | P196 | | |VCCINT | | | | | | | |2.5 | | P197 | | |VCCO | | |0 | | | | |na | | P198 | | |GND | | | | | | | | | | P199 | |IOB | |UNUSED | |0 | | | | | | | P200 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | |



"Engineering for the Future" P201 | |IOB | |UNUSED | |0 | | | | | | | P202 | |IOB | |UNUSED | |0 | | | | | | | P203 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | P204 | |IOB | |UNUSED | |0 | | | | | | | P205 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | P206 | |IOB | |UNUSED | |0 | | | | | | | P207 | | |TCK | | | | | | | | | | P208 | | |VCCO | | |0 | | | | |na | | ----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- |----- | * Default value. ** This default Pullup/Pulldown value can be overridden in Bitgen. *** In some smaller packages, the VCCO bank number of a pin may trail the VREF bank number (VCCO,VREF).



"Engineering for the Future" Appendix E: Post-Route Text-Based Timing Analysis Report -------------------------------------------------------------------------------- Release 6.2.02i Trace G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml ALU_machine_4_bit ALU_machine_4_bit.ncd -o ALU_machine_4_bit.twr ALU_machine_4_bit.pcf Design file: ALU_machine_4_bit.ncd Physical constraint file: ALU_machine_4_bit.pcf Device,speed: xc2s200,-5 (PRODUCTION 1.27 2003-12-13) Report level: error report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:2698 - No timing constraints found, doing default enumeration. INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Setup/Hold to clock clk ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ Data<0> | 3.000(R)| 0.000(R)|clk_BUFGP | 0.000| Data<1> | 3.000(R)| 0.000(R)|clk_BUFGP | 0.000| Data<2> | 3.000(R)| 0.000(R)|clk_BUFGP | 0.000| Data<3> | 3.000(R)| 0.000(R)|clk_BUFGP | 0.000| Go | 3.084(R)| 0.452(R)|clk_BUFGP | 0.000| reset | 5.520(R)| -0.042(R)|clk_BUFGP | 0.000| ------------+------------+------------+------------------+--------+ Clock clk to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ Alu_out<0> | 13.523(R)|clk_BUFGP | 0.000| Alu_out<1> | 16.804(R)|clk_BUFGP | 0.000| Alu_out<2> | 16.588(R)|clk_BUFGP | 0.000| Alu_out<3> | 16.503(R)|clk_BUFGP | 0.000| Alu_out<4> | 17.489(R)|clk_BUFGP | 0.000| Led_idle | 7.665(R)|clk_BUFGP | 0.000| Led_rdy | 12.561(R)|clk_BUFGP | 0.000| Led_wait | 12.823(R)|clk_BUFGP | 0.000| ------------+------------+------------------+--------+ Clock to Setup on destination clock clk ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall|



"Engineering for the Future" Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk | 7.473| | | | ---------------+---------+---------+---------+---------+ Pad to Pad ---------------+---------------+---------+ Source Pad |Destination Pad| Delay | ---------------+---------------+---------+ Data<0> |Alu_out<0> | 11.524| Data<0> |Alu_out<1> | 14.680| Data<0> |Alu_out<2> | 14.367| Data<0> |Alu_out<3> | 14.310| Data<0> |Alu_out<4> | 15.077| Data<1> |Alu_out<0> | 10.742| Data<1> |Alu_out<1> | 13.666| Data<1> |Alu_out<2> | 14.164| Data<1> |Alu_out<3> | 14.107| Data<1> |Alu_out<4> | 14.874| Data<2> |Alu_out<0> | 11.351| Data<2> |Alu_out<2> | 13.595| Data<2> |Alu_out<3> | 14.526| Data<2> |Alu_out<4> | 15.292| Data<3> |Alu_out<0> | 11.104| Data<3> |Alu_out<3> | 13.618| Data<3> |Alu_out<4> | 15.217| Opcode<0> |Alu_out<0> | 12.181| Opcode<0> |Alu_out<1> | 13.927| Opcode<0> |Alu_out<2> | 13.498| Opcode<0> |Alu_out<3> | 13.978| Opcode<0> |Alu_out<4> | 13.674| Opcode<1> |Alu_out<0> | 11.751| Opcode<1> |Alu_out<1> | 13.428| Opcode<1> |Alu_out<2> | 12.909| Opcode<1> |Alu_out<3> | 13.359| Opcode<1> |Alu_out<4> | 12.762| Opcode<2> |Alu_out<0> | 10.330| Opcode<2> |Alu_out<1> | 11.971| Opcode<2> |Alu_out<2> | 11.714| Opcode<2> |Alu_out<3> | 12.165| Opcode<2> |Alu_out<4> | 12.231| ---------------+---------------+---------+ Analysis completed Tue Feb 08 15:52:35 2005 -------------------------------------------------------------------------------- Peak Memory Usage: 48 MB



"Engineering for the Future" APPENDIX F: PROGRAMMING FILE GENERATION REPORT Release 6.2.02i - Bitgen G.30 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Loading device database for application Bitgen from file "ALU_machine_4_bit.ncd". "ALU_machine_4_bit" is an NCD, version 2.38, device xc2s200, package pq208, speed -5 Loading device for application Bitgen from file 'v200.nph' in environment C:/Xilinx. Opened constraints file ALU_machine_4_bit.pcf. Wed Feb 16 10:32:54 2005 C:/Xilinx/bin/nt/bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No ALU_machine_4_bit.ncd Summary of Bitgen Options: +----------------------+----------------------+ | Option Name | Current Setting | +----------------------+----------------------+ | Compress | (Not Specified)* | +----------------------+----------------------+ | Readback | (Not Specified)* | +----------------------+----------------------+ | DebugBitstream | No** | +----------------------+----------------------+ | ConfigRate | 4** | +----------------------+----------------------+ | StartupClk | Cclk** | +----------------------+----------------------+ | CclkPin | Pullup** | +----------------------+----------------------+ | DonePin | Pullup** | +----------------------+----------------------+ | M0Pin | Pullup** | +----------------------+----------------------+ | M1Pin | Pullup** | +----------------------+----------------------+ | M2Pin | Pullup** | +----------------------+----------------------+ | ProgPin | Pullup** | +----------------------+----------------------+ | TckPin | Pullup** | +----------------------+----------------------+ | TdiPin | Pullup** | +----------------------+----------------------+ | TdoPin | Pullup | +----------------------+----------------------+ | TmsPin | Pullup** | +----------------------+----------------------+ | UnusedPin | Pulldown** | +----------------------+----------------------+ | GSR_cycle | 6** | +----------------------+----------------------+



"Engineering for the Future" | GWE_cycle | 6** | +----------------------+----------------------+ | GTS_cycle | 5** | +----------------------+----------------------+ | LCK_cycle | NoWait** | +----------------------+----------------------+ | DONE_cycle | 4** | +----------------------+----------------------+ | Persist | No* | +----------------------+----------------------+ | DriveDone | No** | +----------------------+----------------------+ | DonePipe | No** | +----------------------+----------------------+ | Security | None** | +----------------------+----------------------+ | UserID | 0xFFFFFFFF** | +----------------------+----------------------+ | Gclkdel0 | 11111** | +----------------------+----------------------+ | Gclkdel1 | 11111** | +----------------------+----------------------+ | Gclkdel2 | 11111** | +----------------------+----------------------+ | Gclkdel3 | 11111** | +----------------------+----------------------+ | ActiveReconfig | No* | +----------------------+----------------------+ | ActivateGclk | No* | +----------------------+----------------------+ | PartialMask0 | (Not Specified)* | +----------------------+----------------------+ | PartialMask1 | (Not Specified)* | +----------------------+----------------------+ | PartialGclk | (Not Specified)* | +----------------------+----------------------+ | PartialLeft | (Not Specified)* | +----------------------+----------------------+ | PartialRight | (Not Specified)* | +----------------------+----------------------+ | IEEE1532 | No* | +----------------------+----------------------+ | Binary | No** | +----------------------+----------------------+ * Default setting. ** The specified setting matches the default setting. Running DRC. DRC detected 0 errors and 0 warnings. Creating bit map... Saving bit stream in "alu_machine_4_bit.bit". Bitstream generation is complete.

Xilinx ISE 6.2.02i – Tutorial - Brigham Young …emp.byui.edu/FisherR/Downloads/Xilinx_ISE6.2.02i_tut.pdf · This tutorial provides a streamlined introduction to the Xilinx Integrated

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