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UltraLogic 128-Macrocell Flash CPLD
CY7C375i
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600
Document #: 38-03029 Rev. *A Revised May 10, 2004
Features 128 macrocells in eight logic blocks
128 I/O pins
Five dedicated inputs including 4 clock pins
In-System Reprogrammable (ISR) Flash technology
JTAG Interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
fMAX= 125 MHz
tPD= 10 ns
tS= 5.5 ns
tCO= 6.5 ns
Fully PCI compliant
3.3V or 5.0V I/O operation
Available in 160-pin TQFP, CQFP, and PGA packages
Functional Description
The CY7C375i is an In-System Reprogrammable ComplexProgrammable Logic Device (CPLD) and is part of theFLASH370i family of high-density, high-speed CPLDs. Likeall members of the FLASH370i family, the CY7C375i isdesigned to bring the ease of use and high performance of the22V10 to high-density PLDs.
Like all of the UltraLogic FLASH370i devices, the CY7C375iis electrically erasable and In-System Reprogrammable (ISR),which simplifies both design and manufacturing flows therebyreducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and outthrough the SDI and SDO pins. The ISR interface is enabledusing the programming voltage pin (ISREN). Additionally,because of the superior routability of the FLASH370i devices,ISR often allows users to change existing logic designs whilesimultaneously fixing pinout assignments.
Logic Block Diagram
PIM
INPUTMACROCELL
Clock
Inputs
4 4
36
16 16
36
LOGIC
BLOCK 3616 16
36
16 I/Os
36 36
36
16 16
36
16 16
64 64
41INPUT/CLOCK
MACROCELLS
I/O0I/O
15 A
Inputs
LOGICBLOCK
C
LOGICBLOCK
B
LOGICBLOCK
D
LOGIC
BLOCKH
LOGICBLOCK
G
LOGICBLOCK
F
LOGICBLOCK
E
I/O16I/O31
I/O32I/O47
I/O48I/O63
I/O112I/O127
I/O96I/O111
I/O80I/O95
I/O64I/O79
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
Selection Guide
7C375i125 7C375i100 7C375i83 7C375iL83 7C375i66 7C375iL66 Unit
Maximum Propagation Delay[1], tPD 10 12 15 15 20 20 ns
Minimum Set-Up, tS 5.5 6 8 8 10 10 ns
Maximum Clock to Output[1], tCO 6.5 7 8 8 10 10 ns
Typical Supply Current, ICC 125 125 125 75 125 75 mA
Note:1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO= 3.3V
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Pin Configurations
I/O
2
124
3
123
4
122
5
121
6
120
7
119
8
118
9
117
10
116
11
115
12
114
13
113
14
112
15
111
16
110
17
109
18
108
19
107
20
106
21
105
22
104
23
103
24
102
25
101
26
100
27
99
28
98
29
97
30
96
31
95
32
94
33
93
34
92
35
91
36
90
37
89
38
88
39
87
40
86
41
85
43
44
160
45
159
46
158
47
157
48
156
49
155
50
154
51
153
52
152
53
151
54
150
55
149
56
148
57
147
58
146
59
145
60
144
61
143
62
142
63
141
64
65
66
67
68
140
69
139
70
138
71
137
72
136
73
135
74
134
75
133
76
132
77
131
78
130
79
129
80
128
81
127
82
126
TQFPTop View
125
84
83
42
1GND
I/O16I/O17I/O18I/O19
I/O20/SCLK
I/O21I/O22I/O23
I/O24I/O25I/O26
I/O27I/O28I/O29I/O30I/O31
I/O32I/O33I/O34I/O35I/O36I/O37I/O38I/O39
I/O40I/O41I/O42I/O43I/O44I/O45I/O46I/O47
GND
CLK0/I0VCCIOGND
CLK1/I1
GND
GND
48
GND 2
CCIO
GND
GND
VCCIO
I/O
49
I/O
50
I/O
51
I/O
52
I/O
53
I/O
54
I/O
55
I/O
56
I/O
57
I/O
58
I/O
59
I/O
60
I/O
61
I/O
62
I/O
63
I/O
I
V CCINT
V
64
I/O
65
I/O
66
I/O
67
I/O
68
I/O
69
I/O
70
I/O
71
I/O
72
I/O
73
I/O
74
I/O
75
I/O
76
I/O
77
78
I/O
79
I/O C
CIO
V
GNDI/O80
I/O81
I/O82
I/O83
I/O84
I/O85
I/O86I/O87
GND
I/O88
I/O89
I/O90
I/O91
I/O92
I/O93
I/O94
I/O95
I/O96
I/O97
I/O98
I/O99I/O100
I/O101
I/O102
I/O103
GND
GND
CLK2/I3
VCCIO
CLK3/I4
I/O104
I/O105
I/O106
I/O107
I/O108/SDII/O109
I/O110
I/O111
VCCIO
GND
GND
V GND
I/O
GND1
12
CCINT
VCCIO
VCCIO
I/O
113
I/O
114
I/O
115
I/O
116
I/O
117
I/O
118
I/O
119
I/O
120
I/O
121
I/O
122
I/O
123
I/O
124
I/O
125
I/O
126
I/O
127
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
ISR
EN
/SMODE
/SDO
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Pin Configurations(continued)
I/O
2
124
3
123
4
122
5
121
6
120
7
119
8
118
9
117
10
116
11
115
12
114
13
113
14
112
15
111
16
110
17
109
18
108
19
107
20
106
21
105
22
104
23
103
24
102
25
101
26
100
27
99
28
98
29
97
30
96
31
95
32
94
33
93
34
92
35
91
36
90
37
89
38
88
39
87
40
86
41
85
43
44
160
45
159
46
158
47
157
48
156
49
155
50
154
51
153
52
152
53
151
54
150
55
149
56
148
57
147
58
146
59
145
60
144
61
143
62
142
63
141
64
65
66
67
68
140
69
139
70
138
71
137
72
136
73
135
74
134
75
133
76
132
77
131
78
130
79
129
80
128
81
127
82
126
CQFPTop View
125
84
83
42
1GND
I/O16I/O17I/O18I/O19
I/O20/SCLK
I/O21I/O22I/O23
I/O24I/O25I/O26I/O27
I/O28I/O29
I/O30I/O31
I/O32I/O33I/O34I/O35I/O36I/O37I/O38I/O39
I/O40
I/O41I/O42I/O43I/O44I/O45I/O46I/O47
GND
CLK0/I0VCC
GND
CLK1/I1
GND
GND 4
8
GND 2
CC
GND
GND
VCC
I/O
49
I/O
50
I/O
51
I/O
52
I/O
53
I/O
54
I/O
55
I/O
56
I/O
57
I/O
58
I/O
59
I/O
60
I/O
61
I/O
62
I/O
63
I/O
I
V C
C
V
64
I/O
65
I/O
66
I/O
67
I/O
68
I/O
69
I/O
70
I/O
71
I/O
72
I/O
73
I/O
74
I/O
75
I/O
76
I/O
77
78
I/O
79
I/O C
C
V
GNDI/O80
I/O81
I/O82
I/O83
I/O84
I/O85
I/O86
I/O87
GND
I/O88
I/O89
I/O90
I/O91
I/O92
I/O93
I/O94
I/O95
I/O96
I/O97
I/O98
I/O99
I/O100
I/O101
I/O102
I/O103
GND
GND
CLK2/I3
VCC
CLK3/I4
I/O104
I/O105
I/O106
I/O107
I/O108/SDII/O109
I/O110
I/O111
VCC
GND
GND
V GND
I/O
GND1
12
CC
VCC
VCC
I/O
113
I/O
114
I/O
115
I/O
116
I/O
117
I/O
118
I/O
119
I/O
120
I/O
121
I/O
122
I/O
123
I/O
124
I/O
125
I/O
126
I/O
127
I/O
0
I/O1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
ISR
EN
/SMODE
/SDO
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Functional Description
The 128 macrocells in the CY7C375i are divided betweeneight logic blocks. Each logic block includes 16 macrocells, a72 x 86 product term array, and an intelligent product termallocator.
The logic blocks in the FLASH370i architecture are connectedwith an extremely fast and predictable routing resourcetheProgrammable Interconnect Matrix (PIM). The PIM bringsflexibility, routability, speed, and a uniform delay to the inter-connect.
Like all members of the FLASH370i family, the CY7C375i is richin I/O resources. Every macrocell in the device features anassociated I/O pin, resulting in 128 I/O pins on the CY7C375i.In addition, there is one dedicated input and four input/clockpins.
Finally, the CY7C375i features a very simple timing model.Unlike other high-density CPLD architectures, there are nohidden speed delays such as fanout effects, interconnectdelays, or expander delays. Regardless of the number ofresources used or the type of application, the timing param-eters on the CY7C375i remain the same.
Logic Block
The number of logic blocks distinguishes the members of theFLASH370i family. The CY7C375i includes eight logic blocks.Each logic block is constructed of a product term array, aproduct term allocator, and 16 macrocells.
Product Term Array
The product term array in the FLASH370i logic block includes36 inputs from the PIM and outputs 86 product terms to theproduct term allocator. The 36 inputs from the PIM areavailable in both positive and negative polarity, making theoverall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in singlepasses through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resourcethat shifts product terms to macrocells that require them. Anynumber of product terms between 0 and 16 inclusive can beassigned to any of the logic block macrocells (this is calledproduct term steering). Furthermore, product terms can beshared among multiple macrocells. This means that productterms that are common to more than one output can be imple-mented in a single product term. Product term steering and
Pin Configurations(continued)
PGABottom View
1 2 3 4 5 6 7 8 9 10 11
R
P
N
M
L
K
J
H
G
F
E
I/O109
D
C
B
A
12 13 14 15
I/O106
I/O105
I/O102
I/O100
I/O98
I/O96
I/O86
I/O89
I/O91
I/O94
I/O95
I/O83
I/O80
I/O78
I/O112
I/O110
I/O108
I/O104
I/O101
I/O99
I/O97
I/O84
I/O87
I/O90
I/O93
GND
I/O81
I/O79
I/O75
/SDI
I/O115
I/O113
I/O111
I/O107
I/O103
GND
CLK3
I/O82
I/O85
I/O88
I/O92
CLK2
GND
I/O77
I/O74
/I4
/I3
I/O118
I/O116
I/O114
VCC
VCC
GND
VCC
GND
I/O76
I/O73
I/O71
/SDO
I/O121
I/O119
I/O117
I/O72
I/O70
I/O69
I/O123
I/O122
I/O120
GND
I/O68
I/O67
I/O126
I/O125
I/O124
VCC
VCC
I/O66
I/O65
I/O64
I/O127
GND
ISREN
GND
GND
I2
GND
I/O63
I/O0
I/O1
I/O2
VCC
VCC
I/O60
I/O61
I/O62
I/O3
I/O4
GND
I/O56
I/O58
I/O59
I/O5
I/O6
I/O8
I/O53
I/O55
I/O57
I/O7
I/O9
I/O12
GND
VCC
VCC
VCC
GND
I/O52/
I/O50
I/O71
SMODE
I/O10
I/O13
GND
I/O18
I/O21
I/O24
CLK28
I/O43
I/O39
GND
CLK1
CLK0
I/O47
I/O49
I/O51
/I0
I/O11
I/O15
I/O17
I/O20
I/O23
I/O26
I/O29
I/O40
I/O37
I/O35
I/O33
GND
I/O44
I/O46
I/O48
I/O14
I/O16
I/O19
I/O22
I/O25
I/O27
I/O30
I/O38
I/O36
I/O34
I/O32
I/O31
I/O41
I/O42
I/O45
/I1
/SCLK
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product term sharing help to increase the effective density ofthe FLASH370i PLDs. Note that product term allocation ishandled by software and is invisible to the user.
I/O Macrocell
Each of the macrocells on the CY7C375i has a separate I/Opin associated with it. The input to the macrocell is the sum ofbetween 0 and 16 product terms from the product termallocator. The macrocell includes a register that can beoptionally bypassed, polarity control over the input sum-term,and four global clocks to trigger the register. The macrocellalso features a separate feedback path to the PIM so that theregister can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects theeight logic blocks on the CY7C375i to the inputs and to eachother. All inputs (including feedbacks) travel through the PIM.There is no speed penalty incurred by signals traversing thePIM.
Programming
For an overview of ISR programming, refer to the FLASH370iFamily data sheet and for ISR cable and software specifica-tions, refer to ISR data sheets. For a detailed description ofISR capabilities, refer to the Cypress application note, AnIntroduction to In System Reprogramming with FLASH370i.
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant withthe PCI Local Bus Specification published by the PCI SpecialInterest Group. The simple and predictable timing model ofFLASH370i ensures compliance with the PCI AC specificationsindependent of the design. On the other hand, in CPLD andFPGA architectures without simple and predictable timing, PCIcompliance is dependent upon routing and product termdistribution.
3.3V or 5.0V I/O Operation
The FLASH370i family can be configured to operate in both3.3V and 5.0V systems. All devices have two sets of VCCpins:one set, VCCINT, for internal operation and input buffers, andanother set, VCCIO, for I/O output drivers. VCCINTpins mustalways be connected to a 5.0V power supply. However, the
VCCIOpins may be connected to either a 3.3V or 5.0V powersupply, depending on the output requirements. When VCCIOpins are connected to a 5.0V source, the I/O voltage levels arecompatible with 5.0V systems. When VCCIO pins areconnected to a 3.3V source, the input voltage levels arecompatible with both 5.0V and 3.3V systems, while the outputvoltage levels are compatible with 3.3V systems. There will bean additional timing delay on all output buffers when operatingin 3.3V I/O mode. The added flexibility of 3.3V I/O capability isavailable in commercial and industrial temperature ranges.
Bus Hold Capabilit ies on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold hasbeen added to all FLASH370i I/Os and dedicated input pins.Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that doesnot degrade the devices performance. As a latch, bus-holdrecalls the last state of a pin when it is three-stated, thusreducing system noise in bus-interface applications. Bus-holdadditionally allows unused device pins to remain unconnectedon the board, which is particularly useful during prototyping asdesigners can route new signals to the device without cuttingtrace connections to VCCor GND.
Design Tools
Development software for the CY7C375i is available fromCypresss Warp, Warp Professional, and Warp Enter-prise software packages. Please refer to the data sheets onthese products for more details. Cypress also activelysupports almost all third-party design tools. Please refer tothird-party tool support for further information.
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Maximum Ratings
(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage Temperature .................................65C to +150C
Ambient Temperature with
Power Applied.............................................55C to +125CSupply Voltage to Ground Potential ............... 0.5V to +7.0V
DC Voltage Applied to Outputsin High-Z State ............................................... 0.5V to +7.0V
DC Input Voltage............................................ 0.5V to +7.0V
DC Program Voltage.....................................................12.5V
Output Current into Outputs ........................................16 mA
Static Discharge Voltage...........................................> 2001V(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
RangeAmbient
Temperature VCC VCCINT VCCIO
Commercial 0C to +70C 5V 0.25V 5V 0.25V or3.3V 0.3V
Industrial 40C to +85C 5V 0.5V 5V 0.5V or3.3V 0.3V
Military[2] 55C to +125C 5V 0.5V
Electrical Characteristics Over the Operating Range[3, 4]
Parameter Description Test Conditions Min. Typ. Max. Unit
VOH Output HIGH Voltage VCC= Min. IOH= 3.2 mA (Coml/Ind)[5] 2.4 V
IOH= 2.0 mA (Mil) V
VOHZ Output HIGH Voltage with OutputDisabled[9] VCC= Max. IOH= 0A (Coml/Ind)
[5, 6]
4.0 VIOH= 50 A (Coml/Ind)
[5, 6] 3.6 V
VOL Output LOW Voltage VCC= Min. IOL= 16 mA (Coml/Ind)[5] 0.5 V
IOL= 12 mA (Mil) V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH voltage for allinputs[7]
2.0 7.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW voltage for allinputs[7]
0.5 0.8 V
IIX Input Load Current VI= Internal GND, VI= VCC 10 +10 A
IOZ Output Leakage Current VCC= Max., VO= GND or VO= VCC, Output Disabled 50 +50 A
VCC= Max., VO= 3.3V, Output Disabled[6] 0 70 125 A
IOS Output Short Circuit Current[8, 9] VCC= Max., VOUT= 0.5V 30 160 mA
ICC Power Supply Current[10] VCC= Max., IOUT= 0 mA,f = 1 MHz, VIN= GND, VCC
Coml/Ind. 125 200 mA
Coml L 66 75 125 mA
Military 125 250 mA
IBHL Input Bus Hold LOW Sustaining Current VCC= Min., VIL= 0.8V +75 A
IBHH Input Bus Hold HIGH Sustaining Current VCC= Min., VIH= 2.0V 75 A
IBHLO Input Bus Hold LOW Overdrive Current VCC= Max. +500 A
IBHHO Input Bus Hold HIGH Overdrive Current VCC= Max. 500 A
Capacitance[9]
Parameter Description Test Conditions Min. Max. Unit
CI/O[11] Input/Output Capacitance VIN= 5.0V at f=1 MHz 8 pF
CCLK Clock Signal Capacitance VIN= 5.0V at f = 1 MHz 5 12 pFNotes:2. TAis the instant on case temperature.3. See the last page of this specification for Group A subgroup testing information.4. If VCCIOis not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT.5. IOH= 2
mA, IOL= 2 mA for SDO.6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by
a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note Understanding Bus Hold for additional information.7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT= 0.5V has been chosen to avoid test
problems caused by tester ground degradation.9. Tested initially and after any design or process changes that may affect these parameters.10. Measured with 16-bit counter programmed into each logic block.11.C I/Ofor dedicated inputs, and for I/O pins with JTAG functionality is 12 pF,and for the ISRENpin is 15 pF Max.
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Note:12.tERmeasured with 5-pF AC Test Load and tEAmeasured with 35-pF AC Test Load.
Inductance[9]
Parameter Description Test Conditions160-Lead
TQFP160-PinCQFP
160-PinCPGA Unit
L Maximum Pin Inductance VIN= 5.0V at 5 = 1 MHz 9 6 10 nH
Endurance Characteristics
[9]
Parameter Description Test Conditions Max. Unit
N Maximum Reprogramming Cycles Normal Programming Conditions 100 Cycles
AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES5V
OUTPUT
35 pF
INCLUDINGJIG ANDSCOPE
5V
OUTPUT
5 pF
INCLUDINGJIG AND
SCOPE
(a) (b)
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Switching Characteristics Over the Operating Range [13]
Parameter Description
7C375i125 7C375i1007C375i83
7C374iL837C375i66
7C375iL66
UnitMin. Max. Min. Max. Min. Max. Min. Max.
Combinator ial Mode Parameters
tPD Input to Combinatorial Output[1] 10 12 15 20 nstPDL Input to Output Through Transparent Input
or Output Latch[1]13 15 18 22 ns
tPDLL Input to Output Through Transparent Inputand Output Latches[1]
15 16 19 24 ns
tEA Input to Output Enable[1] 14 16 19 24 ns
tER Input to Output Disable 14 16 19 24 ns
Input Registered/Latched Mode Parameters
tWL Clock or Latch Enable Input LOW Time[9] 3 3 4 5 ns
tWH Clock or Latch Enable Input HIGH Time[9] 3 3 4 5 ns
tIS Input Register or Latch Set-Up Time 2 2 3 4 ns
tIH Input Register or Latch Hold Time 2 2 3 4 nstICO Input Register Clock or Latch Enable to
Combinatorial Output[1]14 16 19 24 ns
tICOL Input Register Clock or Latch Enable toOutput Through Transparent Output Latch[1]
16 18 21 26 ns
Ouptut Registered/Latched Mode Parameters
tCO Clock or Latch Enable to Output[1] 6.5 7 8 10 ns
tS Set-Up Time from Input to Clock or LatchEnable
5.5 6 8 10 ns
tH Register or Latch Data Hold Time 0 0 0 0 ns
tCO2 Output Clock or Latch Enable to OutputDelay (Through Memory Array)[1]
14 16 19 24 ns
tSCS Output Clock or Latch Enable to OutputClock or Latch Enable (Through MemoryArray)
8 10 12 15 ns
tSL Set-Up Time from Input Through Trans-parent Latch to Output Register Clock orLatch Enable
10 12 15 20 ns
tHL Hold Time for Input Through TransparentLatch from Output Register Clock or LatchEnable
0 0 0 0 ns
fMAX1 Maximum Frequency with InternalFeedback (Least of 1/tSCS, 1/(tS+ tH), or1/tCO)
[9]
125 100 83 66 MHz
fMAX2 Maximum Frequency Data Path in OutputRegistered/Latched Mode (Lesser of 1/(tWL
+ tWH), 1/(tS+ tH), or 1/tCO)
158.3 143 125 100 MHz
fMAX3 Maximum Frequency with ExternalFeedback (Lesser of 1/(tCO+ tS) and 1/(tWL+ tWH,
83.3 76.9 62.5 50 MHz
tOHtIH37x
Output Data Stable from Output ClockMinus Input Register Hold Time for 7C37x[9,14]
0 0 0 0 ns
Notes:13. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.14. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C375i. This specification is met for
the devices operating at the same ambient temperature and at the same power supply voltage.
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Pipelined Mode Parameters
tICS Input Register Clock to Output RegisterClock
8 10 12 15 ns
fMAX4 Maximum Frequency in Pipelined Mode(Least of 1/(tCO+ tIS), 1/tICS, 1/(tWL+ tWH),1/(tIS+ tIH), or 1/tSCS)
125 100 83.3 66.6 MHz
Reset/Preset Parameters
tRW Asynchronous Reset Width[9] 10 12 15 20 ns
tRR Asynchronous Reset Recovery Time[9] 12 14 17 22 ns
tRO Asynchronous Reset to Output[1] 16 18 21 26 ns
tPW Asynchronous Preset Width[9] 10 12 15 20 ns
tPR Asynchronous Preset Recovery Time[9] 12 14 17 22 ns
tPO Asynchronous Preset to Output[1] 16 18 21 26 ns
Tap Controller Parameter
fTAP Tap Controller Frequency 500 500 500 500 kHz
3.3V I/O Mode Parameters
t3.3IO 3.3V I/O mode timing adder 1 1 1 1 ns
Switching Waveforms
Switching Characteristics Over the Operating Range (continued)[13]
Parameter Description
7C375i125 7C375i1007C375i83
7C374iL837C375i66
7C375iL66
UnitMin. Max. Min. Max. Min. Max. Min. Max.
tPD
INPUT
COMBINATORIALOUTPUT
Combinatorial Output
Registered Output
tS
INPUT
CLOCK
tCO
REGISTEREDOUTPUT
tH
CLOCK
tWLtWH
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Switching Waveforms(continued)
Latched Input
tIS
LATCHED INPUT
LATCHENABLE
tICO
COMBINATORIALOUTPUT
tIH
tPDL
LATCH ENABLE
tWLtWH
Latched Input and Output
tICS
LATCHED INPUT
OUTPUT LATCHENABLE
LATCHEDOUTPUT
tPDLL
LATCH ENABLE
tWLtWH
tICOL
INPUT LATCHENABLE
tSLtHL
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Switching Waveforms(continued)
Asy nchronous Reset
INPUT
tRO
REGISTEREDOUTPUT
CLOCK
tRR
tRW
Asy nchronous Preset
INPUT
tPO
REGISTEREDOUTPUT
CLOCK
tPR
tPW
Output Enable/Disable
INPUT
tER
OUTPUTS
tEA
Ordering Information
Speed(MHz) Ordering Code
PackageName Package Type
OperatingRange
125 CY7C375i125AC A160 160-Lead Thin Quad Flatpack Commercial
100 CY7C375i100AC A160 160-Lead Thin Quad Flatpack Commercial
CY7C375i100AI A160 160-Lead Thin Quad Flatpack Industrial
83 CY7C375i83AC A160 160-Lead Thin Quad Flatpack Commercial
CY7C375i83AI A160 160-Lead Thin Quad Flatpack Industrial
CY7C375i83GMB G160 160-Pin Grid Array Military
CY7C375i83UMB U162 160-Pin Ceramic Quad Flatpack[15]
CY7C375iL83AC A160 160-Lead Thin Quad Flatpack Commercial
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MILITARY SPECIFICATIONSGroup A Subgroup Testing
Note:15. Standard product ships trim and formed in a carrier. This product is also available in a molded carrier ring. Contact local Cypress office for package information.
66 CY7C375i66AC A160 160-Lead Thin Quad Flatpack Commercial
CY7C375i66AI A160 160-Lead Thin Quad Flatpack Industrial
CY7C375i66GMB G160 160-Pin Grid Array MilitaryCY7C375i66UMB U162 160-Pin Ceramic Quad Flatpack[15]
CY7C375iL66AC A160 160-Lead Thin Quad Flatpack Commercial
Ordering Information(continued)
Speed(MHz) Ordering Code
PackageName Package Type
OperatingRange
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tPD 9, 10, 11
tCO 9, 10, 11
tICO 9, 10, 11
tS 9, 10, 11
tH 9, 10, 11tIS 9, 10, 11
tIH 9, 10, 11
tICS 9, 10, 11
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Document #: 38-03029 Rev. *A Page 16 of 17 Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorizeits products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of CypressSemiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Warp is a registered trademark and Ultra37000, WarpProfessional, WarpEnterprise, ISR, UltraLogic, FLASH370 and FLASH370iare trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trade-
marks of their respective holders.
Package Diagrams(continued)
SEATING PLANE
DIMENSION IN MM (INCH)
2.79(.110)
2.03(.080)
0.500(.020)
0.050(.002)
(.020 .008)
0.51 0.20
(.006 .001)
0.15 0.02
TYP.
0.300(.012)
TYP.
0.650(.0256)
(1.228 .010)
31.20 0.25
(1.102 .004)
28.00 0.10
SQ.
SQ.
PIN 1
25.350.10
(.998.004)
TYP.
SEE DETAIL A
(.008 MIN.)
0-7
0.20 MIN.
DETAIL A
REFERENCE JEDEC: N/A
PKG. WEIGHT: 6-7gms
0 MIN.
R 0.13(.005)
MIN.
160-Lead Ceramic Quad Flatpack (Cavity Up) U162
51-80106-*A
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Document History Page
Document Title: CY7C375i UltraLogic 128-Macrocell Flash CPLDDocument Number: 38-03029
REV. ECN NO. Issue DateOrig. ofChange Description of Change
** 106374 09/15/01 SZV Change from Spec number: 38-00494 to 38-03029*A 213375 See ECN FSG Added note to title page: Use Ultra37000 For All New Designs