Xilinx - Application Note: Kintex-7 FPGAs SMPTE2022-5/6 ......Hardware System Specifics XAPP896 (v1.0) March 7, 2013 6 SMPTE 2022-5/6 Video Over IP Receiver The SMPTE 2022-5/6 video

XAPP896 (v1.0) March 7, 2013 www.xilinx.com 1

© Copyright 2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. All other trademarks are the property of their respective owners.

Summary This application note covers the design considerations of a Video over IP network system using the performance features of the LogiCORE™ IP SMPTE 2022-5/6 Video over IP transmitter and receiver cores. The design focuses on high bit rate native media transport over 10 Gb/s Ethernet with a built-in forward error correction engine. The design is able to support up to three SD/HD/3G SDI streams.

The reference design has two platforms: the transmitter platform and the receiver platform. The transmitter platform design uses three LogiCORE SMPTE SDI cores to receive the incoming SDI video streams. The received SDI streams are multiplexed and encapsulated into fixed-size datagrams by the SMPTE 2022-5/6 video over IP transmitter core and sent out through the LogiCORE IP 10-Gigabit Ethernet MAC. The 10-Gigabit link is supported by a LogiCORE IP 10-Gigabit Ethernet PCS/PMA using an optical cable connected to the receiver end. On thereceiver platform, the Ethernet datagrams are collected at the 10-Gigabit Ethernet MAC. TheSMPTE 2022-5/6 video over IP receiver core filters the datagrams, de-encapsulates andde-multiplexes the datagrams into individual streams which are output through the SMPTE SDIcores. The Ethernet datagrams are buffered in DDR3 SDRAM memory for both the transmitterand receiver. The DDR traffic passes through the AXI interconnect to the AXI 7 series memorycontroller. A MicroBlaze™ processor is included in the design to initialize the cores and readthe status.

The reference design targets the Xilinx Kintex®-7 FPGA KC705 evaluation kit, which uses the Kintex-7 XC7K325T-2FFG900 FPGA and the Inrevium TB-FMCH-3GSDI2A board. See the Kintex-7 FPGA KC705 Evaluation Kit [Ref 1] and the Inrevium TB-FMCH-3GSDI2A [Ref 2] for details.

Included Systems

The reference design is created using version 14.4 of the ISE® Design Suite: System Edition. Part of the design is created using the Xilinx Platform Studio (XPS) tool. The design also includes software built using the Xilinx Software Development Kit (SDK). The software runs on the MicroBlaze™ embedded processor and implements control and status functions. Complete ISE, XPS, and SDK tool project files are provided with this application note to allow the user to examine and rebuild the design or to use it as a template for starting a new design.

Introduction The reference design is built around the SMPTE 2022-5/6 video over IP transmitter and receiver cores and leverages existing Xilinx IP cores to form the complete system. The input and output of the system are SDI video streams. The system consists of two platforms. The transmitter and receiver cores each reside in separate platforms. An optical cable connects the two platforms simulating an IP network. See Figure 1.

The SMPTE SDI core allows the video over IP cores to receive and transmit SDI streams while the 10-Gigabit Ethernet MAC and 10-Gigabit Ethernet PCS/PMA enable the video over IP cores to transfer SDI data in the Ethernet medium. See Figure 2 and Figure 3.

Application Note: Kintex-7 FPGAs

XAPP896 (v1.0) March 7, 2013

SMPTE2022-5/6 High Bit Rate Media Transport over IP Networks with Forward Error Correction on Kintex-7 FPGAsAuthors: Gilbert Magnaye, Josh Poh, Myo Tun Aung, and Tom Sun

Discontinued IP

http://www.xilinx.com

Introduction


Other than managing the SDI streams, encapsulation and de-encapsulation, the transmitter and receiver cores include forward error correction (FEC) protection features. FEC protects the video stream during the transport of high-quality video over IP networks. With FEC, the transmitter adds systematically generated redundant data to its video. This redundancy allows the receiver to detect and correct a limited number of packet errors occurring anywhere in the video without the need to ask the transmitter for additional video data. These errors, in the form of lost video packets, result from a variety of causes ranging from thermal noise to storage system defects and transmission noise introduced by the environment. FEC gives the receiver the ability to correct these errors without needing a reverse channel to request retransmission of data. This feature can be enabled using the core registers.

X-Ref Target - Figure 1

Figure 1: Block Diagram of the Video over IP System


Figure 2: Block Diagram of the Video over IP Transmitter FPGA


Figure 3: Block Diagram of the Video over IP Receiver FPGA

Transmitter Platform

KC705EvaluationKit

OpticalTransceiver

Receiver Platform

OpticalTransceiver

Inrevium SDIFMC Board

KC705EvaluationKit

Optical cable

X896_01_120412

SDIVideo In

SDIVideoOutInrevium SDI

FMC Board

SDIVideo SMPTE2022-5/6

Video OverIP Transmitter

Triple-RateSDI

Ten GigabitEthernet

MAC

10-GigabitEthernet

PCS/PMA

Ethernet

AXI MM AXI4 Lite

MicroBlazeSubsystem

X896_02_120412

Ethernet SMPTE2022-5/6Video OverIP Receiver

Ten GigabitEthernet

PCS/PMA

Ten GigabitEthernet

MAC

Triple-RateSDI

SDIVideo

AXI MM AXI4 Lite

MicroBlazeSubsystem

X896_03_120412

Discontinued IP


Introduction


High-level control of the system is provided by a simplified MicroBlaze embedded processor subsystem containing I/O peripherals and processor support IP. A clock generator block and a processor system reset block supply clock and reset signals for the system, respectively. An AXI4 interconnect and an AXI4 memory interface generator (MIG) are instantiated in the subsystem allowing the video over IP cores access to the DDR3 SDRAM. See Figure 4 and Table 1 for a block diagram of the MicroBlaze processor subsystem and its address map.


Figure 4: Block Diagram of the Reference Design MicroBlaze Subsystem Built with XPS

AXI 7 SeriesMemory

Controller

AXI ExternalMaster

Connector

AXI ExternalMaster

Connector

AXI ExternalMaster

Connector

AXI ExternalMaster

Connector

Connected to SMPTE2022-5/6 Video Over IP Transmitter or ReceiverConnect to DDR3 SDRAM

AXI Interconnect(AXI MM)

MicroBlazeProcessor

MicroBlazeDebugModule

LMB Block RAMController

LMB Block RAMController

BlockRAM

LMB

LMB

AXI UART(Lite)

AXI InterruptController

CustomizedAXI LiteBridge

Connected to SMPTE2022-5/6Video Over IP Transmitter or Receiver

AXI Interconnect(AXI Lite)

FPGA I/OClock

Generator

ProcessorSystemReset

ModuleX896_04_020413

Table 1: MicroBlaze Subsystem Address Map

Peripheral Instance Base Address High Address

lmb_bram_if_cntlr microblaze_0_i_bram_ctrl 0x00000000 0x0001ffff

lmb_bram_if_cntlr microblaze_0_d_bram_ctrl 0x00000000 0x0001ffff

Mdm debug_module_0 0x7e200000 0x7e20ffff

axi_7series_ddrx axi_7series_ddrx_0 0xc0000000 0xffffffff

axi_uartlite RS232_Uart_1 0x40600000 0x4060ffff

axilite_bridge axilite_bridge_0 0x70e00000 0x70e0ffff

axi_ext_slave_conn ten_gig_eth_mac 0x7c400000 0x7c400fff

Discontinued IP


Hardware Requirements


Hardware Requirements

The hardware requirements for this reference design are:

• Two Kintex-7 FPGA KC705 evaluation kits

• Two Inrevium 3G-SDI boards (TB-FMCH-3GSDI2A)

• Two SFP+ optical transceivers

• Optical cable

• Xilinx Platform Studio 14.4

• ISE Design Suite 14.4

• SDK 14.4

Reference Design Specifics

In addition to the SMPTE 2022-5/6 video over IP transmitter and receiver cores, the reference design includes these cores:

• AXI4 interconnect

• MicroBlaze embedded processor

• MicroBlaze debug module

• Local memory bus

• LMB block RAM controller

• Block RAM

• AXI4 external master connector

• AXI4 external slave connector

• Clock generator

• Processor system reset module

• AXI4-Lite UART

• Customized AXI4-Lite bridge (pcore)

• 7 series FPGAs AXI4 memory controller (DDR2/DDR3)

• SMPTE SDI

• 10-Gigabit Ethernet MAC

• 10-Gigabit Ethernet PCS/PMA

Hardware System Specifics

This section describes the high-level features of the reference design, including how the main IP blocks are configured.

Video Over IP System

The reference design implements the SMPTE 2022-5/6 video over IP cores as modules for broadcast applications that require bridging between broadcast connectivity standards (SD/HD/3G) and a 10-Gigabit Ethernet network. The cores are intended for developing Internet protocol-based systems to reduce the overall cost in broadcast facilities for distribution and routing of audio and video data. The SDI data to be transported are mapped into media datagram payloads as per SMPTE 2022-6. The systematically-generated redundant forward error correction datagrams are formatted according to SMPTE 2022-5. IP/UDP/RTP protocols provide standard headers when transporting the media and FEC datagrams over the IP network.

To support the system functions correctly, the bandwidth available in the network must meet or exceed what is required to support the stream generated by the system. The overhead required for media datagram generation is approximately 5% due to the IP/UDP/RTP and SMPTE 2022-6 headers.

Discontinued IP




SMPTE 2022-5/6 Video Over IP Transmitter

The SMPTE 2022-5/6 video over IP transmitter in the reference design is configured to accept three channels of SDI input from the SMPTE SDI receiver. The transmitter connects to the 10-Gigabit Ethernet MAC via an AXI4-Stream data interface. The transmitter also connects to a customized pcore in the MicroBlaze subsystem via an AXI4-Lite control interface. The transmitter core does not have native EDK support, hence a customized pcore called axilite_bridge is created for register access. The transmitter core uses two AXI4 external master connectors to access the DDR3 SDRAM via the AXI4 interconnect. The memory map address range is fixed at 0xC0000000 – 0xFFFFFFFF.

The transmitter source MAC address is set to 0x000000000000AA. The transmitter source IP address is set to 192.168.1.100 and the destination IP address for all channels is set to 192.168.1.50. The UDP ports are configured as shown in Table 2. The FEC matrix sizes set for the channels are listed in Table 3. These parameters are configurable through the registers.

The SMPTE 2022-5/6 video over IP transmitter contains an AXI4-Lite interface which allows dynamic control of the parameters within the core from a processor. For more information about the registers, see the LogiCORE IP SMPTE 2022-5/6 Video over IP Transmitter v2.1 Product Guide [Ref 3].

The registers are categorized into two sections: the general space and the channel space. The parameters in the general space apply to all of the channels. The parameters in the channel space apply to an individual channel.

For the general registers, normal address read and write access is applied. For the channel registers, observe these steps to update the registers:

1. Set the channel to be configured at register address base_addr+0x030.

2. Configure the channel specific register.

3. Pulse bit 1 of register address base_addr+0x000 to commit the change to the channel registers.

4. Repeat steps 1–3 for another channel or registers (see Figure 5).

Table 2: UDP Port Values for the Three SDI Channels

BNC Connector Channel Source UDP Port Destination UDP Port

RX1 0 0x10 0x10

RX2 1 0x20 0x20

RX3 2 0x30 0x30

Table 3: FEC Matrix Size Values for the Three SDI Channels

BNC Connector Channel L D

RX1 0 77 77

RX2 1 77 77

RX3 2 77 77

Discontinued IP




SMPTE 2022-5/6 Video Over IP Receiver

The SMPTE 2022-5/6 video over IP receiver in the reference design is configured to stream three channels of SDI output to the SMPTE SDI transmitters. The receiver connects to the 10-Gigabit Ethernet MAC through an AXI4-Stream data interface. The receiver also connects to a customized pcore in the MicroBlaze processor subsystem via an AXI4-Lite control interface. The receiver core does not have native EDK support, hence a customized pcore called axilite_bridge is created for register access. The receiver core uses three AXI4 external master connectors to access the DDR3 SDRAM via an AXI4 interconnect. The memory map address range is fixed at 0xC0000000–0xFFFFFFFF. The SMPTE 2022-5/6 video over IP receiver uses a VCXO replacement solution for video clock recovery. See the All Digital VCXO Replacement for Gigabit Transceiver Applications Application Note [Ref 4] for details.


Figure 5: Channel Register Configuration Flow Chart

Start

Set Channel Accessin BaseAddr + 0x030

Configure Channel Specific

Registers

Set Bit 1 ofControl Register

(BaseAddr + 0x000)

Clear Bit 1 ofControl Register

(BaseAddr + 0x000)

Done?

End

Yes

No

X896_05_121712

Discontinued IP




The incoming media packets are filtered based on the UDP destination ports, as shown in Table 4. The IP source address and SSRC are not being used as criteria.

The number of media packets to be buffered before starting the SDI output per channel is set at 14,000.

The SMPTE 2022-5/6 video over IP receiver contains an AXI4-Lite interface which allows users to dynamically control the parameters within the core from a processor. For more information about the registers, see the LogiCORE IP SMPTE 2022-5/6 Video over IP Receiver v2.1 Product Guide [Ref 5].

The registers are categorized into two sections, the general space and the channel space. The parameters in the general space apply to all of the channels. The parameters in the channel space apply to an individual channel.

For the general registers, normal address read and write access is applied. For the channel registers, observe these steps to update the registers:

1. Set the channel to be configured at register address base_addr+0x030.

2. Configure all of the channel registers of interest for the particular channel.

3. Pulse bit 1 of register address base_addr+0x000 to commit the change to the channel registers.

4. Repeat steps 1–3 for another channel. See Figure 5, page 6.

SMPTE SDI

The SMPTE SDI core provides transmitter and receiver interfaces for SMPTE SD-SDI, HD-SDI and 3G-SDI standards. The core is connected to a 7 series FPGA GTX transceivers for serialization and deserialization of the SDI video streams. The SMPTE SDI receiver uses a 148.5 MHz GTX transceiver reference clock frequency to receive its supported SDI bit rates. The receiver automatically determines the incoming SDI bit rate and configures itself and the GTX transceiver appropriately for that SDI mode. The SMPTE SDI transmitter requires two different GTX transceiver reference clock frequencies for its supported SDI bit rates. 148.5 MHz and 148.35 MHz are used in the design. The clock multiplexer built into the GTX transceiver switches between these two reference clocks. A port dynamically controls the operating SDI mode for the transmitter. The transmitter, in turn, controls the GTX transmitter through the DRP to provide the appropriate configuration for each SDI mode. See the LogiCORE IP SMPTE SD/HD/3G-SDI v1.0 Product Guide [Ref 6] for more information.

10-Gigabit Ethernet MAC

The 10-Gigabit Ethernet MAC instance on the transmitter side has its AXI4-Stream transmit interface connected to the output of the SMPTE 2022-5/6 video over IP transmitter. The 10-Gigabit Ethernet MAC instance on the receiver side has its AXI4-Stream receive interface connected to the input of the SMPTE 2022-5/6 video over IP receiver. A 64-bit SDR PHY port is configured in the 10-Gigabit Ethernet MAC to interface to the 10-Gigabit Ethernet PCS/PMA core. No flow control is used. See the LogiCORE IP 10-Gigabit Ethernet MAC v11.4 Product Guide [Ref 7] for more information.

Table 4: UDP Port Values for the Three SDI Channels

BNC Connector Channel Destination UDP Port

TX1 0 0x10

TX2 1 0x20

TX3 2 0x30

Discontinued IP




10-Gigabit Ethernet PCS/PMA

The 10-Gigabit Ethernet PCS/PMA core creates a 10GBASE-R optical link between the video over IP transmitter and receiver. The PCS/PMA uses ones transceiver to achieve a 10 Gb/s data rate. An optical cable is connected between the SFP+ optical transceivers on both sides. The PCS/PMA 10GBASE-R/KR standard is fully specified in clauses 45, 49, 72, 73, and 74 of the 10-Gigabit Ethernet IEEE 802.3-2008 specification. See the LogiCORE 10-Gigabit Ethernet PCS/PMA v2.5 Product Guide [Ref 8] for more information.

AXI4 Interconnect (AXI_MM)

This AXI4 interconnect instance provides the high FMAX and throughput for the design with a 256-bit core data width and a 200 MHz clock frequency. The AXI4 interconnect core data width and clock frequency match the capabilities of the attached AXI4 MIG so that width and clock converters are not required between them. Setting the AXI4 interconnect core data width and clock frequency below the native width and clock frequency of the memory controller creates a bandwidth bottleneck within the system. To help meet the timing requirements of a 256-bit AXI4 interface at 200 MHz, a rank of register slices are enabled between the AXI_MM interconnect and the AXI4 MIG. Together, the AXI4 interconnect and AXI4 MIG form a 4-port AXI4 MPMC connected to four AXI4 external master connectors. The configuration of this AXI4 interconnect is consistent with the system performance optimization recommendations for an AXI4 MPMC-based system as described in the AXI Reference Guide [Ref 9].

7 Series FPGAs AXI4 Memory Controller (DDR2/DDR3)

The 7 series FPGAs AXI4 memory controller (a block that integrates the MIG tool into the XPS tool) is the single slave connected to the AXI4 interconnect. The memory controller AXI4 interface is 256 bits wide running at 200 MHz and disables narrow burst support for optimal throughput and timing. This configuration matches the native AXI4 interface clock and width corresponding to a 64-bit DDR3 DIMM with an 800 MHz memory clock, which is the nominal performance of the memory controller for a Kintex-7 device with a -2 speed specification. Register slices are enabled to ensure that the interface meets timing at 200 MHz. These settings help ensure that a high degree of transaction pipelining is active to improve system throughput. See the 7 Series FPGAs Memory Interface Solutions User Guide [Ref 10] for more information about the memory controller.

AXI4 Interconnect (AXI4-Lite)

The MicroBlaze processor data peripheral (DP) interface master writes and reads to all AXI4-Lite slave registers in the design for control and status information. These interconnects are 32 bits and do not require high FMAX and throughput. Therefore, they are connected to a slower FMAX portion of the design by a separate AXI4 interconnect. The AXI4-Lite interconnect block is configured for shared-access mode because high throughput is not required in this portion of the design. Therefore, area can be optimized over performance on this interconnect block. Also, this interconnect is clocked at 100 MHz to allow the use of synchronous integer ratio clock converters in the AXI4 interconnect, which offer lower latency and less area than asynchronous clock converters. The slaves on the AXI4-Lite interconnect are MDM, AXI4 UART (AXI4-Lite) and a customized pcore to the SMPTE 2022-5/6 video over IP transmitter or receiver core.

Discontinued IP


Software Applications


Software Applications

The individual software applications initialize the video over IP TX and RX systems respectively. After the initialization, commands are selected from the menu in the UART display.

Application-level software and the drivers for controlling the system are written in C. Alternatively, drivers and application software can be written to use the IP control registers directly.

The software configures the register values as shown in Table 5 and Table 6.

After the initial setup sequence, the commands are chosen from the multi-layered menu list in the UART display.

Table 5: Initialized Video Over IP TX Register Values

Offset Register Name Value

General Space

0x060 Src_mac_low_addr 0x000000AA

0x064 Src_mac_high_addr 0x00000000

0x068 Src_IP_addr 0xC0A80064

Channel Space Ch1 Ch2 Ch3

0x104 FEC_config 0x7 0x7 0x7

0x10C FEC_L 0x4D 0x4D 0x4D

0x110 FEC_D 0x4D 0x4D 0x4D

0x128 dest_ip_addr 0xC0A80032 0xC0A80032 0xC0A80032

0x138 src_udp_port 0x10 0x20 0x30

0x13C dest_udp_port 0x10 0x20 0x30

0x140 SSRC 0x12345600 0x12345610 0x12345620

Table 6: Initialized Video Over IP RX Register Values

Offset Register Name Value

General Space

0x054 reserved0 0x000003E8

0x060 mac_low_addr 0x000000BB

0x064 mac_high_addr 0x00000000

0x068 IP_host_addr 0xC0A80032

Channel Space Ch1 Ch2 Ch3

0x100 chan_en 0x1 0x1 0x1

0x104 reserved1 0x3 0x3 0x3

0x110 firewall_sel 0x0 0x0 0x0

0x114 dest_port 0x10 0x20 0x30

0x118 SSRC 0x12345600 0x12345610 0x12345620

0x11C src_ip_host_addr 0xC0A80064 0xC0A80064 0xC0A80064

0x12C start_buffer_size 0x36B0 0x36B0 0x36B0

Discontinued IP


Executing the Reference Design in Hardware



This section provides instructions to execute the reference design in hardware. This reference design runs on the KC705 and TB-FMCH-3GSDI2A boards (shown in Figure 6 and Figure 7).


Figure 6: Video Over IP System Setup

10GbE

SDI

SDI

HDMI

HDMI

Canon HV20Camcorder

ConvergentHDMI > SDI

Black MagicSDI > HDMI

28” Monitor

KC705Board

KC705 Board

Inrevium3G-SDIModule

Inrevium3G-SDIModule

USB JTAG

OmniTekOTM1000

(with 3G Eye)

USB UART

USB JTAG USB UART

X896_06_120712

Discontinued IP




In these instructions, the numbers in parentheses correspond to the callout numbers in Figure 7.

1. Connect a USB cable from the host PC to the USB JTAG port (1). Ensure the appropriate device drivers are installed.

2. Connect a second USB cable from the host PC to the USB UART port (2). Ensure that the USB UART drivers described in Hardware Requirements, page 4, are installed.

3. Connect the TB-FMCH-3GSDI2A board to the HPC-FMC connector (3) of the KC705 board.

4. Connect an SFP+ Optical Transceiver to the SFP slot (4).

5. Connect a jumper to J4 (5) to enable SFP+ transmitter

6. Connect one end of the optical cable (6) to the SFP+ connector of the transmitter board, the other end to the SFP+ connector of the receiver board.

7. Connect the CH0-TX, CH1-TX, and CH2 ports of the TB-FMCH-3GSDI2A board (7) on the receiver KC705 board to the SDI video monitor.

8. Connect the CH0-RX, CH1-RX, and CH2 ports of the TB-FMCH-3GSDI2A board (8) on the transmitter KC705 board to the SDI video generator.

9. Connect the KC705 board power connector (9) to a power supply.

10. Move the KC705 board power switch (10) to the ON position.

11. Ensure that the HW-KC705 board revision (11) is the same for both the TX and RX platforms.


Figure 7: KC705 and TB-FMCH-3GSDI2A Boards

1

25

4

6 3

8 7

10

911

X896_07_120712

Discontinued IP




12. Start a terminal program (e.g., HyperTerminal) on the host PC with these settings:

• Baud Rate: 115200

• Data Bits: 8

• Parity: None

• Stop Bits: 1

• Flow Control: None

Note: 10 Gb ETH PCS/PMA GTX transceiver P and N pins were swapped on board revisions before v1.1 (e.g., v1.0 and C). This causes optical signal compatibility issues on standard equipment. This issue is resolved by connecting TXPOLARITY and RXPOLARITY to VCC in the ten_gig_eth_pcs_pma_v2_5_gtwizard_10gbaser_gt.vhd RTL file which inverts the GTX transceiver TX and RX ports.

Executing the Reference System Using the Pre-built Bitstream and the Compiled Software Application with the ISE iMPACT Tool

Follow these steps to execute the system using files in the appropriate ready_for_download directory:

VoIP_TX: <unzip_dir>/kc705_smpte2022_56_3ch_tx/

VoIP_RX: <unzip_dir>/kc705_smpte2022_56_3ch_rx/

Invoke the ISE iMPACT tool and configure the FPGA using the download.bit file in the appropriate directory:

VoIP_TX: >cd <unzip_dir>/kc705_smpte2022_56_3ch_tx/ready_for_download

VoIP_RX: >cd <unzip_dir>/kc705_smpte2022_56_3ch_rx/ready_for_download

Note: The software application starts immediately after the completion of FPGA configuration. The executable file (ELF) is embedded in the configuration file download.bit.

Discontinued IP


Results from Running Hardware and Software



V_SMPTE2022_56_TX UART Display

The HyperTerminal screen of the V_SMPTE2022_56_TX reference design displays the output that is shown in Figure 8.


Figure 8: V_SMPTE2022_56_TX HyperTerminal Output

x896_08_021513

____ ____ / /\/ //___/ \ / Xilinx Inc.\ \ \/ V_SMPTE2022_56_TX KC705 Reference Design \ \ Created: November 15, 2012 / / Copyright (c) 2012 Xilinx, Inc./___/ /\ All rights reserved.\ \ / \ \___\/\___\

VoIP TX ResetVoIP TX Initializing...IP Address: 192.168.0.100MAC Address: 00-00-00-00-00-AATime Stamp: DisabledIP Version: IPv4VLAN: DisabledVLAN Tag: 0xABCDVoIP TX Initialization done

Initializing Channel 1Channel EnabledDest IP Addr: 192.168.0.50Source Port: 0x0010Dest Port: 0x0010SSRC: 0x12345600FEC Size: 77x77FEC: OffChannel 1 Initialization Done



------------------------- VoIP TX Main Menu -------------------------

Select option 1 = Reset Core 2 = Initialize Core 3 = Configure Channel 4 = Probe Current Settings q = exit ? = help------------------>

Discontinued IP




One of six options can be chosen from those displayed on the HyperTerminal screen:

1 = Reset core

2 = Initialize core (general space registers only)

3 = Configure channel (opens select channel submenu)

4 = Probe current settings (displays status of selected registers in general space)

q = Exit software application

? = Display current menu

Select the configure channel option by entering 3. One of four options can be chosen from the resulting select channel display as shown in Figure 9:

1 = Channel 1

2 = Channel 2

3 = Channel 3

m = Main menu

After selecting any of the channels, the select option submenu is displayed as shown in Figure 10.

One of six options can be chosen from those in the menu list:

1 = Channel init (configure target channel registers)

2 = Channel enable/disable

3 = FEC On/Off (toggle FEC engine)

4 = Probe status

m = Main menu

c = Channel select


Figure 9: V_SMPTE2022_56_TX Select Channel HyperTerminal Output


Figure 10: V_SMPTE2022_56_TX Select Option HyperTerminal Output

x896_09_021513

Select Channel 1 = Channel 1 2 = Channel 2 3 = Channel 3 m = Main Menu------------------>

Select Option 1 = Channel Init 2 = Channel Enable/Disable 3 = FEC On/Off 4 = Probe Status m = Main Menu c = Channel Select------------------>

x896_10_021513

Discontinued IP




V_SMPTE2022_56_RX UART Display

The HyperTerminal screen of the V_SMPTE2022_56_RX reference design displays the output shown in Figure 11.


Figure 11: V_SMPTE2022_56_RX HyperTerminal Output

X896_11_021513

____ ____ / /\/ //___/ \ / Xilinx Inc.\ \ \/ V_SMPTE2022_56_RX KC705 Reference Design \ \ Created: November 15, 2012 / / Copyright (c) 2012 Xilinx, Inc./___/ /\ All rights reserved.\ \ / \ \___\/\___\

VoIP RX ResetVoIP RX Initializing...IP Address: 192.168.0.50MAC Address: 00-00-00-00-00-BBVoIP RX Initialization done

Initializing Channel 1Channel EnabledHost IP Addr: 192.168.0.100Source Port: 0x0010SSRC: 0x12345600Buffer Size: 14000Channel 1 Initialization Done



------------------------- VoIP RX Main Menu -------------------------

Select option 1 = Reset Core 2 = Initialize Core 3 = Configure Channel 4 = Probe Current Settings q = exit ? = help------------------>

Discontinued IP




One of six options can be chosen from those displayed on the HyperTerminal screen:

1 = Reset core

2 = Initialize core general space registers

3 = Configure channel (opens select channel submenu)

4 = Probe current settings (displays status of selected registers in general space)

q = Exit software application

? = Display current menu

Select the configure channel option by entering 3. One of four options can be chosen from the resulting select channel display as shown in Figure 12:

1 = Channel 1

2 = Channel 2

3 = Channel 3

m = Main menu

After selecting any of the channels, the select option submenu is displayed as shown in Figure 13

One of the five options can be chosen from those in the menu list:

1 = Channel init (configure target channel registers)

2 = Channel enable/disable

3 = Probe status

m = Main menu

c = Channel select


Figure 12: V_SMPTE2022_56_RX Select Channel HyperTerminal Output


Figure 13: V_SMPTE2022_56_RX Select Option HyperTerminal Output

X896_12_021513

Select Channel 1 = Channel 1 2 = Channel 2 3 = Channel 3 m = Main Menu------------------>

X896_13_021513

Select Option 1 = Channel Init 2 = Channel Enable/Disable 3 = Probe Status m = Main Menu c = Channel Select------------------>

Discontinued IP


Building Hardware


Building Hardware

This section covers rebuilding the hardware design. Before rebuilding the project, ensure that the licenses for the SMPTE 2022-5/6 video over IP transmitter and receiver cores, 10-Gigabit Ethernet PCS/PMA, and 10-Gigabit Ethernet MAC are installed.

Generating the Programming File with the ISE Design Suite1. Open the XISE project file with the ISE tools:

TX: <unzip dir>\kc705_smpte2022_56_3ch_tx\HW\VoIP_TX_10G_ISE\VoIP_TX_ISE.xise

RX: <unzip dir>\kc705_smpte2022_56_3ch_rx\HW\VoIP_TX_10G_ISE\VoIP_RX_ISE.xise

2. Select Generate Programming File.

Compiling Software Using the SDK Tools1. Click i_system_basic in the Hierarchy view of the ISE design suite.

2. Double click Export Hardware Design To SDK with Bitstream

3. In the workspace launcher, select the appropriate workspace:

TX: <unzip dir>\kc705_smpte2022_56_3ch_tx\SW\SDK_workspace

RX: <unzip dir>\kc705_smpte2022_56_3ch_rx\SW\SDK_workspace

4. Click OK.

5. Import the board support package (BSP), hardware platform, and software applications into the workspace by selecting File > Import > General > Existing Projects.

6. Click Next, then browse to the appropriate directory:

TX: <unzip dir>\kc705_smpte2022_56_3ch_tx\SW

RX: <unzip dir>\kc705_smpte2022_56_3ch_rx\SW

7. Click OK.

8. Ensure that all check boxes are selected.

9. Click Finish.

The BSP and software applications compile in this step. The process takes two to five minutes. Existing software applications can now be modified and new software applications created with the SDK tools.

Update Bitstream in XPS to include the ELF file1. Open the appropriate XMP project file with the XPS tool:

TX: <unzip dir>\kc705_smpte2022_56_3ch_tx\HW\TOP\peripheral\system_basic\

system_basic.xmp

RX: <unzip dir>\kc705_smpte2022_56_3ch_rx\HW\TOP\peripheral\system_basic\system_basic.xmp

2. Add the ELF file from SDK_Workspace into the XPS tool project by selecting Project > Select Elf File… and, in the Choose Implementation ELF file dialog, select the appropriate ELF file:

TX: <unzip dir>\kc705_smpte2022_56_3ch_tx\SW\SDK_workspace\voip_tx\Debug\voip_tx.elf

RX: <unzip dir>\kc705_smpte2022_56_3ch_rx\SW\SDK_workspace\voip_rx\Debug\voip_rx.elf

3. Select Device Configuration > Update Bitstream to initialize the block RAM with a bootloop program. This ensures that the processor boots with a stable program in memory. The updated bitstream is placed in the appropriate directory:

TX: <unzip dir>\kc705_smpte2022_56_3ch_tx\HW\TOP\peripheral\system_basic\

implementation\download.bit

Discontinued IP


Building Hardware


RX: <unzip dir>\kc705_smpte2022_56_3ch_rx\HW\TOP\peripheral\system_basic\

implementation\download.bit

Running the Hardware and Software through SDK1. Open the JTAG configuration tool as shown in Figure 14 by selecting Xilinx Tools >

Configure JTAG Settings.

2. Select Digilent USB Cable in the type field.

3. Select Automatically Discover Devices on JTAG Chain

Note: Two workstations might be necessary, one for TX and another for RX when running from the SDK tools since the debugger can only connect to a single Digilent USB cable at a time.

4. Click OK

5. Select Xilinx Tools > Program FPGA.

Note: Ensure bootloop is used for microblaze_0.

6. Click Program.

7. In the Project Explorer window, right click and select the appropriate function:

TX: voip_tx_main > Run As > Launch on Hardware

RX: voip_rx_main > Run As > Launch on HardwareX-Ref Target - Figure 14

Figure 14: JTAG Configuration Settings

X896_14_120712

Discontinued IP


Design Characteristics


Design Characteristics

The reference design is implemented in a Kintex-7 FPGA (XC7K325T-2FFG900) using ISE Design Suite: System Edition 14.4. Resource utilization values are shown in Table 7 and Table 8.

Note: Device resource utilization results depend on the implementation tool versions. Exact results can vary. These values should be used as a guideline.

Reference Design

The reference design check list is shown in Table 9. The reference design files for this application note can be downloaded from:

http://www.xilinx.com/member/smpte2022/index.htm

Table 7: Resources Used for V_SMPTE2022_56_TX Platform per Summary Report

Item Resources Used

LUTs 46,786 out of 203,800 (22%)

I/Os 163 out of 500 (32%)

RAMB36E1s 91 out of 445 (21%)

RAMB18E1s 13 out of 890 (1%)

Table 8: Resources Used for V_SMPTE2022_56_RX Platform per Summary Report

Item Resources Used

LUTs 45,752 out of 150,720 (23%)

I/Os 163 out of 500 (32%)

RAMB36E1s 107 out of 445 (24%)

RAMB18E1s 15 out of 890 (1%)

Table 9: Reference Design Check List

Parameter Description

General

Developer names Gilbert Magnaye, Josh Poh, Myo Tun Aung, Tom Sun

Target devices Kintex-7 FPGA

Source code provided Yes

Source code format VHDL (some sources encrypted)

Design uses code/IP from existing Xilinx application note/reference designs, CORE Generator software, or third party

Cores generated from EDK and from Core Generator tool

Simulation

Functional simulation performed N/A

Timing simulation performed N/A

Test bench used for functional and timing simulations N/A

Test bench format N/A

Simulator software/version used N/A

SPICE/IBIS simulations N/A

Implementation

Synthesis software tools/version used XST 14.4

Discontinued IP

http://www.xilinx.com/member/smpte2022/index.htm


Reference Design


Table 10 and Table 11 are extracted from the module utilization report of the design summary from the ISE design suite.

Implementation software tools/versions used ISE Design Suite 14.4; System Edition

Static timing analysis performed Yes (Passing timing in PAR/TRCE)

Hardware Verification

Hardware verified Yes

Hardware platform used for verification Kintex-7 FPGA KC705 Evaluation Kit

Table 9: Reference Design Check List (Cont’d)

Parameter Description

Table 10: V_SMPTE2022_56_TX Device Utilization

Module Name Slices Slice Registers LUTs LUTRAM

Block RAM/ FIFO

DSP48E1 BUFG BUFIO BUFR

VoIP_Framework_TX_IOB 1 0 1 0 0 0 1 0 0

LMH0387ctrl 38 84 106 24 1 0 0 0 0

Si5324CTRL 50 101 119 24 2 0 0 0 0

Video Over IP 13052 28375 27238 767 69 0 8 0 0

-i_kc705_sdi_wrapper 0 0 0 0 0 0 3 0 0

>>SDI_GTX 0 0 0 0 0 0 0 0 0

>>gen_sdi_rxtx[0].SDI_RXTX_i 679 1007 1660 13 1 0 0 0 0



-i_v_smpte2022_56_tx 7829 18665 15398 151 66 0 1 0 0

-ten_gig_block 29 150 21 0 0 0 0 0 0

>>GEN_10BASER.i_10baseR_pcs_pma 1334 2839 3007 210 0 0 4 0 0

>>xgmac_block 1798 3654 3780 377 0 0 0 0 0

VoIP_Framework_TX_IOB 2 0 3 0 0 0 0 0 0

system_basic 10508 23630 19319 2611 32 3 3 0 0

-RS232_Uart_1 65 81 88 18 0 0 0 0 0

-axi4lite_0 177 89 190 0 0 0 0 0 0

-axi_7series_ddrx_0 8048 17389 15022 2411 0 0 0 0 0

-axi_interconnect_0 1219 4920 2477 6 0 0 0 0 0

-axilite_bridge 6 0 10 0 0 0 0 0 0

-clock_generator 1 0 1 0 0 0 2 0 0

-debug_module 85 128 131 23 0 0 1 0 0

-microblaze 876 982 1372 151 0 3 0 0 0

-microblaze_bram_block 0 0 0 0 32 0 0 0 0

-microblaze_d_bram_ctrl 6 2 4 0 0 0 0 0 0

-microblaze_dlmb 1 1 0 0 0 0 0 0 0

Discontinued IP


Reference Design


-microblaze_i_bram_ctrl 4 2 2 0 0 0 0 0 0

-microblaze_ilmb 1 1 0 0 0 0 0 0 0

-proc_sys_reset 19 35 22 2 0 0 0 0 0

Total 23651 52190 46786 3426 104 3 12 0 0

Table 10: V_SMPTE2022_56_TX Device Utilization (Cont’d)


Block RAM/ FIFO


Table 11: V_SMPTE2022_56_RX Device Utilization


Block RAM/FIFO


VoIP_Framework_RX_IOB 9 13 28 0 0 0 1 0 0

LMH0387ctrl 43 81 106 24 1 0 0 0 0

Si5324CTRL 48 99 119 24 2 0 0 0 0

VoIP_Framework_RX_IOB 2 0 3 0 0 0 0 0 0

i_VoIP_Framework_RX 12781 29670 25522 1099 87 0 8 0 0

-gen_clock_recovery[0].i_clock_recovery 307 665 809 49 0 0 0 0 0



-i_kc705_sdi_wrapper 2 1 2 1 0 0 3 0 0

>>SDI_GTX 0 0 0 0 0 0 0 0 0




-v_smpte2022_56_rx_v2_1 7743 18228 14166 311 87 0 1 0 0

-ten_gig_block 28 150 29 0 0 0 0 0 0

>>GEN_10BASER.i_10baseR_pcs_pma 1334 2829 2970 210 0 0 4 0 0

>>xgmac_block 1683 3508 3549 416 0 0 0 0 0

system_basic 10734 24988 19974 2611 32 3 3 0 0

-RS232_Uart_1 57 81 95 18 0 0 0 0 0

-axi4lite_0 166 89 192 0 0 0 0 0 0

-axi_7series_ddrx_0 8079 17419 15051 2411 0 0 0 0 0

-axi_interconnect_0 1433 6248 3071 6 0 0 0 0 0

-axilite_bridge 7 0 10 0 0 0 0 0 0

-clock_generator 1 0 1 0 0 0 2 0 0

-debug_module 98 128 118 23 0 0 1 0 0

-microblaze 863 982 1408 151 0 3 0 0 0

-microblaze_bram_block 0 0 0 0 32 0 0 0 0

-microblaze_d_bram_ctrl 5 2 4 0 0 0 0 0 0

Discontinued IP


Conclusion


Conclusion This application note describes a Video over IP network system using various Xilinx IP cores. The Reference Design demonstrates the ability of the SMPTE 2022-5/6 video over IP cores to encapsulate and de-encapsulate multiple SDI streams and transport them through a 10 Gb/s Ethernet pipe. The utilization of the Ethernet bandwidth is over 90% with three 3G-SDI video streams. The Reference Design can perform recovery of a limited number of Ethernet packets when impairment is introduced into the network with the forward error correction engine turned on.

References This application note uses these references:

1. Kintex-7 FPGA KC705 Evaluation Kit :

www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm

2. Inrevium TB-FMCH-3GSDI2A,

solutions.inrevium.com/products/fmc/serial_connectivity/index.html

3. PG032, LogiCORE IP SMPTE 2022-5/6 Video over IP Transmitter v2.1 Product Guide

4. XAPP589, All Digital VCXO Replacement for Gigabit Transceiver Applications Application Note

5. PG033, LogiCORE IP SMPTE 2022-5/6 Video over IP Receiver v2.1 Product Guide

6. PG071, LogiCORE IP SMPTE SD/HD/3G-SDI v1.0 Product Guide

7. PG072, LogiCORE IP 10-Gigabit Ethernet MAC v11.4 Product Guide

8. PG068, LogiCORE 10-Gigabit Ethernet PCS/PMA v2.5 Product Guide

9. UG761, AXI Reference Guide

10. UG586, 7 Series FPGAs Memory Interface Solutions User Guide

11. AMBA AXI4 specifications,

infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.amba/index.html

12. UG683, EDK Concepts, Tools, and Techniques: A Hands-On Guide to Effective Embedded System Design (v14.4)

Revision History

The following table shows the revision history for this document.

-microblaze_dlmb 1 1 0 0 0 0 0 0 0

-microblaze_i_bram_ctrl 3 2 2 0 0 0 0 0 0

-microblaze_ilmb 1 1 0 0 0 0 0 0 0

-proc_sys_reset 20 35 22 2 0 0 0 0 0

Total 23617 54851 45752 3758 122 3 12 0 0

Table 11: V_SMPTE2022_56_RX Device Utilization (Cont’d)


Block RAM/FIFO


Date Version Description

03/07/2013 1.0 Initial Xilinx release.

Discontinued IP


http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm

http://solutions.inrevium.com/products/fmc/serial_connectivity/index.html

http://www.xilinx.com/support/documentation/ip_documentation/v_smpte2022_56_tx/v1_0/pg032_v_smpte2022_56_tx.pdf

http://www.xilinx.com/support/documentation/ip_documentation/v_smpte_sdi/v1_0/pg071-v-smpte-sdi.pdf

http://www.xilinx.com/support/documentation/ip_documentation/ten_gig_eth_mac/v11_4/pg072-ten-gig-eth-mac.pdf

http://www.xilinx.com/support/documentation/ip_documentation/ten_gig_eth_pcs_pma/v2_5/pg068-ten-gig-eth-pcs-pma.pdf

http://www.xilinx.com/support/documentation/ip_documentation/axi_ref_guide/v14_1/ug761_axi_reference_guide.pdf

http://www.xilinx.com/support/documentation/ip_documentation/ug586_7Series_MIS.pdf

http://www.xilinx.com/support/documentation/ip_documentation/v_smpte2022_56_rx/v1_0/pg033_v_smpte2022_56_rx.pdf

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.amba/index.html

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/edk_ctt.pdf

http://www.xilinx.com/support/documentation/application_notes/xapp589-VCXO.pdf

Notice of Disclaimer


Notice of Disclaimer

The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use ofXilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "ASIS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OFMERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2)Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory ofliability) for any loss or damage of any kind or nature related to, arising under, or in connection with, theMaterials (including your use of the Materials), including for any direct, indirect, special, incidental, orconsequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damagesuffered as a result of any action brought by a third party) even if such damage or loss was reasonablyforeseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation tocorrect any errors contained in the Materials or to notify you of updates to the Materials or to productspecifications. You may not reproduce, modify, distribute, or publicly display the Materials without priorwritten consent. Certain products are subject to the terms and conditions of the Limited Warranties whichcan be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and supportterms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to befail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability foruse of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps.

Automotive Applications DisclaimerXILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANYAPPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I)THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFEOR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINXDEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THEOPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMERASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCHAPPLICATIONS.

Discontinued IP


http://www.xilinx.com/warranty.htm

http://www.xilinx.com/warranty.htm#critapps

Xilinx - Application Note: Kintex-7 FPGAs SMPTE2022-5/6 ......Hardware System Specifics XAPP896 (v1.0) March 7, 2013 6 SMPTE 2022-5/6 Video Over IP Receiver The SMPTE 2022-5/6 video

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