XFEL Meeting, RAL XFEL Meeting, RAL 20 January 2011 20 January 2011 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing Wing XFEL 2D Pixel Clock and Control System XFEL 2D Pixel Clock and Control System
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XFEL Meeting, RAL 20 January 2011 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System.
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XFEL Meeting, RAL XFEL Meeting, RAL
20 January 201120 January 2011
Erdem Motuk, Martin Postranecky, Matt Warren, Matthew WingErdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing
XFEL 2D Pixel Clock and Control SystemXFEL 2D Pixel Clock and Control System
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OUTLINEOUTLINE
• Progress up to dateProgress up to date
• Hardware StructureHardware Structure
• Firmware structure Firmware structure
• Current StatusCurrent Status
• Outstanding IssuesOutstanding Issues
• Future plansFuture plans
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Progress up to dateProgress up to date
• Acquired software and licence for Allegro ConceptHDLAcquired software and licence for Allegro ConceptHDL– Design flow established – The first run slightly slow – improved for Design flow established – The first run slightly slow – improved for
othersothers
– Schematic design and packaging at UCL – Layout at RALSchematic design and packaging at UCL – Layout at RAL
• Test card A design Test card A design – Schematic entry/layout finished – Named PC3461MSchematic entry/layout finished – Named PC3461M
– In the manufacturing and assembly stage In the manufacturing and assembly stage
• RTM design has startedRTM design has started– Schematic entry startedSchematic entry started
• xTCA crate has been purchased xTCA crate has been purchased – Set up and running with SLCSet up and running with SLC
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Progress up to dateProgress up to date
• Firmware design on the development platformFirmware design on the development platform– Telegram transmit/receiveTelegram transmit/receive
– FAST message transmit/receiveFAST message transmit/receive
– Test BenchTest Bench• Firmware comprising all transmit/receive blocksFirmware comprising all transmit/receive blocks
• Transmit can be started by external input (push-button or ChipScope VIO)Transmit can be started by external input (push-button or ChipScope VIO)
• Results can be observed by ChipScopeResults can be observed by ChipScope
– PCIePCIe• Development card can be accessed through PCIeDevelopment card can be accessed through PCIe
PCM3461 Assembly drawing top and bottom sidesPCM3461 Assembly drawing top and bottom sides
RECEIVE
TRANSMIT
Test / Prototyping
area
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Hardware StructureHardware Structure
• PC3461M to be used forPC3461M to be used for– FAST message transmit/receive testing (via ETH cables)FAST message transmit/receive testing (via ETH cables)
– Available for others to use (with the XUPV5 development board)Available for others to use (with the XUPV5 development board)
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Hardware StructureHardware Structure
• Prototype RTM to test with the DAMC2 board in the xTCA Prototype RTM to test with the DAMC2 board in the xTCA cratecrate– Early prototype availability for the systemEarly prototype availability for the system
– Diagnosing bugs/gotchas with the designDiagnosing bugs/gotchas with the design
– Later revision to add more capabilityLater revision to add more capability
– Prototyping platformPrototyping platform
for extra features if needed for extra features if needed
– Tests to be carried out Tests to be carried out
in the actual setup (xTCA crate)in the actual setup (xTCA crate)
RJ4
5 CO
NN
EC
TO
RS
(8/16)
LVD
S
DR
IVE
RS
LVD
S
RE
CE
IVE
CLOCK / PLL
I2C / EEPROM
POWER
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Firmware StructureFirmware Structure• A test firmware that integrates transmit/receive and other A test firmware that integrates transmit/receive and other
featuresfeatures– One bit file to program the FPGAs on the dev boardsOne bit file to program the FPGAs on the dev boards
– ChipScope cores associated with each blockChipScope cores associated with each block
• Firmware diagram – Finished blocks + extras for testFirmware diagram – Finished blocks + extras for testClocking implemented according
Two packet structures for data and eventsTwo packet structures for data and events Start Byte (x2C) + Write_Type + CRC (for events)Start Byte (x2C) + Write_Type + CRC (for events)
• Programmable memory read/write functionality in firmwareProgrammable memory read/write functionality in firmware
• A simple driver written for LinuxA simple driver written for Linux
• A simple application to access registers on the FPGAA simple application to access registers on the FPGA
• To read/write Train_no and Bunch_Pattern_IdTo read/write Train_no and Bunch_Pattern_Id
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Firmware StructureFirmware Structure
Fast Message TransmitFast Message Transmit• Implemented according to the specsImplemented according to the specs
• Simple XOR checksumSimple XOR checksum
Register blockRegister block• Different registers for different sourcesDifferent registers for different sources
– PCIe and telegram data at the moment
• Multiplexes between different sources for FAST message transmitMultiplexes between different sources for FAST message transmit
External TriggerExternal Trigger• Buttons on the boardButtons on the board
• Start / Stop / ResetStart / Stop / Reset
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Current StatusCurrent Status• C&C firmwareC&C firmware
– Fast Message Generation – Start and Stop messagesFast Message Generation – Start and Stop messages
– Telegram receive Telegram receive
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Current StatusCurrent Status
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Current StatusCurrent Status
TEST SETUPTEST SETUP
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Outstanding IssuesOutstanding Issues
– Telegram transmit/receive testing and feedbackTelegram transmit/receive testing and feedback• Further development / debuggingFurther development / debugging
– RTM designRTM design• Exact dimensions of the RTM card Exact dimensions of the RTM card
• DAMC2 schematic or a manual neededDAMC2 schematic or a manual needed
• Any experience / useful to know bitsAny experience / useful to know bits
– TR and DAMC2 availabilityTR and DAMC2 availability
– xTCA cratexTCA crate• Operating system / device driversOperating system / device drivers
• Any gotchas / experience with the crateAny gotchas / experience with the crate
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ScheduleSchedule
• PC3461M ready PC3461M ready
– Initial testing with the cardInitial testing with the card
– Card made availableCard made available
• RTM designRTM design
– Schematic captureSchematic capture
– LayoutLayout
– ManufacturingManufacturing
• Further firmware debug / developmentFurther firmware debug / development
– With the DAMC2 boardWith the DAMC2 board
– With the TR boardWith the TR board
– In the xTCA crateIn the xTCA crate
– VETO logic VETO logic
February 2011February 2011February 2011February 2011March 2011March 2011