Tokyo Electron (TEL) Overview C2 東京エレクトロン(TEL)の事業概要 Global TEL 1 TEL の世界展開 Industry Data 2 インダストリー・データ Roles and Architecture of 4 Semiconductor Devices 半導体デバイスの役割と構造 Semiconductor Device Miniaturization 5 and Clean Technology 半導体デバイスの微細化とクリーン化技術 Semiconductor & TFT-LCD/OLED Panel 6 Manufacturing Process Flow 半導体製造プロセスおよび TFT-LCD ・有機 EL パネル製造プロセス Consolidated Operating Results 8 連結業績 FACT BOOK 2019 TOKYO ELECTRON As of March 31, 2019 CONTENTS 目次 Semiconductor 10 Production Equipment (SPE) Sales 半導体製造装置売上高 Consolidated Financial Data 11 連結財務データ Consolidated Balance Sheets 16 連結貸借対照表 Consolidated Statements of Operations 18 連結損益計算書 Consolidated Statements of 18 Comprehensive Income 連結包括利益計算書 Consolidated Statements of Cash Flows 19 連結キャッシュ・フロー計算書 Stock Information 20 株式情報 東京エレクトロン ファクトブック2019
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Tokyo Electron(TEL) Overview C2東京エレクトロン(TEL)の事業概要
Global TEL 1TELの世界展開
Industry Data 2インダストリー・データ
Roles and Architecture of 4Semiconductor Devices半導体デバイスの役割と構造
Consolidated Statements of 18Comprehensive Income連結包括利益計算書
Consolidated Statements of Cash Flows 19連結キャッシュ・フロー計算書
Stock Information 20株式情報
東京エレクトロン ファクトブック2019
World HeadquartersAkasaka Biz Tower3-1 Akasaka 5-chome, Minato-kuTokyo 107-6325, JapanTel. +81-3-5561-7000www.tel.com
Printed on recycled paper.本誌は再生紙を使用しています。
Printed in JapanPR57-112
005_0454002471906.indd 2 2019/06/01 3:34:11
FPD Production EquipmentFPD (フラットパネルディスプレイ) 製造装置
FPD: Flat Panel Display
■ Corporate Information 会社概要
Tokyo Electron (TELTM) Overview 東京エレクトロン(TELTM)の事業概要
■ Composition of Net Sales by Segment セグメント別売上構成比
Fiscal year ended March 31, 20192019年3月期
Corporate Name Tokyo Electron Limited商号 東京エレクトロン株式会社 World Headquarters Akasaka Biz Tower, 3-1 Akasaka 5-chome,本社所在地 Minato-ku, Tokyo, Japan 東京都港区赤坂5-3-1 赤坂Bizタワー Established November 11, 1963 設立 1963年11月11日 Capital ¥54.9 Billion (as of March 31, 2019) 資本金 549億円(2019年3月31日現在)
• Tokyo Electron Technology Solutions Ltd. 東京エレクトロン テクノロジーソリューションズ㈱• Tokyo Electron Kyushu Ltd. 東京エレクトロン九州㈱• Tokyo Electron Miyagi Ltd. 東京エレクトロン宮城㈱• Tokyo Electron FE Ltd. 東京エレクトロンFE㈱• Tokyo Electron BP Ltd. 東京エレクトロンBP㈱• Tokyo Electron Agency Ltd. 東京エレクトロンエージェンシー㈱
• Tokyo Electron U.S. Holdings, Inc.
• Tokyo Electron America, Inc.
• TEL Technology Center, America, LLC
• TEL Venture Capital, Inc.
• TEL Epion Inc.
• TEL FSI, Inc.
• Tokyo Electron Europe Ltd.
• Tokyo Electron Israel Ltd.
• TEL Magnetic Solutions Ltd.
• Tokyo Electron Korea Ltd.
• Tokyo Electron Taiwan Ltd.
• Tokyo Electron (Shanghai) Ltd.
• Tokyo Electron (Kunshan) Ltd.
• Tokyo Electron Singapore Pte. Ltd.
Tokyo Electron Ltd.東京エレクトロン(株)
■ Tokyo Electron and its Consolidated Subsidiaries 東京エレクトロンと連結子会社As of March 31, 2019(2019年3月31日現在)
Number of consolidated subsidiaries : Total of 33 including the 20 below連結子会社数:下記20社含め計33社
Source 出典:VLSI Research, June 2019Source 出典:*1 IHS Markit, Application Market Forecast Tool AMFTTM, Q1 2019 Results are not an endorsement of Tokyo Electron Limited. Any reliance on these results is at the third party’s own risk. Visit technology.ihs.com for more details.
*2 WSTS *3 SEAJ, SEMI, SEMI Japan
アプライド マテリアルズ
エーエスエムエル
東京エレクトロン
ラムリサーチ
ケーエルエー・テンコール
アドバンテスト
SCREENセミコンダクターソリューションズ
テラダイン
KOKUSAI ELECTRIC
日立ハイテクノロジーズ 1.40
1.48
1.49
2.22
2.57
4.24
10.87
10.91
12.81
14.01Applied Materials
ASML
Tokyo Electron
Lam Research
KLA-Tencor
Advantest
SCREEN Semiconductor Solutions
Teradyne
KOKUSAI ELECTRIC
Hitachi High-Technologies
(US$ Billion 十億ドル)World Electronic Equipment
Production Market*1
世界電子機器市場US$2,359B
World Semiconductor Market*2
世界半導体市場US$469B
2018
World Electronic Equipment Production Market*世界電子機器市場
World Wafer Processing Equipment Market世界ウェーハプロセス用処理装置市場
Source 出典: IHS Markit, Application Market Forecast Tool AMFTTM, Q1 2019 Results are not an endorsement of Tokyo Electron Limited. Any reliance on these results is at the third party’s own risk. Visit technology.ihs.com for more details.
4 Roles and Architecture of Semiconductor Devices 半導体デバイスの役割と構造Roles of semiconductor device and architecture 半導体デバイスの役割と構造2
MPU/Logic
Data processing
DRAM
CMOS image sensor
3D NAND
Semiconductor devices come in many types, each with a specific role. Microprocessor units (MPUs) and logic devices are responsible for data processing, much like the human brain. DRAM is like a whiteboard or memo pad for temporarily holding information. NAND flash memory is like a library, storing huge amounts of information. Like the eyes, CMOS image sensors obtain visual information. The architecture of semiconductor devices is very much dependent on the device’s role in computing and varies greatly, requiring highly diverse fabrication process technologies.
Miniaturization of semiconductor devices and clean technology 半導体デバイスの微細化とクリーン化技術 3
Miniaturization enhances the performance and density of semiconductor devices. The fabrication technologies that produce state-of-the-art semiconductor devices require atomic-level control and extreme cleanliness. In the case of logic devices, for instance, 20 trillion transistors* are fabricated in neat rows on a silicon wafer 300 millimeters across. Fins—the smallest constituent features of transistors—are just eight nanometers wide (for reference, one nanometer is equivalent to one billionth of a meter). Fabricating fins on a silicon wafer is thus comparable to fabricating and correctly positioning 20 trillion elements the size of a human red blood cell on the Maracanã Stadium in Rio de Janeiro. On top of that, in order to maintain high yield, no more than 10 foreign particles larger than 15 nanometers can be allowed in that space. A particle of this size on a 300-millimeter silicon wafer is roughly proportional to half a grain of cypress pollen on the Maracanã Stadium.
Nanowire FET, which consists of less than twenty atoms in length, is likely to be introduced at the 5nm generation or beyond.
原子十数個分の幅で構成されるナノワイヤトランジスタは、5nm世代以降での採用が予想されます。
μm nm Å
1 mm 100μm 10μm
6~8μm
1μm 100nm
WaferΦ300mm
Maracanã Stadium in Rio de Janeiroリオデジャネイロ マラカナン競技場
298×260m
Transistorトランジスタ
×20 trillion×20兆個
10nm 1nm
* Transistor: A semiconductor device used to amplify or switch electronic signals and electrical power*トランジスタ:電気信号の増幅やスイッチ動作をさせる半導体素子
** FET: Field e�ect transistor
Nanowire FET**
=
× 1,000
Red blood cell赤血球
×20 trillion×20兆個
WaferΦ300mm
Maracanã Stadium in Rio de Janeiroリオデジャネイロ マラカナン競技場
298×260m
Particleパーティクル
Particleパーティクル FinFET**
Fewer than 1010個以下
=
Cedar pollenスギ花粉
Influenza virusインフルエンザウィルス
Transistorトランジスタ DNA
Atom原子
Red blood cell赤血球
Fewer than 1010個以下
30μm
6~8μm 100nm 2.5nm
30μm(÷2)
8nm
15nm
8nm
15nm200nm
Source 出典: Intel Corporation
Half a grain of cypress pollenスギ花粉の半分程度
2018.04.11[TEL] Branding Project
FACT BOOK 2018 一部改訂サイズ:W280 x H215mm
右ページ ※ノンブルはダミーです。確定し次第、差し替えをお願いします。
sp010_0454002471906.indd 4 2019/07/05 17:11:39
5Roles and Architecture of Semiconductor Devices 半導体デバイスの役割と構造 Semiconductor Device Miniaturization and Clean Technology 半導体デバイスの微細化とクリーン化技術Roles of semiconductor device and architecture 半導体デバイスの役割と構造2
MPU/Logic
Data processing
DRAM
CMOS image sensor
3D NAND
Semiconductor devices come in many types, each with a specific role. Microprocessor units (MPUs) and logic devices are responsible for data processing, much like the human brain. DRAM is like a whiteboard or memo pad for temporarily holding information. NAND flash memory is like a library, storing huge amounts of information. Like the eyes, CMOS image sensors obtain visual information. The architecture of semiconductor devices is very much dependent on the device’s role in computing and varies greatly, requiring highly diverse fabrication process technologies.
Miniaturization of semiconductor devices and clean technology 半導体デバイスの微細化とクリーン化技術 3
Miniaturization enhances the performance and density of semiconductor devices. The fabrication technologies that produce state-of-the-art semiconductor devices require atomic-level control and extreme cleanliness. In the case of logic devices, for instance, 20 trillion transistors* are fabricated in neat rows on a silicon wafer 300 millimeters across. Fins—the smallest constituent features of transistors—are just eight nanometers wide (for reference, one nanometer is equivalent to one billionth of a meter). Fabricating fins on a silicon wafer is thus comparable to fabricating and correctly positioning 20 trillion elements the size of a human red blood cell on the Maracanã Stadium in Rio de Janeiro. On top of that, in order to maintain high yield, no more than 10 foreign particles larger than 15 nanometers can be allowed in that space. A particle of this size on a 300-millimeter silicon wafer is roughly proportional to half a grain of cypress pollen on the Maracanã Stadium.
Nanowire FET, which consists of less than twenty atoms in length, is likely to be introduced at the 5nm generation or beyond.
原子十数個分の幅で構成されるナノワイヤトランジスタは、5nm世代以降での採用が予想されます。
μm nm Å
1 mm 100μm 10μm
6~8μm
1μm 100nm
WaferΦ300mm
Maracanã Stadium in Rio de Janeiroリオデジャネイロ マラカナン競技場
298×260m
Transistorトランジスタ
×20 trillion×20兆個
10nm 1nm
* Transistor: A semiconductor device used to amplify or switch electronic signals and electrical power*トランジスタ:電気信号の増幅やスイッチ動作をさせる半導体素子
** FET: Field e�ect transistor
Nanowire FET**
=
× 1,000
Red blood cell赤血球
×20 trillion×20兆個
WaferΦ300mm
Maracanã Stadium in Rio de Janeiroリオデジャネイロ マラカナン競技場
298×260m
Particleパーティクル
Particleパーティクル FinFET**
Fewer than 1010個以下
=
Cedar pollenスギ花粉
Influenza virusインフルエンザウィルス
Transistorトランジスタ DNA
Atom原子
Red blood cell赤血球
Fewer than 1010個以下
30μm
6~8μm 100nm 2.5nm
30μm(÷2)
8nm
15nm
8nm
15nm200nm
Source 出典: Intel Corporation
Half a grain of cypress pollenスギ花粉の半分程度
2018.04.11[TEL] Branding Project
FACT BOOK 2018 一部改訂サイズ:W280 x H215mm
右ページ ※ノンブルはダミーです。確定し次第、差し替えをお願いします。
sp010_0454002471906.indd 5 2019/07/05 17:11:40
6 Semiconductor & TFT-LCD/OLED Panel Manufacturing Process Flow 半導体製造プロセスおよびTFT-LCD・有機ELパネル製造プロセス
The front-end process for FPD production (known as the TFT array process) is similar to the semiconductor manufacturing process.FPD製造の要となる前工程(TFTアレイプロセス)も、半導体の製造プロセスとほぼ同様のステップを踏みます。
Packaging/Assemblyパッケージング・組み立て
Inspection検査
Wafer Bonding/Thinning/Debonding支持基板貼り合わせ・薄化・剥離
Wafer Probe Testingウェーハ検査
Interconnect Formation多層配線形成
Contact Formationコンタクト形成
Semiconductor Manufacturing Process 半導体製造プロセス
Waferウェーハ
Silicondioxide filmシリコン酸化膜
Siliconnitride filmシリコン窒化膜
Module process
モジュールプロセス
TFT=Thin Film Transistor TFT-LCD Panel
Glasssubstrateガラス基板
TFT array process TFTアレイプロセス
Wafer process (Front-end) ウェーハ処理プロセス(前工程)
FPD Coater/DeveloperFPDコータ/デベロッパ
Exceliner™
FPD Plasma Etch/Ash SystemFPDプラズマエッチング/アッシング装置
Betelex™
Inkjet printing system for manufacturing OLED panels有機ELパネル製造用インクジェット描画装置
Elius™
Displayディスプレイ
Bac
k lig
ht
ITO
ITO
Pola
rize
r Filt
er
Alig
nmen
t La
yer
Liqu
id C
ryst
al
Alig
nmen
t La
yer
ITO
Ele
ctro
deO
ver C
oat
GB
BMBM
BMR
Gla
ss(C
olor
Filt
er S
ide)
Gla
ss(T
FT A
rray
Sid
e)
Pola
rize
r Filt
er
ITO
TFT
TFT
TFT
Color Filter TFT Array Substrate
Photoresist coating
フォトレジスト塗布Exposure
露光Development
現像Etching
エッチングAshing
レジスト剥離Cleaning
洗浄TFT array inspection
TFTアレイ検査Deposition
成膜
OLED Panel
Ano
deA
node
Hol
e In
ject
ion
laye
rH
ole
Tran
sfer
laye
r
Cat
hode
laye
rEl
ectr
on In
ject
ion
laye
rEl
ectr
on T
rans
fer l
ayer
Enca
psul
atio
n
Cov
er G
lass
Gla
ss(T
FT A
rray
Sid
e)
Ano
de
TFT
TFT
TFT
TFT Array SubstrateEmissive Layer(Top Emission)
GB
R
Assembly and Test process (Back-end) 検査・組み立てプロセス(後工程)
Cell process
セルプロセスModule process
モジュールプロセスColor filter process
カラーフィルタプロセス
Encapsulation
封止Display
ディスプレイOLED layer formation
有機EL層成膜
Isolation Formation, Gate Formation素子分離形成、ゲート形成
Gate Electrodeゲート電極
Intermetaldielectric film層間絶縁膜
Metal film金属膜
Metal film金属膜
LCD panel LCDパネル
OLED panel 有機ELパネル
Logic
DRAM
CMOS image sensor
3D NAND
Completed integrated Circuit集積回路の完成
CompletedSemiconductor Packaging半導体パッケージングの完成
Thin films such as silicon dioxide, silicon nitride and others are deposited by thermal oxidation, CVD* and/or ALD** on the wafer surface.
While the wafer is rotated at a high speed, a thin layer of photoresist is coated uniformly on its surface.
ウェーハを高速回転させながら、フォトレジストをウェーハ全面に薄く、均一に塗布します。
*Photoresist: a light-sensitive material that changes its properties when exposed to ultraviolet (UV) light.
*フォトレジスト: UV光により性質変化が起こる感光材料
Photoresist* coatingフォトレジスト* 塗布
Oxide/Nitride film deposition酸化膜形成・窒化膜形成
Repetition繰り返し
To transfer the integrated circuit pa�ern onto a wafer, an equipment called stepper irradiates UV light on the photoresist layer through a pa�erned photomask aligned over the wafer.
A Plasma etch system removes the exposed dielectric silicon dioxide, silicon nitride and others from the wafer surface according to the remaining photoresist.
In a post-etch process, the residual photoresist is removed, and the wafer is soaked into chemical solvents to remove particles and impurities on the wafer.
Each diced chip is examined whether it can be assembled to the package.
ウェーハから切り出されたチップ一つひとつに対し、良・不良判定をおこないます。
The chips are a�ached to package substrates or lead frames, and are sealed with ceramic or plastic.
良品チップをパッケージ基板、またはリードフレームに接続し、セラミック樹脂などに封入します。
To form wiring that connects individual transistors, first a dielectric (oxide) layer is deposited over the gate layer so another layer of circuit can be laid on top. Contact holes (vias) are then opened in the dielectric layer, and are filled with metal by CVD.
Another dielectric layer is deposited on top, in which trenches are etched to form yet another wiring pa�ern. The trenches are filled with a metal film, and then the excess metals are polished and the surface is planarized. These processes are repeated to make a multi level interconnect.
Each integrated circuit is tested by a wafer prober to find any failed circuits.
完成された集積回路の一つひとつに検査針を当て良・不良判定をおこないます。
A�er fabricating redistribution layers and bump electrodes, a support substrate may be temporarily bonded to the wafer to facilitate thinning, and is then removed by a debonder.
While the wafer is rotated at a high speed, a thin layer of photoresist is coated uniformly on its surface.
ウェーハを高速回転させながら、フォトレジストをウェーハ全面に薄く、均一に塗布します。
*Photoresist: a light-sensitive material that changes its properties when exposed to ultraviolet (UV) light.
*フォトレジスト: UV光により性質変化が起こる感光材料
Photoresist* coatingフォトレジスト* 塗布
Oxide/Nitride film deposition酸化膜形成・窒化膜形成
Repetition繰り返し
To transfer the integrated circuit pa�ern onto a wafer, an equipment called stepper irradiates UV light on the photoresist layer through a pa�erned photomask aligned over the wafer.
A Plasma etch system removes the exposed dielectric silicon dioxide, silicon nitride and others from the wafer surface according to the remaining photoresist.
In a post-etch process, the residual photoresist is removed, and the wafer is soaked into chemical solvents to remove particles and impurities on the wafer.
Each diced chip is examined whether it can be assembled to the package.
ウェーハから切り出されたチップ一つひとつに対し、良・不良判定をおこないます。
The chips are a�ached to package substrates or lead frames, and are sealed with ceramic or plastic.
良品チップをパッケージ基板、またはリードフレームに接続し、セラミック樹脂などに封入します。
To form wiring that connects individual transistors, first a dielectric (oxide) layer is deposited over the gate layer so another layer of circuit can be laid on top. Contact holes (vias) are then opened in the dielectric layer, and are filled with metal by CVD.
Another dielectric layer is deposited on top, in which trenches are etched to form yet another wiring pa�ern. The trenches are filled with a metal film, and then the excess metals are polished and the surface is planarized. These processes are repeated to make a multi level interconnect.
Each integrated circuit is tested by a wafer prober to find any failed circuits.
完成された集積回路の一つひとつに検査針を当て良・不良判定をおこないます。
A�er fabricating redistribution layers and bump electrodes, a support substrate may be temporarily bonded to the wafer to facilitate thinning, and is then removed by a debonder.
Completed Transistor before Wiring配線前のトランジスタ(素子)が完成
Logic
DRAM
3D NAND
CMOS image sensor
sp010_0454002471906.indd 7 2019/07/05 17:11:41
8
Notes: 1. From FY2015, Tokyo Electron Device, which operates the Electronic Components and Computer Networks business, changed from consolidated subsidiary to equity method affiliate.
2. From FY2016, PV production equipment sales are included in others sales.
Consolidated Operating Results 連結業績
Net Sales売上高
Net Sales by Division部門別売上高
Composition of Net Salesby Division部門別売上構成比
TEL’s fiscal year ends on March 31. Each fiscal year described in this document is identified by the year in which it ends. For example, FY2019 is the fiscal year ended March 31, 2019.当社は3月31日を決算日としています。本誌記載の年度は各営業期間の終了した会計年度です。例えば、FY2019は2019年3月31日に終了した会計年度です。
Sales by division represents the sales to customers.部門別売上高は、外部顧客に対する売上高です。
’19
240,000
180,000
120,000
60,000
0
40
30
20
10
0
(¥ Million 百万円) (%)
SG&A expenses 販売費及び一般管理費Ratio to net sales 対売上高比率
’17’15’14 ’16 ’18
800,000
600,000
400,000
200,000
0
60
45
30
15
0
(¥ Million 百万円) (%)
Cost of sales 売上原価Gross profit margin 売上総利益率
’17’15’14 ’16 ’18 ’19
100
75
50
25
0
(%)
’17’15’14 ’16 ’18 ’19
1,600,000
1,200,000
800,000
400,000
0
(¥ Million 百万円)
Semiconductor Production Equipment 半導体製造装置FPD Production Equipment FPD製造装置PV Production Equipment PV製造装置Electronic Components/Computer Networks 電子部品・情報通信機器Others その他
Notes: 1. Segment profit (loss) is based on income (loss) before income taxes. 2. From FY2015, Tokyo Electron Device, which operates the Electronic Components and Computer Networks
business, changed from consolidated subsidiary to equity method affiliate. 3. As PV Production Equipment business has been excluded from reportable segments from FY2016, it is not
presented on the graph and table of segment profit (loss).
Fixed ratio = Fixed assets / Total net assets × 100固定比率=固定資産÷純資産合計×100
Consolidated Financial Data 連結財務データ
Working Capital and Current Ratio運転資本および流動比率
FY年度
(¥ Million 百万円)Working capital
運転資本
(%)Current ratio
流動比率
2014 450,982 364.5
2015 498,070 388.2
2016 451,355 371.8
2017 528,168 313.2
2018 578,144 256.9
2019 678,014 322.4
Working capital = Current assets – Current liabilities運転資本=流動資産-流動負債Current ratio = Current assets / Current liabilities × 100流動比率=流動資産÷流動負債×100
Receivable Turnover 売上債権回転日数
FY年度
(Days 日)Receivable turnover売上債権回転日数
2014 77
2015 66
2016 64
2017 61
2018 52
2019 42
Receivable turnover = Trade notes and accounts receivable at fiscal year-end / Net sales × 365売上債権回転日数=期末受取手形および売掛金÷売上高×365
Inventory Turnoverたな卸資産回転日数
FY年度
(Days 日)Inventory turnoverたな卸資産回転日数
2014 100
2015 105
2016 107
2017 108
2018 111
2019 101
Inventory turnover = Inventories at fiscal year-end / Net sales × 365たな卸資産回転日数=期末たな卸資産÷売上高×365
FY年度
(Times 回)Fixed asset turnover
固定資産回転率
2014 2.66
2015 2.97
2016 3.48
2017 4.47
2018 5.17
2019 4.82
Fixed asset turnover = Net sales / Average fixed assets固定資産回転率=売上高÷期首・期末平均固定資産
Notes: From FY2019, the Company adopts “Partial Amendments to Accounting Standard for Tax Effect Accounting” (ASBJ Statement No. 28, revision on February 16, 2018). “Working capital and current ratio”, “fixed assets and fixed ratio”, and “fixed asset turnover” for FY2018 have been restated in the graphs and tables in accordance with the revised accounting standard.
ROE = Net income (loss) attributable to owners of parent / Average total equity × 100自己資本利益率=親会社株主に帰属する当期純損益 ÷期首・期末平均自己資本×100
FY年度
(¥ Million 百万円)Equity自己資本
2014 578,091
2015 639,483
2016 562,369
2017 643,094
2018 767,146
2019 880,748
Equity = Net assets – Subscription rights to shares – Non-controlling interests自己資本=純資産-新株予約権-非支配株主持分
FY年度
(%)Equity ratio自己資本比率
2014 69.8
2015 73.0
2016 70.9
2017 67.2
2018 63.8
2019 70.0
FY年度
(¥ Million 百万円)Total assets
総資産
2014 828,591
2015 876,153
2016 793,367
2017 957,447
2018 1,202,796
2019 1,257,627
Total asset turnover = Net sales / Average total assets総資産回転率=売上高÷期首・期末平均総資産
FY年度
(Times 回)Total asset turnover
総資産回転率
2014 0.76
2015 0.72
2016 0.80
2017 0.91
2018 1.05
2019 1.04
Notes: From FY2019, the Company adopts “Partial Amendments to Accounting Standard for Tax Effect Accounting” (ASBJ Statement No. 28, revision on February 16, 2018). “Total assets”, “total asset turnover”, and “equity ratio” for FY2018 have been restated in the graphs and tables in accordance with the revised accounting standard.
ROA = (Operating income or loss + Interest and dividend income) / Average total assets × 100
総資産利益率=(営業損益+受取利息および配当金)÷期首・期末平均総資産 ×100
R&D Expenses研究開発費
Capital Expenditures and Depreciation and Amortization設備投資額および減価償却費
FY年度
(¥ Million 百万円)R&D expenses
研究開発費
2014 78,663
2015 71,349
2016 76,286
2017 83,800
2018 97,103
2019 113,980
FY年度
(¥ Million 百万円)Capital expenditures
設備投資額
(¥ Million 百万円)Depreciation and amortization
減価償却費
2014 12,799 24,888
2015 13,183 20,878
2016 13,341 19,257
2017 20,697 17,872
2018 45,603 20,619
2019 49,754 24,323
FY年度
(¥ Million 百万円)Cash on hand
手元資金
2014 268,146
2015 317,682
2016 236,673
2017 315,366
2018 373,877
2019 392,634
Cash on hand = Cash and cash equivalents at the end of the year + Time deposits and short-term investments with maturities over three months手元資金=現金及び現金同等物期末残高+満期日又は償還日までの期間が3ヶ月を超える定期預金および短期投資の残高
Cash on Hand手元資金
’16
400,000
300,000
200,000
100,000
0
(¥ Million 百万円)
’14 ’15 ’17 ’19’18
Notes: 1. Amortization of goodwill is not included in depreciation and amortization. 2. From FY2019, the Company adopts “Partial Amendments to Accounting Standard for Tax Effect Accounting” (ASBJ
Statement No. 28, revision on February 16, 2018). “Return on assets (ROA)” for FY2018 have been restated in the graph and table in accordance with the revised accounting standard.
Capital expenditures 設備投資額 Depreciation and amortization 減価償却費
’14 ’15 ’17 ’18 ’19
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14
Net Income (Loss) per Employee従業員1人当たり当期純損益
Net Sales per Employee従業員1人当たり売上高
Net sales per employee = Net sales / Number of employees worldwide従業員1人当たり売上高=売上高÷従業員数
FY年度
(¥ Million 百万円)Net sales per employee従業員1人当たり売上高
2014 49.8
2015 56.5
2016 62.5
2017 71.1
2018 94.7
2019 100.3
FY年度
(¥ Million 百万円)Net income (loss) per employee
従業員1人当たり当期純損益
2014 (1.6)
2015 6.6
2016 7.3
2017 10.2
2018 17.1
2019 19.5
Net income (loss) per employee = Net income (loss) attributable to owners of parent / Number of employees worldwide従業員1人当たり当期純損益=親会社株主に帰属する当期純損益 ÷従業員数
FY年度
(Persons 人)Number of employees worldwide
従業員数
2014 12,304
2015 10,844
2016 10,629
2017 11,241
2018 11,946
2019 12,742
FY年度
(¥ Million 百万円)Free cash flow
フリーキャッシュフロー
2014 33,392
2015 64,238
2016 60,369
2017 118,022
2018 139,748
2019 149,539
Free Cash Flowフリーキャッシュフロー
(¥ Million 百万円)
FY年度
Cash flow fromoperatingactivities
営業活動によるキャッシュ・フロー
Cash flow frominvestingactivities
投資活動によるキャッシュ・フロー
Cash flow fromfinancingactivities
財務活動によるキャッシュ・フロー
Cash and cashequivalents at
end of year現金及び現金
同等物期末残高
2014 44,449 (19,599) (186) 104,797
2015 71,806 155,737 (18,213) 317,632
2016 69,398 (150,013) (138,600) 95,638
2017 136,948 (28,893) (39,380) 164,366
2018 186,582 (11,833) (82,549) 257,877
2019 189,572 (84,033) (129,761) 232,634
Cash flows from investing activities include changes in time deposits and short-term investments with maturities over three months投資活動によるキャッシュ・フローには、満期日又は償還日までの期間が3ヶ月を超える定期預金および短期投資の増減が含まれています。
Free cash flow = Cash flows from operating activities + Cash flows from investing activities (excluding changes in time deposits and short-term investments with maturities over three months)フリーキャッシュフロー=営業活動によるキャッシュ・フロー+投資活動によるキャッシュ・フロー(満期日又は償還日までの期間が3ヶ月を超える定期預金および短期投資の増減を除く)
’16
20
15
5
0
-5
(¥ Million 百万円)
10
’14 ’15 ’17 ’18 ’19’16 ’17
120
90
60
30
0 ’14 ’15 ’18
(¥ Million 百万円)
’19
Number of Employees Worldwide従業員数
’16
16,000
8,000
12,000
4,000
0
(Persons 人)
’14 ’15 ’17 ’18 ’19’16
200,000
100,000
150,000
50,000
0
(¥ Million 百万円)
’14 ’15 ’17 ’18 ’19
Cash Flowsキャッシュ・フロー
400,000
–200,000
0
200,000
–400,000’14 ’15 ’16 ’17 ’18
Cash flow from operating activities 営業活動によるキャッシュ・フローCash flow from investing activities 投資活動によるキャッシュ・フローCash flow from financing activities 財務活動によるキャッシュ・フローCash and cash equivalents at end of year 現金及び現金同等物期末残高
(¥ Million 百万円)
’19
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15
Net Income (Loss) per Share1 株当たり当期純損益
Cash Flow per Share1 株当たりキャッシュ・フロー
Net Assets per Share1 株当たり純資産
Cash Dividends per Share1 株当たり配当金
Payout Ratio配当性向
Notes: The number of shares outstanding excluding the treasury stock is used for calculation of per share data. 注) 1株当たり指標の計算には自己株式数を控除後の発行済株式数を使用しています。
FY年度
(¥ 円)Net income (loss) per share
1 株当たり当期純損益
2014 (108.31)
2015 401.08
2016 461.10
2017 702.26
2018 1,245.48
2019 1,513.58
Net income (loss) per share = Net income (loss) attributable to owners of parent / Average total number of shares outstanding in each fiscal year
1 株当たり当期純損益=親会社株主に帰属する当期純損益 ÷期中平均発行済株式数
FY年度
(¥ 円)Cash flow per share
1 株当たりキャッシュ・フロー
2014 30.58
2015 517.56
2016 575.10
2017 811.20
2018 1,371.14
2019 1,661.90
Cash flow per share = (Net income or loss attributable to owners of parent + Depreciation and amortization) / Average total number of shares outstanding in each fiscal year
Notes: From FY2019, the Company adopts “Partial Amendments to Accounting Standard for Tax Effect Accounting” (ASBJ Statement No. 28, revision on February 16, 2018). FY2018 results have been restated in the table in accordance with the revised accounting standard.
Total liabilities and net assets 負債及び純資産合計 668,998 696,351 809,205 783,610 775,527 828,591 876,153 793,367 957,447 1,202,796 1,257,627
Notes: 1. From FY2011, the Company adopts “Accounting Standard for Presentation of Comprehensive Income” (June 30, 2010). 2. From FY2014, the Company adopts “Accounting Standard for Retirement Benefits” (May 17, 2012). Accrued pension and severance
costs for or before FY2013 are included in Net liability for defined benefits. 3. From FY2016, the Company adopts “Accounting Standard for Business Combinations” (September 13, 2013), “Accounting Standard for
Consolidated Financial Statements” (September 13, 2013), and “Accounting Standard for Business Divestitures” (September 13, 2013). 4. From FY2019, the Company adopts “Partial Amendments to Accounting Standard for Tax Effect Accounting” (ASBJ Statement No. 28,
revision on February 16, 2018). FY2018 results have been restated in the table in accordance with the revised accounting standard.
Net income (loss) 当期純利益(損失) (8,493) 72,807 37,179 6,358 (19,213) 71,928 77,936 115,248 204,399 248,228
Net income attributable to non-controlling interests 非支配株主に帰属する当期純利益 303 539 883 453 282 195 40 44 39 28 —
Net income (loss) attributable to owners of parent 親会社株主に帰属する当期純利益(損失) 7,543 (9,033) 71,924 36,725 6,076 (19,408) 71,888 77,891 115,208 204,371 248,228
Notes: 1. From FY2011, the Company adopts “Accounting Standard for Presentation of Comprehensive Income” (June 30, 2010). 2. From FY2014, the Company adopts “Accounting Standard for Retirement Benefits” (May 17, 2012). 3. From FY2016, the Company adopts “Accounting Standard for Business Combinations” (September 13, 2013), “Accounting Standard for
Consolidated Financial Statements” (September 13, 2013), and “Accounting Standard for Business Divestitures” (September 13, 2013).
Effect of exchange rate changes on cash and cash equivalents 現金及び現金同等物に係る換算差額 (2,068) 445 (1,009) (299) (5,334) (3,973) 3,505 (2,776) 53 1,312 (1,020)Net increase (decrease) in cash and cash equivalents 現金及び現金同等物の増減額 (127,676) 58,056 41,110 (6,274) (73,462) 20,690 212,835 (221,993) 68,728 93,511 (25,243)Cash and cash equivalents at beginning of year 現金及び現金同等物期首残高 193,492 65,883 123,939 165,050 158,776 85,313 104,797 317,632 95,638 164,366 257,877Effect of newly consolidated subsidiary 新規連結子会社の影響 67 — — — — — — — — — —Increase (decrease) in cash and cash equivalents from changes in fiscal year-end of consolidated subsidiaries 連結子会社の決算期変更に伴う現金及び現金同等物の増減額 — — — — — (1,206) — — — — —Cash and cash equivalents at end of year 現金及び現金同等物期末残高 65,883 123,939 165,050 158,776 85,313 104,797 317,632 95,638 164,366 257,877 232,634
Notes: From FY2016, the Company adopts “Accounting Standard for Business Combinations” (September 13, 2013), “Accounting Standard for Consolidated Financial Statements” (September 13, 2013), and “Accounting Standard for Business Divestitures” (September 13, 2013).
Price / earnings ratio = Common stock price / Net income per share 株価収益率 = 株価 ÷ 1 株当たり当期純利益Price / book value ratio = Common stock price / Net assets per share 株価純資産倍率 = 株価 ÷ 1 株当たり純資産Price / cash flow ratio = Common stock price / Cash flow per share 株価キャッシュ・フロー倍率 = 株価 ÷ 1 株当たりキャッシュ・フロー
Notes: 1. Number of shares issued as of March 31, 2016 decreased 15,400 thousand shares (8.53% of issued shares before the cancellation) from March 31, 2015 due to cancellation of treasury stock.
2. From FY2016, the number of shares issued of less than one thousand has been rounded down in the “Number of shares issued.” 3. The number of shares outstanding excluding the treasury stock is used for calculation of per share data.
2012I II III IV I II III IV I II III IV I II III IV I II III IV I
2009 2010 2011II III IV I IV
2013I II III
2014 2015 2016I IV III III
2017I IV I
2019II III
2018
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21
■ Major Shareholders (Top 10) 大株主一覧(上位10位)As of March 31, 2019 2019年3月31日現在
Name of shareholders株主名
Number of shares held (Thousands)持株数(千株)
Voting share ratio (%)持株比率(%)
The Master Trust Bank of Japan Limited (trust account) 日本マスタートラスト信託銀行株式会社(信託口)
30,791 18.75
Japan Trustee Services Bank Limited (trust account) 日本トラスティ・サービス信託銀行株式会社(信託口)
17,573 10.70
JP Morgan Chase Bank 380055 ジェーピー モルガン チェース バンク 380055
9,627 5.86
Tokyo Broadcasting System Holdings, Inc. 株式会社東京放送ホールディングス 7,077 4.31Trust & Custody Services Bank, Limited (securities investment trust account) 資産管理サービス信託銀行株式会社(証券投資信託口)
3,672 2.23
Name of shareholders株主名
Number of shares held (Thousands)持株数(千株)
Voting share ratio (%)持株比率(%)
JP Morgan Chase Bank 385151 ジェーピー モルガン チェース バンク 385151 3,108 1.89Japan Trustee Services Bank Limited (trust account 4) 日本トラスティ・サービス信託銀行株式会社(信託口4)
2,801 1.70
Japan Trustee Services Bank Limited (trust account 5) 日本トラスティ・サービス信託銀行株式会社(信託口5)
2,616 1.59
State Street Bank West Client Treaty 505234 ステート ストリート バンク ウェスト クライアント トリーティー 505234
2,538 1.54
Japan Trustee Services Bank Limited (trust account 7) 日本トラスティ・サービス信託銀行株式会社(信託口7)
2,442 1.48
Notes: 1. Shares of less than one thousand have been rounded down in the “Number of shares held.” 2. Voting share ratios are calculated excluding treasury stock (1,002,816 shares). Figures are truncated after the second decimal
place. Treasury stock excludes the 249,701 Company shares owned by the executive compensation Board Incentive Plan (BIP) trust account and the share-delivering Employee Stock Ownership Plan (ESOP).
Notes: 1. Number of shareholders and shares includes number of odd lot shareholders and odd lot shares. 2. From FY2016, the number of shares of less than one thousand has been rounded down in the “Shares.” 3. Treasury stock excludes the 249,701 Company shares owned by the executive compensation Board Incentive Plan
(BIP) trust account and the share-delivering Employee Stock Ownership Plan (ESOP).
Japanese financial institutions and securities companies 金融機関・証券会社Foreign institutions and others 外国法人等Japanese individuals and others 個人その他Other Japanese corporations その他の法人Treasury stock 自己株式51.6% 9.6% 5.5%32.7% 0.6%
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