Workshop April 4th, 2007 A UC Discovery Project FLCC

04/04/2007FLCC

FLCC – Sensors & Control

Feature-level Compensation & Control

WorkshopApril 4th, 2007

Sensor and Control

A UC Discovery Project

04/04/2007

2

FLCCFLCC – Sensors & Control

Current Milestones (Year III, 1/27/06 to 1/26/07)

• Complete experimental study for CD non-uniformity reducing across the litho-etch sequence (SENS Y3.2)

– Experimentally verify DI & FI CDU improvement using model based optimal control of PEB with various CD objective functions. DONE

• Using Spatial CD Correlation in IC Design (SENS Y3.3) – Develop test structures and measurement plans for extracting spatial correlation

characteristics. DONE• Aerial Image Metrology (SENS Y3.4)

– Complete the micro-assembly of the commercial CCD with the Si carrier wafer. Integrate the aperture mask and the CCD arrays. IN POGRESS / EMPHASIS SHIFTED TO APPLICATIONS

• Modeling and demonstration of metrology wafer for detection and thin-film roughness monitoring.

– Initiate prototyping of wireless data acquisition/transmission and evaluate performance with measurements made in experimental systems. DONE

04/04/2007

3


CD Uniformity ControlCharlie Zhang

• Making each process step spatial uniform is prohibitively expensive

• Our approach: manipulate PEB temperature spatial distribution of multi-zone bake plate (and die-to-die dose) to compensate for other systematic across-wafer CD variation sources

CDU Control Framework

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4


Long Term Overall FI CD Improvement ~35%in recently completed experiment at AMD/SDC

across-wafer sigma of 250 1:1 lines, using CDSEM

FI CDV before and after control

0

0.5

1

1.5

2

2.5

Before After

FI C

DV

1 si

gma(

nm) Wfr1

Wfr2

Wfr3

Wfr4

Wfr5

Wfr6

DI CDV before and after control

00.5

11.5

22.5

33.5

44.5

Before After

DI C

DV

1 si

gma

(nm

) Wfr1

Wfr2

Wfr3

Wfr4

Wfr5

Wfr6

DI CD uniformity is sacrificed in order to optimize FI CD uniformity

σ=1.36nm

m=141.9nm

σ=1.21nm

m=142.1nm

σ=1.26nm

m=141.7nm

σ=1.14nm

m=141.5nm

σ=1.41nm

m=141.4nm

σ=1.39nm

m=142.4nm

Qiaolin (Charlie) Zhang, on internship at AMD/ Spansion 2005-06

04/04/2007

5


Zero-footprint Optical Metrology Wafer – Prototyping and ModelingData Transmission

Photo/RF Transmitter

Dielectric Layer as Optical Window

Si

Battery Data Acquisition Unit

500µm

Data Transmission

Photo/RF Transmitter

Dielectric Layer as Optical Window

Si

Battery Data Acquisition Unit

500µm

GSR: John Gerling

Faculty: Professor Nathan Cheung

04/04/2007

6


Current Milestones (MMC Y4.1)• Simulate and experimentally verify the monitoring of

lateral patterns development (e.g. wet etching high aspect-ratio contact holes in dielectrics).

• Enhance signal-to-noise ratio for better sensitivity with high-brightness LEDs.

• Investigate multi-stage mechanisms of Cu etching near end point.

04/04/2007

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Current Achievements• Simulated monitoring of high aspect-ratio contact holes

in dielectrics.• Enhanced signal-to-noise ratio for better sensitivity with

high brightness LEDs and investigated effects of manufacturing noise on metrology system.

Work In Progress• Investigate Cu etching mechanism.• Experimental verification of lateral pattern etch

monitoring (e.g. wet etching of high aspect-ratio contact holes and trenches in dielectrics).

04/04/2007

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Simulation of Contact Hole Wetting• Goal: Simulate monitoring of wetting in high aspect-ratio contact holes in dielectrics.• Simulation Setup: Thin film stack, simulated wavelengths of 463, 525 and 632 nm.

Ambient layer [Vacuum], z=semi-infiniteSi3N4 layer (1), z=650.00 nm

4X [SiO2/Vacuum] multilayer, N=20, d=6.25 nm, Gamma=0.700SiO2 layer (2), z=4.37 nmH2O or Vacuum layer (3), z=1.88 nm

Substrate layer [H2O], z=semi-infinite

Effective Medium Theory: Effective refractive index of layer used in simulation is equal to volume fraction of A*(na+ika) + volume fraction of B*(nb+ikb)

Justification: Thickness of layer and lateral dimensions of features < wavelength of photon

0% 25% 50% 75% 100%

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nm525=λ

nm463=λ

Simulation of Contact Hole Wetting Cont.

Reflectance as a function of angle for 463 nm and 525 nm incident light for 0%, 25%, 50% , 75%, and 100% wetting conditions.

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• Sweet spots for the angular reflection between 40-60 degrees for substrate thicknesses varying from 500 nm to 2000 nm.

nm632=λ

Simulation of Contact Hole Wetting Cont.

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HB LED Apparatus

• SemiLEDs Peak Wavelength: 463±15 nm• Advanced Photonix Inc. Photodiode: PDB-V106 • Sample: Spin-coated Shipley S1818 photo resist • on Pyrex/Glass 520-540 µm substrate• Etchant: Photoresist Stripper PRS3000• Data Collection: HP4145

04/04/2007

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Signal-to-noise ratio enhancement with HB LED• PR etch monitoring with room light only, then room light plus LED.

• Significantly less dependence on ambient light levels than with the low power LED used in previosu prototypes

0 10 20 306.875

7.000

7.125

7.250

7.375

7.500

Room light ON Room light OFF

Sign

al (V

)

Etching time (s)

Experimental Condition: Sputtering deposition, etching solution: Cyantek CR-7 (Perchoric based), Glass window thickness 500µm, LED peak wavelength 463±15nm, Cu thickness 60-70nm. I = LED current. Light on/off indicates the external room light.

HB LED 2.7 um PR Etch with 0.1 s resolution

6.50E-05

7.00E-05

7.50E-05

8.00E-05

8.50E-05

9.00E-05

0 10 20 30 40 50

Time [s]

Cur

rent

[A]

HB LED + Room Lights

Low Brightness LED

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Effect of Specular Reflections• Silicon wafer mirror to reflect ambient and LED light back to photodiode.

Conducted under various lighting conditions.

• Specular reflection from strong point sources can add significant noise to system. Specular reflection from room lights is almost negligible. This is a benefit of the HB LED.

Specular Reflection

0.0E+00

2.0E-05

4.0E-05

6.0E-05

8.0E-05

1.0E-04

1.2E-04

0 5 10 15 20 25 30

Time [s]

Cur

rent

[A] Room Light

room Light + LED

Room Light + LED +Flashlight

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• Conducted with room light and LED on for sample thickness ranging from 1.5 um to 2.7 um. Drop of PRS3000, monitoring done with HP4145B at 0.05 second resolution.

• 1) transient effect from PRS3000 drop, • 2) linear or slight parabolic decrease in signal as etch proceeds • 3) flat response when etch is complete.

Photoresist Wet Etch Monitoring

PR Etch 50 sec with 0.05 sec resolution

6.0E-05

6.5E-05

7.0E-05

7.5E-05

8.0E-05

8.5E-05

9.0E-05

9.5E-05

0 10 20 30 40 50

Time [s]

Cur

rent

[A] 1.5 um

1.8 um2.1 um2.7 um

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Future Milestones

• Experimental verification of lateral pattern etch monitoring (e.g. wet etching of high aspect-ratio contact holes and trenches in dielectrics).

• Investigate Cu/PR etching mechanism.• Prototyping the self-contained metrology unit

with wireless I/O.

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Integrated Aerial Image Sensor

Mask Pattern

Black: ideal, diffraction limited opticsRed: optics with typical aberrations

Students: Jing Xue, Chaohao Wang, Yu Ben

Faculty: Prof. Costas J. Spanos• Students: Jing Xue, Chaohao Wang, Yu Ben

• Faculty: Prof. Costas J. Spanos• Title: Integrated Aerial Image Sensor (IAIS)

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2007 Main Objective• Complete IAIS prototype and test within the UC Berkeley Microlab• Interact with key company collaborators for testing beyond the UC

Berkeley Microlab.• Explore fully integrated design with special purpose UV detectors

• Complete the Aberration Monitor, specified on the defocus and coma target

• Complete the Process Window Monitor (combine with ODP test pattern)

• Explore the Aerial Image Distortion & Variation, OPC and Post-OPC properties, combining with DFM work

• Investigate the Polarization Monitor properties

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IAIS System Description

Litho.

λ, ΝΑ, σ, mask, ab., …

Aerial Image(AI)

IAISAperture Mask

IAISPhoto-detector

Detector Image(DI)

Photo-current(PC)

Φ1 Φ2 Φ3 Φ1 Φ2 Φ3

Substrate

Photo- detectorAperture mask

Mask aperture

IAIS AMF: x -> ξAI DI

x ξ Noise thresholder PC

yOutputInput

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IAIS Metrology Capabilities

*292nm 1:1 line/space pattern, 193nm, 0.75NA

Nonab: slope= 2.65 /(λ/NA); CD = 145 (nm)Df .06: slope= 2.29 /(λ/NA); CD = 145 (nm)Df .08: slope= 1.81 /(λ/NA); CD = 143 (nm)

a. Image intensity &intensity variation

b. Image contrast & contrast variation

Nonab: slope= 12.13/(λ/NA); CD = 145 (nm)Df .06: slope= 11.89 /(λ/NA); CD = 145 (nm)Df .08: slope= 8.28 /(λ/NA); CD = 143 (nm)

d. Image slope & slope variation

c. CD & CD variation e. Image shift & its variation

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IAIS Aperture Mask PatterningFolded Spatial shift Matrix Measurement Results:

Shift 300.6nm

Shift 299.4nm

Shift 303.8nm

Distance 7.249 µm

Distance 7.249 µm

Distance 7.252 µm

)(550 nm±Aperture Groups spatial shift

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IAIS Microlab Prototype (I-line)Aperture mask pattern

Circuit connection: BCAM v.2 CCD

Assembly measurement results by Profilometer:

CCD dummy chip is co-planar to the wafer carrier with maximum height difference of 1.17µm, and tilt angle 0.0014o (along x)

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IAIS Application - Aberration Monitoring

p

d

wb

wn d

90o/180o -90o/-180o0o 0o

wb

0o

Top

mas

k de

sign

0.49 0.72Distance between 0o and the phase shift grating determines the sensitivity of this aberration and the orthogonality to the other aberrations

Defocus highest sensitivity occurs at 0.556 (λ/NA); highest orthogonality to spherical occurs at 0.53 (λ/NA)

* A. R. Neureuther, etal., Proc. SPIE, 2001; G. Robins, PhD 2005

Def

ocus

Tar

get

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IAIS Application – Aberration Monitoring

%5.82=∆I %5.82=∆I

Spherical TargetDefocus Target

%2.18/;%3.48/ 21 =∆=∆ nonnon IIII

Defocus:

Spherical:

%8.165/;%5.82/ 21 =∆=∆ nonnon IIII Defocus: %63/;%5.59/ 21 =∆=∆ nonnon IIII

Spherical: %95/;%9.216/ 21 =∆=∆ nonnon IIII

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Aberration Analysis System• Characterizing the aberrations of an

exposure system is crucial for design verification as design rules shrink– Valuable information for performing mask

correction– Needed for OPC generation and OPC

verification

• Conventional methods– Time consuming– Indirectly done through OPC calibration

patterns– Cannot obtain a complete aberration map– Cannot be used to compare individual optical

columns

• A fast, in-situ aberration measurement is desired

Students: Yu Ben, Jing Xue, Chaohao Wang

Faculty: Costas J. Spanos

04/04/2007

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2007 Main Objective• Refine the Zernike coefficients extraction scheme to

achieve better robustness

• Adjust the grating and pellicle design with partial coherence taken into account

• Design new feature adaptable to Optical Digital Profiling (ODP) analysis

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The Problem – Partial Coherence “blurs” Aberrations

Mask Substrate

Mask Pattern

Diffraction Pattern

Mask Substrate

Mask Pattern

Diffraction Pattern

Partial coherence prevents the probing ray from sampling a well-defined point on the pupil plane, yielding an averaged value of phase distortion.

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Pupil Plane Sampling• Assuming a perfectly coherent,

point light source, pupil plane sees the Fourier Transform of the reticle.

• Points at pupil plane correspond to features with different spatial frequencies

• Gratings with different periods can diffract light onto different points on the pupil plane

• An opaque pattern on pellicle can be used to select the desired probing rays1

mask

pellicle

1Nigel R. Farrar”, Adlai L. Smithb et al, Proc. SPIE, Vol 4000 (2000)

04/04/2007

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Pupil Sampling With Pellicle Obscuration

•Radius ~ 844.6 µm on mask, 168.9 µm on wafer

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Aberration Measurement via Image Shift Detection• Wave aberration is equivalent to image shift

– Lateral shift amount = – For a system with Strehl ratio larger than 97%, total variance can be

estimated to be less than 0.03 following Maréchal formula

• The corresponding aberration is in the order of a few hundredths of a wavelength

• The lateral shift is in the order of a few nanometers• Two approaches

– Integrated Arial Image Sensor

– Optical Digital Profilometry (ODP)

( )22 21 φσ−≈S

0 5 10 15 20 25 30 35 40 45 500.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Displacement (nm)

Nor

mal

ized

Inte

nsity

TETM

TEMPEST simulation result

( ) ( )fwfw ⋅− λ/)0()(

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Effect of Partial Coherence• Partial coherence causes the probing ray to sample a widened area

• The measurements reflect an averaged pupil map corresponding to various illumination schemes

Averaged pupil map with incoherent (σ=0.3) illumination

Averaged pupil map with quadrupole illumination

Original Pupil Map

Zernike coefficients can be extracted by least mean square fitting

Pupil map can be reconstructed

Reconstructed pupil map at the presence of quadrupole illumination

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Zernike Coefficient Extraction with Partial Coherence

∑=j

jjZaw ),(),( θρθρ

∑ ⋅=j

nmjjnm Zaw )},({)},({ θρθρ OO

An over-determined linear system which can be solved by least mean square fitting

O{ ⋅ } represents the averaging operation

Extraction method:

In this simulation:72 sampling points (8 in radial direction, 9 in angular direction, evenly distributed in both directions)Coefficients are randomly chosen to generate the original aberration function, which corresponds to Strehl ratio of 97%A constant background ( ~ 1% of total variation) is introduced as noise

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Coherence Enhancement• Substrate back surface can be patterned1 to enhance

the coherence• Partial coherence factor can be reduced to ~ 0.1 with

T = 6 mm, and Lx = 100 µm

Mask Substrate

Pattern

Substrate Back surface

1Shinroku Maejima et al, Proc. SPIE, Vol 6283, 62833A-1 (2006)

mm)(6=T

167.0mm6

µm100==≈

TLxα

16.058.0NAsin max ===

Mθ

10.0max

≈=θασ

04/04/2007

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Future Goals• Complete system simulation confirming the

pellicle pattern functionality • Design patterns compatible with ODP

measurements• Build system prototype and perform ODP

analysis to extract aberration information

04/04/2007

35


Modeling Spatial Gate Length Variation in the 0.2µm to 1.15mm Separation Range

• Manufacturing-induced variation in device parameters leads to variability in circuit performance

• Two approaches to address this concern:– Tailor IC design to minimize

sensitivity to parameter variation– Use process control to reduce

manufacturing variation• Investigate these approaches

through Monte Carlo analysis of canonical circuits

• For accurate, useful predictions, Monte Carlo framework must model reality very well

Specific focus of this work: detailed spatial variation of gate length

Student(s): Paul Friedberg, Qian Ying Tang, George Cheng, Willy Cheung, Kun QianFaculty: Costas J. Spanos

04/04/2007

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Short(µm)-Range CD Test Structures• Dense ELM base case test structure (90nm tech.):

• To increase measurable range, insert dummy lines:

• Maximum 255 dummy lines: 1.15mm range, 71µm pitch

Base test structure: Range = 4.76µmPitch = 280nm

Range

Range = 9.52µm Pitch = 560nm

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Full Chip View2.

35m

m

1.8mm

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Raw Data (Averaged Across Chips)• 25 total pre-diced chips (wafer location unknown)

• Two instances per chip (horiz, vert), 9 DUT’s per chip, 17 measurement positions within each DUT

3825 total measurements for each orientation

1

4

7

10

1316

123456789

(bla

nk)

130.5

131.5

132.5

133.5

134.5

135.5

136.5

Avg

. CD

(nm

)

DUT

position

• Vertical orientation:• Horizontal orientation:

Avg

. CD

(nm

)

DUT

position1

4

7

10

1316

123456789

(bla

nk)

129

130

131

132

133

134

135

04/04/2007

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Pattern Density-Dependent Etch Model• Etch microloading can explain the deterministic pattern

observable in measurements from DUT’s 1-4

• Model contains two density metrics1) “Local” density: intended to capture shorter-range etch effects, we count

the total polysilicon area within a moving window that is centered on the line in question:

2) “Global” density: intended to capture longer-range etch effects, we calculate the total area of polysilicon within a given DUT

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0

0.2

0.4

0.6

horiz vert

Varia

nce

(nm

^2)

pattern dependentrandom

Breakdown of µm-Scale Variance

• Etch micro-loading model accounts for roughly 1/3rd of the µm-range spatial variation

• Does autocorrelation exist in the remaining residuals?

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Autocorrelation in Residual Component• Autocorrelation analysis for model residuals:

• Very little correlation (for the most part, not different from zero correlation within statistical significance)• Consistent positive correlation due to slight incompleteness in modeling of deterministic variation.

Horizontal Orientation Vertical Orientation

95% confidence interval around zero correlation

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M1,n-1M1,n-2 M1,n

Gate

Pulse

Clk1

Clk2Pulse

Source force

Source sense

Drain force

Drain sense

MOS Test Structures• NMOS array equipped to allow full 4-pt probing:

M1,nM1,n-1M1,n-2

1

0 01000…

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Future Goals• Milestone M45: Spat. CD Correlation in IC

Design• May 1, 2007: Submit novel ELM and MOS test

structures to foundry.• Spring, 2007: Incorporate CD measurements

into Monte Carlo framework.

• This work is also funded by SRC grant 1324.001.

04/04/2007

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Impact of Line Edge Roughness on sub-42nm Device Variability

• Intrinsic parameter fluctuations greatly impact circuit performance and yield. The three primary sources of variability that have peaked interest in the scientific community are:– Line edge roughness (LER)– Gate oxide thickness variability (GOV), and– Random dopant fluctuations (RDF)

• The formation of LER is stochastic event and its origins lie in the resist patterning process. Polymer aggregates contained in resist films have been identified as the primary cause of LER.

• Novel double-gate and triple-gate device (FinFET like) structure have been suggested as replacements for traditional CMOS.

• We are interested in understanding the impact of LER on the device performance of such structures.– In particular, we would like to model device

parameters such as Vt, Ioff, and Idsat using LER descriptors (α, ξ, and σ )

Student: Kedar Patel

Faculty: Costas Spanos

04/04/2007

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Objectives• Gate LER Investigation

– Generate a model to produce LER with α, ξ, and σ as parameters

• Done. Used MATLAB.

– Generate a basic structure in Sentaurus for the device

• Done.

– Introduce LER in the Sentaurus structure– Propose a model for device behavior using LER

descriptors (α, ξ, and σ )

04/04/2007

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What is Line Edge Roughness (LER)?1

2

1

1

N

ii

LWR

L L

Nσ =

⎡ ⎤−⎢ ⎥

⎢ ⎥=−⎢ ⎥

⎢ ⎥⎣ ⎦

∑

( )

2 2 2

2 2

2

2 1

LWR L R L R

L R LER

LWR LER

σ σ σ ρσ σσ σ σ

σ ρ σ

= + += ≡

= +

LWR

LER

W

<L>

LWR

LER

W

<L>

LWR

LER

W

<L>

Line edge roughness (LER) and line width roughness (LWR) are oftenused synonymously. Mathematically, they are related but different…

04/04/2007

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Transfer of LER

Schematic of a typical gate stack

Resist

Poly-SiGate Dielectric

Substrate

Hard MaskBARC

Pawloski (SPIE 2006)

04/04/2007

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Illustration of LER in FinFET

+ =Fin

Gate

FT

B

h

t

L

+ =Fin

Gate

FT

B

FT

B

h

t

h

t

LLT

Gate LER

t

F and B

Fin LER

h

04/04/2007

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Unfolded FinFET

FG

Body

BG

S D

h

h

T

B

F

t

<L>

Etch Progression

Average Gate Length

Tapered Etch Profile(Curtain Effect)

Li

X X’

Y Y’

Gate

Fin DS

Top View

Distribution of determines the FG andBG placement and CD

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LER Descriptors• 3σ variation is not a sufficient

descriptor of LER

• Complete description of LER is achieved by a power spectral density function, a first-order autoregressive process or height-height correlationfunction and σ

• Extraction of these descriptors starts with DSP of the SEM image

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Future Goals• Near Term

– Create statistical variability model with LER and long distance large scale variability of CDs.

– Assess the impact of Ioff and Ion for sub-42nm nodes• Long Term

– Fin LER Investigation• Study mobility degradation

– LER in contact/via structures• Contact edge roughness can greatly change the resistance

04/04/2007

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Circuit Size Optimization with Multiple Sources of Variation and Position Dependant Correlation

• Digital Circuit Sizing Optimization Problem– Goal: size the gates in a combinational logic circuit– Minimize the effects of individual gate delay variations and

spatial correlations on the overall circuit delay• Previous Work: Geometric Programming approach

– Objective:– where: Di = nominal delay for gate I

k = a constant ~ 2derived from Pelgrom’s

Modelwith model parameter γ– Constraints: Fixed maximum total circuit area

)]}([min{max }{ DkD ipi

ipathsallcircuitp σ+∑∈

∈

iii DxD )()( 2/1−= γσ

† S. Boyd, S.-J. Kim, D. Patil, and M. Horowitz , “A Heuristic Method for Statistical Digital Circuit Sizing ,” 31st SPIE International Symposium on Microlithography, February 2006.†† M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching Properties of MOS Transistors,”, IEEE J. Solid-state Circuits, Vol.24, No. 5, pp.1433-1439, Oct. 1989.

†

††

Students: Qian Ying Tang and Paul Friedberg Faculty: Costas Spanos

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Spatial Correlation based Modeling

)]}([min{max }{ DkD ipi

ipathsallcircuitp σ+∑∈

∈

• Adding delay variation dependence on Leff in the objective function:

iiLeffiithi DxDxD )()()( 2/12/1 −− += γγσ

]}[)]([min{max,,

22}{ ∑∑

≠∈∈∈ ++

jipjijiiji

piipathsallcircuitp kDkD σσρσ

iiLeffiithi DxDxD )()()( 2/12/1 −− += γγσρij ≡ spatial correlation between gate i and j with separation dij

where:

• Adding variation dependence on Leff and Spatial Correlation

where:

XL characteristic correlation lengthρB characteristic correlation baseline

Large scale model ⎩

⎨⎧

≥≤−−

=LijB

LijBLij

XdXdXd

ρρ )1(/1

04/04/2007

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• A model for calculating the parameter mismatch ∆P between two rectangular devices (WxL) separated by a distance Dx.

• Pelgrom’s Model suggests a spatial correlation structure implicitly– devices situate close together have higher degree of correlation/similarity than

devices separated by further apart

• Pelgrom’s model can be used to model the variance of the gate delay. • The major difference between this approach and the spatial correlation based

model: – Both terms are used vs. only the first term is used for deriving the variance of the

gate delay.

)],(),,([2)],([)],([

)],(),([)(

2211222

112

221122

yxPyxPCorryxPyxP

yxPyxPP

−+=

−=∆

σσ

σσ

WLAp

2 22xp DS+

variance of the parameter “spatial correlation”

Pelgrom’s Model and Implications

222

2 )( xpp DS

WLA

P +=∆σ

04/04/2007

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Sources of Variation• Original Pelgrom’s Model accounts for systematic across-wafer

variation only.

• A modified Model that accounts for all sources of variation is required- Wafer-level variation

• Slowly varying parabolic shaped variation across entire wafer• A consequence of loading effects in etching or deposition• Contributes a random component to the parameter value for each device in

a die.- Within-field variation

• Varies systematically and deterministically across a single die, but is identical for all dies in a wafer

• Mainly a consequence of mask errors and systematic variations in the exposure tool

• Pelgrom’s model no longer gives an accurate predication of the relationship between variance of mismatch and device separation due to this type of variation

- Layout or density dependant variation• Introduced during etching, lithography or CMP processing steps.

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Monte-Carlo Simulation ResultsHistograms of the circuit delay obtained from 5000 Monte-Carlo Samples

Design E(D) (nsec)

Std Dev (nsec)

Upper 95% quantile (nsec)

Percentage improvement in

quantile (%)Sp. Corr. 20.2 0.32 20.7

deterministic 20.6 0.52 21.64.2

Frequency

Delay(nsec)

Spatial correlation based design

Deterministic Design

(a)

Delay (nsec)

Modified Pelgrom’s Model based design

Deterministic Design

(b)

Design E(D) (nsec)

Std Dev (nsec)

Upper 95% quantile (nsec)

Percentage improvement in

quantile (%)

Modif. Pelg. 12.2 1.77 15.4

deterministic 23.0 3.48 29.247.3

(a) Comparison of the spatial correlation based design and the corresponding deterministic design; (b) Comparison of the modified Pelgrom’s model design and the corresponding deterministic design.

Frequency

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Modeling IC Robustness to Process Variability• Variability of IC performance induced by

manufacturing variations emerges as a major challenge.

• While the control of the fabrication process is improving, it is also necessary to make circuits more robust against process variations.

• The robustness of circuit components that constitute critical delay paths, in particular, must be modeled and understood.

• Basic Model of Process Variability– Systematic: Across Lot, Across Wafer,

Across Field (including field position and pattern depended effects).

– Random: Lot to Lot, Wafer to Wafer, Field to Field, Line Edge Roughness Effects, Random Dopant Fluctuation.

• The proper robustness model must comprehend both random and systematic variability.

– In this work we focus on systematic Across Filed and Across Wafer variability, and we treat random variability as uncorrelated white noise.

Student: Kun Qian

Faculty: Costas J. Spanos

04/04/2007

58


2007 Main Objective• Establish variability robustness models

– Ring oscillators– Sequences of inverter chains– 1-D and 2-D floor placement of the above

• Investigate the interaction between the process induced device parameter variations and the delay (speed) of sample circuits– Random CD variations ( White Noise )– Systematic CD variations

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Ring Oscillator Variability ModelDx Dx

• 3-stage Ring Oscillator• 1-D placement

– Field size T– stage separation DX

– Placement is randomlychosen within [-T+Dx, T-Dx]

• Uniform random CD variation

• Quadratic CD systematic variation along x- direction

L

xT

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Simplified Device ModelDelay for stage-I of ring oscillator circuit:

IDSAT ,i =W

L + δ Li

⋅ COX µ ⋅ VDD − VTh0 + VDDe− L +δ Li( )/l −VDSAT ,i

2⎛⎝⎜

⎞⎠⎟

VDSAT ,i ⋅ 1+ λVDD( )

≈W

L + δ Li

⋅COX µ ⋅ VDD − VTh0 + VDDe− L /l ⋅ 1 −δ Li

l⎛⎝⎜

⎞⎠⎟

−VDSAT ,i

2⎡

⎣⎢⎤

⎦⎥VDSAT ,i ⋅ 1 + λVDD( )

tP,i =COXVDD W L + δ Li( )⎡⎣ ⎤⎦

IDSAT ,i

⋅ 1 +L + δ Li+1

L + δ Li

⎛⎝⎜

⎞⎠⎟

=COXVDD W 2L + δ Li + δ Li+1( )⎡⎣ ⎤⎦

IDSAT ,i

Dx Dx

i-1 i i+1

• Variability can be obtained through closed form solutions.

• No need to run intensive Monte Carlo simulations.

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CD White noise Variation vs. Lgate• ∆L ~ Uniform Distribution, [-0.025um, 0.025um]• Leff=L- ∆L

0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.260

10

20

Rel

ativ

e V

aria

nce

(Per

cent

) σ( τ

)/E( τ

)

L(µm)

Whitenoise

0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.260

10

20

Mea

n de

lay

(ps)

Parameter VariableLeff RandomDX

Dx Dx

• No correlation between gate delay and gate separation• Larger gate length reduces the relative delay variance

σ/E(tP), but increases the average delay.

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Deterministic Variation vs. Dx

• Larger separation generates smaller relative delay variance, since the possible position on the die is limited by Dx.

• Dx T/2 : no variation at all.

Dx Dx

0 1000 2000 3000 4000 50000

2

4

6

Rel

ativ

e V

aria

nce

(Per

cent

)σ

( τ)/E

( τ)

Dx(µm)

Deterministic Variation

0 1000 2000 3000 4000 500016

17

18

19

Mea

n de

lay

(ps)

Parameter Variable

LGate Quadratic

DX

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Arbitrary Orientation

• 3-stage Ring Oscillator• 2-D placement• The placement of devices is not

parallel to either X or Y-axis.• Position is random within

[-T+Dx, T-Dx]*[-T+Dy, T-Dy]Dy

Dy

Dx Dx

Parameter Variable

LGate Quadratic

DX

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Relative Variance ContourVariance changes more rapidly with orientation at small separation, while tend to be insensitive when separation is comparable to field size.

0.5 1 1.5 2 2.5 3 3.5 4 4.5

x 10-3

1

2

3

4

x 10-3

0

0.01

0.02

0.03

0.04

0.05

0.06

Dx(m)

Dy(m)

Rel

ativ

e V

aria

nce(

m)

• Define the appropriate method to integrate into the design flow• Applying the same method to more complex circuit structures.

– Evaluate different units from standard cell libraries.– Investigate the impact of different circuit topologies.

Future Goals

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New Milestones (Year IV, 1/27/07 to 1/26/08)• Zero-footprint Metrology Wafer (continuing) (MMC Y4.1) Investigate multi-stage mechanisms

of Cu etching near end point. Simulate and experimentally verify the monitoring of lateral patterns development (e.g. wet etching high aspect-ratio contact holes in dielectrics). Enhance signal-to-noise ratio for better sensitivity with high brightness LEDs.

• Complete Aerial image Sensor Testing Phase. (continuing) (MMC Y4.2) Complete prototype and test within the UC Berkeley Microlab. Interact with key company collaborators for testing beyond the UC Berkeley Microlab. Explore fully integrated design with special purpose UV detectors.

• Incorporate LER into the process variability problem (new). (MMC Y4.3) Create statistical variability model with LER and long distance large scale variability of CDs. Assess impact on the saturation and off-regimes using device simulation for sub 42nm nodes.

• Develop engineering models for OPC Calibration (new). (MMC Y4.4) Use model based simulation, pattern matching, test-patterns, typical layouts and experiments to assess the completeness and stability of current approaches and to assess the potential improvements of novel representations, sampling, and systems optimization.

• Complete feasibility study of sensitivity model based edge updating for OPC (new). (MMC Y4.5) Calculate sensitivity model for test binary mask. Develop algorithm to calculating edge corrections globally using sensitivity model and distributed optimization. Assess iteration stability and compare with standard roster-based edge updating.

• Compare ODP and electrical metrology measurements of long-range correlation (new) (MMC 4.6) Layout identical Optical Profilometry 2D test patterns that have a variety of 2D patterns and compare the across chip and across wafer spatial correlations in electrical and scatterometry results.

• Develop suite of 2D ODP test patterns for monitoring manufacturing issues. (MMC 4.7 may appear in a supplemental proposal) Apply learning from initial measurements of Optical Digital Profilometry on test patterns with simulation of process non-idealities to design, layout, and measure a second generation of parameter sensitive and parameter specific manufacturing monitors.

Workshop April 4th, 2007 A UC Discovery Project FLCC

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