Work in Progress --- Not for Publication 1 PIDS 7/11/00 PIDS ITWG Meeting PIDS ITWG Emerging Research Devices Working Group Face-to-Face Meeting Jim Hutchby - Facilitating Room: Mont Blanc 2 Atria Novotel - Grenoble, France 8:00 a.m - 4:00 p.m. April 25, 2001
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Work in Progress --- Not for Publication 1 PIDS 7/11/00 PIDS ITWG Meeting PIDS ITWG Emerging Research Devices Working Group Face-to-Face Meeting Jim Hutchby.
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Work in Progress --- Not for Publication
1 PIDS
7/11/00
PIDS ITWG Meeting
PIDS ITWG Emerging Research Devices Working Group Face-to-Face
PIDS ITWG Novel Devices Working Group Participants
George Bourinaoff Intel/SRC Joop Bruines Philips Joe Brewer U. Florida Jim Chung Compaq Peng Fang AMAT Steve Hillenius Agere Toshiro Hiramoto Tokyo U. Jim HutchbySRC Dae Gwan Kang Hyundai
Makoto Yoshimi Toshiba Kentarou Shibahara Hiroshima U. Kristin De Meyer IMEC Tak Ning IBM Byong Gook Park Seoul N. U. Luan Tran Micron Bin Zhao Conexant Victor Zhirnov SRC/NCSU Ramon Compano Europe Com
Work in Progress --- Not for Publication
3 PIDS
7/11/00
PIDS ITWG Emerging Devices Working Group Working Group Objectives
Prepare a sub-section of the 2001PIDS ITRS Assess advanced non-bulk CMOS-related
technologies Assess potential and issues related to novel
devices and technologies related to: Logic Memory Information Processing Architectures
Work in Progress --- Not for Publication
4 PIDS
7/11/00
PIDS ITWG Emerging Devices Working Group Meeting Objectives & Desired Outcomes
Complete the Emerging Research Devices Tables– Non Bulk CMOS– Research Memory Devices– Logic Devices– Technologies– Architectures
Complete design and layout of the Emerging Technology Sequence Chart
Set Working Group Agenda for completing our section– Emerging Technology Sequence Chart (July ITRS Mtg.)– Text descriptions of Table Entries (July ITRS Mtg.)– Reference text for Table Entries (July ITRS Mtg.)– Completed Emerging Research Devices Section (8/30)
Work in Progress --- Not for Publication
5 PIDS
7/11/00
PIDS ITWG Emerging Devices Working Group Agenda
8:00 Introductions 8:15 Review meeting objectives and agenda Hutchby8:30 Review status of Emerging Research Hutchby
Emerging Technology Sequence11This chart is intended to guide research. It is not intended to predict future technologies
Well doping
channelDepletion layer
isolation
halo
Bulk CMOS
PD SOI CMOS
back-gate
channel
isolation
buried oxide
channel
top-gate
Double-Gate CMOS
High mobility (strained Si / SiGe)
Hig
h k
gate
diel
ectr
ic
Molecular devices
Sel
f-as
sem
bly
Met
al g
ate
Nanotube
Waf
er b
ondi
ng &
laye
r tr
ansf
er
3D-integration
100 nm 15nm
Nan
omet
er-
scal
e C
MP
Air
bri
dge
Cu
inte
rcon
nect
Low
-k IL
D
Con
tact
s to
nano
devi
ces
Inte
rcon
nect
s
for
nano
devi
ces
2005 2020Year
2nm50nm
2010
CNN & QCA networks
Dev
ices
Arc
hit
ectu
reT
ech
no
log
y
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13 PIDS
7/11/00
NDWG IssuesNon Bulk CMOS Devices
Should we have an entry for Fully Depleted SOI or just a single entry for SOI without specifying PD or FD. We are all agreed that we should have some kind of entry for SOI. The question is whether the entry should refer to SOI or to FD-SOI?
Double gate structures. The Japan Region proposes to discuss 1) Vertical MOSFET, 2) DELTA, 3) double-gate MOSFET separately.
Work in Progress --- Not for Publication
14 PIDS
7/11/00
NDWG IssuesEmerging Logic Devices
Novel Logic Devices. Should we refer to this table as the “Emerging Logic Devices Table”? Other tables could be similarly named, e.g., “Emerging Memory Devices Table”, etc.
What position should we take regarding application of the NDWG’s judgement on the various entries? Should we leave any out if we think they are too speculative?
Added Row Metric. The US Group added a new row metric entitled “Maturity”. This metric is proposed to be added to all the tables
Work in Progress --- Not for Publication
15 PIDS
7/11/00
NDWG IssuesEmerging Logic Devices
Given our position on the RTD and its lack of potential, due to its being a 2-terminal device, what position should we take on the newer versions of 2-terminal devices, such as molecular switches, consisting of single molecules operating in a tunneling mode? We all agree that we should have an entry for single molecular devices and for Carbon Nanotubes. Also, the Far East Region view is that we should keep the sub-category for RTD 2-terminal devices. The US Region agrees that we should keep the entry for the RTD 2-terminal device in the RTD-FET section.
Work in Progress --- Not for Publication
16 PIDS
7/11/00
NDWG IssuesEmerging Memory Devices
MRAM. Should we separate the entries for GMR and Tunnel Junction Devices?
MRAM. The title “Pseudo-Spin-Valve Memory” might be substituted for “GMR Memory”.
Work in Progress --- Not for Publication
17 PIDS
7/11/00
NDWG IssuesEmerging Memory Devices
We need more discussion of how best to group these different memory types, and how best to categorize them with descriptive titles. Cell size, access time, retention time, write cycles and power.
Should the “Yano Device” be a separate entry to the Memory Table?
Crested Tunnel Barrier Memory. A concern is this title is specific to Prof. Liharev’s approach. Several other names including Nano Floating Gate have been suggested.
Coulomb Blockade Memory. Concern has been expressed that this title is not descriptive. Another title of “Single Electron Memory” has been suggested.
Work in Progress --- Not for Publication
18 PIDS
7/11/00
NDWG IssuesEmerging Architectures
We need to decide whether and where to put 3-D Heterogeneous Integration? Specifically, do we put the 3-D Heterogeneous Integration in the Emerging Architecture Table? The US Region agrees this should be in the Emerging Architectures Table.
We need to decide whether or not to keep the entries for Defect Tolerant Architecture and Molecular Computing in the Emerging Architecture Table?