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Wire Tension Task Force progress report Roxanne Guenette Diego Garcia-Gamez 1
8

Wire Tension Task Force progress report

May 22, 2022

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Page 1: Wire Tension Task Force progress report

Wire Tension Task Force progress report

Roxanne GuenetteDiego Garcia-Gamez

1

Page 2: Wire Tension Task Force progress report

Recent efforts

• Harvard: Develop electrical method for DUNE APAs (Roxanne, Sebastien Prince, Nathan Felt, John Oliver, Jackson Weaver and Shion Kubota (2new undergrads)) ✓ Replicate Manchester’s results

✓ Develop low-noise automated solution (prototype 1)

✓ Demonstrate multiwire viability (prototype 2)

• Colorado (Mike Mooney at. al.): Investigate information from cold electronics ✓ Study protoDUNE cold test results

✓ Proposed special runs for protoDUNE data taking

2

https://indico.fnal.gov/event/19889/

Page 3: Wire Tension Task Force progress report

Electrical method (test bench)

• Replicate Machester’s results ✓Homemade Testing Bench

Sebastien Prince 5

SBND boards

3 soldered wires

SHV and BNC connector panel

with CR components

Oscilloscope

AC amplifier

Multichannel HV power supply

Low-voltage DC power supply

Waveform generator

DAQ and Data Analysis

‣ Matlab-based DAQ using oscilloscope ongoing - Still more work towards automatization is needed

‣ Amplitude of fitted sinusoidal signal as function of frequency shown

- 400 V DC, 80 V AC

‣ Resonance at 44.3 Hz, giving 4.96 N (wire tension at 5 N)

‣ Built a pulley system to reduce friction

Sebastien Prince 12

36 38 40 42 44 46 48 50 52 54Hz

0.18

0.2

0.22

0.24

0.26

0.28

0.3

0.32

0.34

mV

Method replicated!

DAQ and Data Analysis

‣ Matlab-based DAQ using oscilloscope ongoing - Still more work towards automatization is needed

‣ Amplitude of fitted sinusoidal signal as function of frequency shown

- 400 V DC, 80 V AC

‣ Resonance at 44.3 Hz, giving 4.96 N (wire tension at 5 N)

‣ Built a pulley system to reduce friction

Sebastien Prince 12

36 38 40 42 44 46 48 50 52 54Hz

0.18

0.2

0.22

0.24

0.26

0.28

0.3

0.32

0.34

mV

Method replicated!

3Jackson is developing a fitting tool

Page 4: Wire Tension Task Force progress report

Electrical method (test bench)

• Replicate Machester’s results ✓

• Automatized DAQ (underway)

• Home-made wire boards ordered

• Systematics study (vs wire length, pitch, tension) of the method expected in the next month (Sebastien & Jackson)

Homemade Testing Bench

Sebastien Prince 5

SBND boards

3 soldered wires

SHV and BNC connector panel

with CR components

Oscilloscope

AC amplifier

Multichannel HV power supply

Low-voltage DC power supply

Waveform generator

4

Same manufacturer than for the board (see next slide) This will allow us to assess the company

Page 5: Wire Tension Task Force progress report

Study of the wire linear density

• Verify impact of wire linear density (T=4*μ*L2*f02 )

• We want to understand the precision needed on the linear density and how it can impact the error on the measurements

• Jackson has been gathering the data to extract μ and testing the impact

5

Final results underway

Page 6: Wire Tension Task Force progress report

Electrical method

• Our engineer has completed the design of the board

• This should reduce the noise significantly (hence allow for lower voltages)

• Board will be assembled and tested in the new few weeks

• We will use the board on both the local test bench and the 35t APA

• Automatisation usine FPGA

6

A A

B B

C C

D D

1

1

2

2

3

3

4

4

5

5

TITLE:Wire Tension Monitor REV: 0.9

Date: 28-Feb-'19

Sheet: 1/5

Drawn By: jnoliver

Company: Harvard University - LPPC

VC

C

Vss

INVA-1

INVB-1 INVC-1

(Wire 4 filter)(Wire 2 filter)

fclk

Wire4_bp

Wire2-bp

BPC-1

BPA

HPB-1

LPB-1

SB-1

SA-1

LPA-1

HPA-1

LPC-1

INVD-1

HPC-1

SD-1

LPD-1

BPD-1

HPD-1

SC-1

1u

C1

1u

C2

2.0k

R1

4.02k

R2

8.06k

R3

10k

R4

0 Ohm

R5

10k

R6

2kR7

4.02kR8

8.06kR9

2.0k

R11

4.02k R12

8.06k R13

0 Ohm R14

2.0kR15

4.02k R16

0

R18

10kR19

10kR20

LTC1068-200IG#PBF

U1

INV/B1HPBNB2BPB3LPB4SB5NC/26AGND7V+8NC9SA10LPA11BPA12HPANA13INV/A14 INV/D 15HPDND 16BPD 17LPD 18SD 19NC/3 20CLK 21NC/4 22V- 23SC 24LPC 25BPC 26HPCNC 27INV/C 28

8.06kR17

DRAFT

Passive LP filters @ 50kHz

10nf

C6

10nf

C7

10nf

C8

559320310

CN2

112233

49.9k

R71

49.9k

R72

1k

R73

1k

R74

1k

R75

49.9k

R76

49.9k

R77

AD8221ARMZ-R7

U5

–IN1RG2RG3+IN4 VSS 5REF 6OUT 7VCC 8

100MEG

R78

100MEG

R79

100MEG

R80

Wire4

(Ant

enna

)(W

ire2

)(W

ire4

)

SMA_Conn

U7

SMA_Conn

U15

SMA_Conn

U16

(Instrumentation amplifiers)

(Ant

enna

sel

ect

jum

per)

VC

CV

CC

Vss

Vss

4.7pf

C9

4.7pf

C10

4.7pf

C11

4.7pf

C52

0 Ohm R10

100nf

C57

100nf

C58

Wire2_out

Wire4_out

Wirex = bare signal wireWirex_out = amplified by instrumentation amplifierWirex_bp = amplified and bandpass filtered

AD8221ARMZ-R7

U6

–IN1RG2RG3+IN4 VSS 5REF 6OUT 7VCC 8

TestPin

TP3

TestPin

TP4

Wire2

Antenna

Page 7: Wire Tension Task Force progress report

News from the board design

• Andrew (PSL) has a new preliminary design of the wire carrier boards and for now, the head boards will allow for voltages up to 400V (we don’t know yet about the side boards)

• Andrew has also designed new “test boards” which can be installed on the APA (instead of the CR boards), and they stay with the APA until the CR boards are installed. These should simplify the design of the connection to the APA boards

7

Scaling : 93.36 %

Printed 2:03 PM, 2/21/2019 by awlaundrie

WIRE TENSION TESTS.

THIS SCHEME ENABLES

DIFFERENTIAL VOLTAGES

A

B

C

D

D

C

B

A

X1

X2

X3

X4

X5

X6

X7

X8

XA

XB

XD

XC

SIMPLIFIED DIAGRAM FOR APA TEST BOARDS

WIRES ARE GROUPED INTO FOUR

CONNECTORS PER LAYER WITH

EACH CONNECTOR BIASED AT A

COMMON VOLTAGE.

CONNECTORS AND CABLES

THAT DO NOT SUPPORT

REQUIRED FOR ELECTRONIC

SPRING CONTACTS TO X HEAD BOARD

CONNECTIONS TO TEST SYSTEM

TEST BOARDS REMAIN WITH APA UNTIL CR AND G-BIAS BOARDS ARE ATTACHED.

Simplified schematic from Andrew

Page 8: Wire Tension Task Force progress report

Summary

• Good progress on the electrical method, and it seems now very promising

• New board design also relieve the previous constraint on voltage (at least for head boards), but we still want to reduce the voltages used if possible

• Still few things to figure out: ✓What will be the maximum voltages allowed on the other boards? ✓ How do we measure the G-plane (can we ask for wires to not be

grouped? ✓How many wire can we do with a reasonable board and how long will it

take? ✓While the electrical method will be great for Production Site and ITF,

once the cold electronics is installed, we cannot use it as is…8