Top Banner
William Stallings Computer Organization and Architecture 8 th Edition
34

William Stallings Computer Organization and Architecture 8 th Edition

Feb 23, 2016

Download

Documents

conley

William Stallings Computer Organization and Architecture 8 th Edition. Chapter 15 – Control Unit Operations . 15.1 Micro-Operations. The operation of a computer in executing a program consists of a sequence of Instruction Cycles , with one machine instruction per cycle. - PowerPoint PPT Presentation
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript

Slide 1

William Stallings Computer Organization and Architecture8th EditionChapter 15 Control Unit Operations 15.1 Micro-OperationsThe operation of a computer in executing a program consists of a sequence of Instruction Cycles, with one machine instruction per cycle.Each instruction cycle can be subdivided into small units. One comprises fetch, indirect, execute and interrupt, with only the fetch and execute cycle always occurring.These smaller cycles involves a series of steps referred to as Micro-operations because each step is simple and does very little.

Constituent Elements of Program Execution

An instruction cycle' (also called fetch-and-execute cycle, fetch-decode-execute cycle, and FDX) is the time period during which a computer processes a machine language instruction from its memory or the sequence of actions that the central processing unit (CPU) performs to execute each machine code instruction in a program.The name fetch-and-execute cycle is commonly used. The instruction must be fetched from main memory, and then executed by the CPU. This is fundamentally how a computer operates, with its CPU reading and executing a series of instructions written in its machine language. From this arise all functions of a computer familiar from the user's end.

Fetch - 4 RegistersMemory Address Register (MAR) - Connected to address bus - Specifies address for read or write operationMemory Buffer Register (MBR) - Connected to data bus- Holds data to write or last data readProgram Counter (PC) - Holds address of next instruction to be fetchedInstruction Register (IR) - Holds last instruction fetched

Fetch SequenceAddress of next instruction is in PCAddress (MAR) is placed on address busControl unit issues READ commandResult (data from memory) appears on data busData from data bus copied into MBRPC incremented by 1 (in parallel with data fetch from memory)Data (instruction) moved from MBR to IRMBR is now free for further data fetches

Fetch Sequence (symbolic)t1:MAR