Wieman: 1 LBNL Micro-vertex STAR Collaboration Meeting Aug 2003 LBNL Howard Wieman, Fred Bieser, Robin Gareus (Heidelberg), Howard Matis, Marcus Oldenburg, Gulshan Rai, Fabrice Retiere, Kai Schweda, Hans-Georg Ritter, Eugene Yamamoto UCI Yandong Chen, Stuart Kleinfelder BNL Instrumentation Div Consulting OSU Ivan Kotov Purdue Dennis Reichhold
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Wieman: 1 LBNL Micro-vertex STAR Collaboration Meeting Aug 2003 LBNL Howard Wieman, Fred Bieser, Robin Gareus (Heidelberg), Howard Matis, Marcus Oldenburg,
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Wieman: 1LBNL
Micro-vertex
STAR Collaboration Meeting Aug 2003
LBNLHoward Wieman, Fred Bieser, Robin Gareus (Heidelberg), Howard Matis,
Marcus Oldenburg, Gulshan Rai, Fabrice Retiere, Kai Schweda, Hans-Georg Ritter, Eugene Yamamoto
UCIYandong Chen, Stuart Kleinfelder
BNL Instrumentation DivConsulting
OSUIvan Kotov
PurdueDennis Reichhold
Wieman: 2LBNL
Today's topics
• Monolithic APS CMOS, new development of photo-gate – Purpose
– Modeling
– First silicon results
• Mechanical work– Vibration measurements
– Light weight silicon support, another approach
– Thin beam pipes
Wieman: 3LBNL
• CDS removal of fixed pattern noise and KTC reset noise on the chip (standard diode requires CDS off chip)
• Increase signal by reducing signal spreading to adjacent pixels. The photo gate permits large geometry without adding capacitance to the sense node.
Photo gate purpose - addresses standard diode limitations
P-
P
P+
Standard diode geometry
Standard APS diode structure
Wieman: 4LBNL
photo gate
source follower gate
reset gate
transfer gate
row select gate
sense node drain
• Large photo-gate to collect large fraction of the charge on a single pixel, directly on the p- epi layer
• Small transfer gate also directly on p- epi layer
• Small drain (minimum capacitance) connected to source follower gate (sense node)
Photo-gate geometry
20 m
x -2 m- 1 m 1 m5 nm
8 m
0.1 m
0.4 m
P epi 1.4x1015 1/cm3
N+ 1x1020 1/cm3
photo gate transfer gate
drain
x = 0.4 and 0.8 m
(simulation quantities)
Wieman: 5LBNL
Photo-gate issues in standard CMOS
• No double poly process – possible poor transfer between gates because of low transverse field
• Floating n well between gates, a bad solution to the transfer problem with single poly
• Sub-micron process may solve problem
single poly, limitation of CMOS
double poly, standard for CCDs
photo gatetransfer gate drain
floating n well
Wieman: 6LBNL
Photo gate/transfer gate operation
photogate
transgate1.8 V V
drain2.4 V
photogate
transgate
drain
V phg = 0.8 Vtransfer mode
V phg = 2.4 Vcollection mode
Wieman: 7LBNL
Photo gate/transfer gate with 800 nm separation
photogate
transgate1.8 V V
drain2.4 V
photogate
transgate
drain
V phg = 0.8 Vtransfer mode
V phg = 2.4 Vcollection mode
Wieman: 8LBNL
Drain current after light injection
• 400 nm between photo gate and transfer gate, no floating n well
• Nano amp drain current
• Rapid electron transfer - complete in 60 ns
photo gate
transfer gate drain
Light injection
60 ns
Wieman: 9LBNL
First silicon tests, comparing photo-gate with standard diode structure
Photo-gate directly to sense node drain
DC bias:V photo-gate 0.6 VV drain 2.4 V
Output signal for Fe55 X-ray test
Issue:
ADC
Linear
ADC
Log
diode
Photo-gate 1
Photo-gate 2
diode - fullcharge collection
Why is the signal spread out – is it surface traps under the gate?
Wieman: 10LBNL
Mechanical Concept• Single end
support for rapid installation and removal
– For beampipe bake out
– Insurance for beam excursion damage
• Readout electronics in end support module
Low Mass Carbon fiber tube
Thin silicon ladders under tension
Aluminum Kapton cables under tension
Wieman: 11LBNL
Tension concept
Wieman: 12LBNL
Tension concept
Wieman: 13LBNL
50 m Silicon
9
Thinned and polished wafers, a standard industrial process
Thinned Silicon wire bonded to cable, both supported under tension
Used in wind tunnel test
Wieman: 14LBNL
Air cooling and vibration
• 1-2 m/s air cools 100 mW/cm2
• TV holography shows 2 m vibration for tensioned silicon structure
TV holography vibration map
Lucite wind tunnel Thin silicon ladder,tension support