WI-FI TECHNOLOGY CHAPTER 1 1. INTRODUCTION 1.1 Introduction to VLSI The first digital circuit was designed by using electronic components like vacuum tubes and transistors. Later Integrated Circuits (ICs) were invented, where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration). Using design at this level, one can create digital sub blocks (adders, multiplexes, counters, registers, and etc.) on an IC. This level is LSI (Large Scale Integration), using this scale of integration people succeeded to make digital subsystems (Microprocessor, I/O peripheral devices and etc.) on a chip. At this point design process started getting very complicated. i.e., manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical. This created new challenges to digital designers as well as circuit designers. Designers felt need to automate these processes. In this process, Rapid advances in Software Technology and development of new higher level Page 1
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WI-FI TECHNOLOGY
CHAPTER 1
1. INTRODUCTION
1.1 Introduction to VLSI
The first digital circuit was designed by using electronic components like vacuum tubes
and transistors. Later Integrated Circuits (ICs) were invented, where a designer can be able to
place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale
Integration) scale. With the advent of new fabrication techniques designer can place more than
100 gates on an IC called MSI (Medium Scale Integration). Using design at this level, one can
create digital sub blocks (adders, multiplexes, counters, registers, and etc.) on an IC. This level is
LSI (Large Scale Integration), using this scale of integration people succeeded to make digital
subsystems (Microprocessor, I/O peripheral devices and etc.) on a chip.
At this point design process started getting very complicated. i.e., manually conversion from
schematic level to gate level or gate level to layout level was becoming somewhat lengthy
process and verifying the functionality of digital circuits at various levels became critical. This
created new challenges to digital designers as well as circuit designers. Designers felt need to
automate these processes. In this process, Rapid advances in Software Technology and
development of new higher level programming languages taken place. People could able to
develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools, for design
electronics circuits with assistance of software programs. Functional verification and Logic
verification of design can be done using CAD simulation tools with greater efficiency. It became
very easy to a designer to verify functionality of design at various levels.
With advent of new technology, i.e., CMOS (Complementary Metal Oxide Semiconductor)
process technology. One can fabricate a chip contains more than Million of gates. At this point
design process still became critical, because of manual converting the design from one level to
other. Using latest CAD tools could solve the problem. Existence of logic synthesis tools design
engineer can easily translate to higher-level design description to lower levels. This way of
designing (using CAD tools) is certainly revolution in electronic industry. This may be leading
to development of sophisticated electronic products for both consumer as well as business
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WI-FI TECHNOLOGY 1.2 IC Design Flow
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Specifications
Behavioral Description
RTL Description
Behavioral Simulation
Functional Simulation
BehavioralSynthesis
Logic Synthesis
Gate Level Net list
Constraints
Constraints
Lib
AutomaticP&R
Layout
Logic simulation
Fabrication
Lay Out Management
SPECIFICATION
Behavioral simulation
BehavioralSimulation
RTL Description
Functional simulation
Lib
Gate level netlist
Logic simulation
Layout
Layout
WI-FI TECHNOLOGY
1.3 Introduction to VHDL
VHDL is acronym for VHSIC hardware Description language. VHSIC is acronym for very
high speed Integrated Circuits. It is a hardware description language that can be used to model a
digital system at many levels of abstraction, ranging from the algorithmic level to the gate level.
The VHDL language can be regarded as an integrated amalgamation of the following
languages:
Sequential language
Concurrent language
Net-list language
Timing specifications
Waveform generation language - VHDL
This language not only defines the syntax but also defines very clear simulation
semantics for each language construct. Therefore, models written in this language can be verified
using a VHDL simulator. This subset is usually sufficient to model most applications .The
complete language, however, has sufficient power to capture the descriptions of the most
complex chips to a complete electronic system.
1.3.1 History
The requirements for the language were first generated in 1988 under the VHSIC chips for the
department of Defense (DOD). Reprocurement and reuse was also a
big issue. Thus, a need for a standardized hardware description language for the design,
documentation, and verification of the digital systems was generated. The IEEE in the December
1987 standardized VHDL language; this version of the language is known as the IEEE STD
1076-1987. The official language description appears in the IEEE standard VHDL language
Reference manual, available from IEEE. The language has also been recognized as an American
National Standards Institute (ANSI) standard. According to IEEE rules, an IEEE standard has
to be reballoted every 5 years so that it may remain a standard so that it may remain a standard.
Consequently, the language was upgraded with new features, the syntax of many constructs was
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WI-FI TECHNOLOGYmade more uniform, and many ambiguities present in the 1987 version of the language were
resolved. This new version of the language is known as the IEEE STD 1076-1993.
1.3.2 Capabilities
The following are the major capabilities that the language provides along with the features that
the language provides along with the features that differentiate it from other hardware languages.
The language can be used as exchange medium between chip vendors and CAD tool users.
Different chip vendors can provide VHDL descriptions of their components to system designers.
The language can be used as a communication medium between different CAD and CAE tools
The language supports hierarchy; that is a digital can be modeled as asset of interconnected
components; each component, in turn, can be modeled as a set of interconnected subcomponents.
The language supports flexible design methodologies: top-down, bottom-up, or mixed. It
supports both synchronous and asynchronous timing models.
Various digital modeling techniques, such as finite –state machine descriptions, and Boolean
equations, can be modeled using the language.
The language is publicly available, human-readable, and machine-readable.
The language supports three basic different styles: Structural, Dataflow, and behavioral.
It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to
very precise gate-level descriptions.
Arbitrarily large designs can be modeled using the language, and there are no limitations
imposed by the language on the size of the design.
1.3.3 Hardware Abstraction
VHDL is used to describe a model for a digital hardware device. This model specifies the
external view of the device and one or more internal views. The internal view of the device
specifies functionality or structure, while the external view specifies the interface of the device
through which it communicates with the other modules in the environment.In VHDL each device
model is treated as a distinct representation of a unique device, called an Entity. The Entity is
thus a hardware abstraction of the actual hardware device. Each Entity is described using one
model, which contains one external view and one or more internal views.
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WI-FI TECHNOLOGYArchitecture Body
An architecture body using any of the following modeling styles specifies the internal details of
an entity.
As a set of interconnected components (to represent structure)
As a set of concurrent assignment statements (to represent data flow)
As a set of sequential assignment statements (to represent behavior)
As any combination of the above three.
Structural style of modeling
In this one an entity is described as a set of interconnected components. Such a model for the
HALF_ADDER entity, is described in a n architecture body
Architecture ha of ha is
Component Xor2 Port (X, Y in BIT; Z out BIT)
End component
Component And2
Port (L, M in BIT; N outBIT)
End component
Begin
X1 Xor2portmap (A, B, SUM)
A1 AND2portmap (A, B, CARRY)
End ha
The name of the architecture body is ha .the entity declaration for half adder specifies the
interface ports for this architecture body. The architecture body is composed of two parts the
declaration part and the statement part. Two component declarations are present in the
declarative part of the architecture body.
The declared components are instantiated in the statement part of the architecture body using
component instantiation. The signals in the port map of a component instantiation and the port
signals in the component declaration are associated by the position.
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WI-FI TECHNOLOGY1.3.4 Dataflow Style Of Modeling
In this modeling style, the flow of data through the entity is expressed primarily using concurrent
signal assignment statements. The data flow model for the half adder is described using two
concurrent signal assignment statements .In a signal assignment statement, the symbol <=implies
an assignment of a value to a signal.
1.3.5 Behavioral Style Of Modeling
The behavioral style of modeling specifies the behavior of an entity as a set of statements that are
executed sequentially in the specific order. These sets of sequential statements, which are
specified inside a process statement, do not explicitly specify the structure of the entity but
merely its functionality. A process statement is a concurrent statement that can appear with in an
architecture body.
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WI-FI TECHNOLOGY
CHAPTER 2
2. INTRODUCTION TO HDL TOOLS
2.1 Simulation Tool
2.1.1 Active HDL Overview
Active-HDL is an integrated environment designed for development of VHDL, Verilog,
and EDIF and mixed VHDL-Verilog-EDIF designs. It comprises three different design entry
tools, VHDL'93 compiler, Verilog compiler, single simulation kernel, several debugging tools,
graphical and textual simulation output viewers, and auxiliary utilities designed for easy
management of resource files, designs, and libraries.
2.1.2 Standards Supported
2.1.2.1 VHDL
The VHDL simulator implemented in Active-HDL supports the IEEE Std. 1076-1993
standard.
2.1.2.2 Verilog
The Verilog simulator implemented in Active-HDL supports the IEEE Std. 1364-1995
standard. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also
supported in Active-HDL.
2.1.2.3 EDIF
Active-HDL supports Electronic Design Interchange Format version 2 0 0.
2.1.2.4 VITAL
The simulator provides built-in acceleration for VITAL packages version 3.0. The
VITAL-compliant models can be annotated with timing data from SDF files. SDF files must
comply with OVI Standard Delay Format Specification Version 2.1.
2.1.2.5 WAVES
Active-HDL supports automatic generation of test benches compliant with the WAVES
standard. The basis for this implementation is a draft version of the standard dated to May 1997
(IEEE P1029.1/D1.0 May 1997). The WAVES standard (Waveform and Vector Exchange to
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WI-FI TECHNOLOGYSupport Design and Test Verification) defines a formal notation that supports the verification
and testing of hardware designs, the communication of hardware design and test verification
data, the maintenance, modification and procurement of hardware system.
2.1.3 ACTIVE-HDL Macro Language
All operations in Active-HDL can be performed using Active-HDL macro language. The
language has been designed to enable the user to work with Active-HDL without using the
graphical user interface (GUI).
1.HDL Editor
HDL Editor is a text editor designed for HDL source files. It displays specific syntax
categories in different colors (keyword coloring). The editor is tightly integrated with the
simulator to enable debugging source code. The keyword coloring is also available when HDL
Editor is used for editing macro files, Perl scripts, and Tcl scripts.
2.Block Diagram Editor
Block Diagram Editor is a graphical tool designed to create block diagrams. The
editor automatically translates graphically designed diagrams into VHDL or Verilog code.
3. State Diagram Editor
State Diagram Editor is a graphical tool designed to edit state machine diagrams.
The editor automatically translates graphically designed diagrams into VHDL or Verilog code.
4. Waveform Editor
Waveform Editor displays the results of a simulation run as signal waveforms. It
allows you to graphically edit waveforms so as to create desired test vectors.
5. Design Browser
The Design Browser window displays the contents of the current design, that is:
Resource files attached to the design.
The contents of the default-working library of the design.
The structure of the design unit selected for simulation
VHDL, Verilog, or EDIF objects declared within a selected region of the current
design.
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WI-FI TECHNOLOGYConsole window
The Console window is an interactive input-output text device providing entry for
Active-HDL macro language commands, macros, and scripts. All Active-HDL tools output their
messages to Console
2.1.4 Compilation
Compilation is a process of analysis of a source file. Analyzed design units contained
within the file are placed into the working library in a format understandable for the simulator. In
Active-HDL, a source file can be on of the following:
VHDL file (.vhd)
Verilog file (.v)
EDIF net list file
State diagram file (.asf)
Block diagram file (.bde)
In the case of a block or state diagram file, the compiler analyzes the intermediate
VHDL, Verilog, or EDIF file containing HDL code (or net list) generated from the diagram.A
net list is a set of statements that specifies the elements of a circuit (for example, transistors or
gates) and their interconnection.
Active-HDL provides three compilers, respectively for VHDL, Verilog, and EDIF. When
you choose a menu command or toolbar button for compilation, Active-HDL automatically
employs the compiler appropriate for the type of the source file being compiled.
2.1.5 Simulation
The purpose of simulation is to verify that the circuit works as desired.The Active-HDL
simulator provides two simulation engines.
Event-Driven Simulation
Cycle-Based Simulation
The simulator supports hybrid simulation – some portions of a design can be simulated in
the event-driven kernel while the others in the cycle-based kernel. Cycle-based simulation is
significantly faster than event-driven.
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WI-FI TECHNOLOGY
Fig2.1.5: Simulation
2.2SYNTHESISTOOL
2.2.1OVERVIEW OF XILINX ISE
Integrated Software Environment (ISE) is the Xilinx design software suite. This overview
explains the general progression of a design through ISE from start to finish. ISE enables you to
start your design with any of a number of different source types, including:
HDL (VHDL, Verilog HDL, ABEL)
Schematic design files
EDIF
NGC/NGO
State Machines
IP Cores
From your source files, ISE enables you to quickly verify the functionality of these sources using
the integrated simulation capabilities, including ModelSim Xilinx Edition and the HDL Bencher
test bench generator. HDL sources may be synthesized using the Xilinx Synthesis Technology
(XST) as well as partner synthesis engines used standalone or integrated into ISE. The Xilinx
implementation tools continue the process into a placed and routed FPGA or fitted CPLD, and
finally produce a bit stream for your device configuration.
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WI-FI TECHNOLOGY2.2.2Design Entry
ISE Text Editor - The ISE Text Editor is provided in ISE for entering design code and viewing
reports.
Schematic Editor - The Engineering Capture System (ECS) is a graphical user interface (GUI)
that allows you to create, view, and edit schematics and symbols for the Design Entry step of the
Xilinx® design flow.
CORE Generator - The CORE Generator System is a design tool that delivers parameterized
cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such
as adders, to system-level building blocks such as filters, transforms, FIFOs, and memories.
Constraints Editor - The Constraints Editor allows you to create and modify the most
commonly used timing constraints.
PACE - The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O,
Global logic, and Area Group constraints.State CAD State Machine Editor - State CAD allows
you to specify states, transitions, and actions in a graphical editor. The state machine will be
created in HDL.
2.2.3 Implementation
Translate - The Translate process runs NGD Build to merge all of the input net lists as well as
design constraint information into a Xilinx database file. Map - The Map program maps a
logical design to a Xilinx FPGA.
Place and Route (PAR) - The PAR program accepts the mapped design, places and routes the
FPGA, and produces output for the bit stream generator.
Floor planner - The Floor planner allows you to view a graphical representation of the FPGA,
and to view and modify the placed design.
FPGA Editor - The FPGA Editor allows you view and modify the physical implementation,
including routing.
Timing Analyzer - The Timing Analyzer provides a way to perform static timing analysis on
FPGA and CPLD designs. With Timing Analyzer, analysis can be performed immediately after
mapping, placing or routing an FPGA design, and after fitting and routing a CPLD design.
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WI-FI TECHNOLOGY Fit (CPLD only) - The CPLDFit process maps a net list(s) into specified devices and creates
the JEDEC programming file.Chip Viewer (CPLD only) - The Chip Viewer tool provides a
graphical view of the inputs and outputs, macro cell details, equations, and pin assignments.
2.2.4 Device Download and Program File Formatting
BitGen - The BitGen program receives the placed and routed design and produces a bit stream
for Xilinx device configuration.
IMPACT - The iMPACT tool generates various programming file formats, and subsequently
allows you to configure your device.
XPower - XPower enables you to interactively and automatically analyze power consumption
for Xilinx FPGA and CPLD devices.
Integration with ChipScope Pro.
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WI-FI TECHNOLOGY
CHAPTER 3
INTRODUCTION TO WIFI
3.1 INTRODUCTION
Wi-Fi is a popular technology that allows an electronic device to exchange
data wirelessly (using radio waves) over a computer network, including high-
speed Internet connections. The Wi-Fi Alliance defines Wi-Fi as any "wireless
local area network (WLAN) products that are based on the Institute of Electri
cal and Electronics Engineers' (IEEE) 802.11 standards". However, since most
modern WLANs are based on these standards, the term "Wi-Fi" is used in general English as a
synonym for "WLAN".
A device that can use Wi-Fi (such as a personal computer, video game
console, smartphone, tablet, or digital audio player) can connect to a network resource such as
the Internet via a wireless network access point. Such an access point (or hotspot) has a range of
about 20 meters (65 feet) indoors and a greater range outdoors. Hotspot coverage can comprise
an area as small as a single room with walls that block radio waves or as large as many square
miles this is achieved by using multiple overlapping access points.
"Wi-Fi" is a trademark of the Wi-Fi Alliance and the brand name for products using
the IEEE 802.11 family of standards. Only Wi-Fi products that complete Wi-Fi
Alliance interoperability certification testing successfully may use the "Wi-Fi CERTIFIED"
designation and trademark.
Wi-Fi has had a checkered security history. Its earliest encryption system, WEP, proved
easy to break. Much higher quality protocols, WPA and WPA2, were added later. However, an
optional feature added in 2007, called Wi-Fi Protected Setup (WPS), has a flaw that allows a
remote attacker to recover the router's WPA or WPA2 password in a few hours on most
implementations. Some manufacturers have recommended turning off the WPS feature. The Wi-
Fi Alliance has since updated its test plan and certification program to ensure all newly-certified
devices resist brute-force AP PIN attacks.
1.Internet access
A Wi-Fi-enabled device can connect to the Internet when within range of a wireless
network connected to the Internet. The coverage of one or more (interconnected) access points
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WI-FI TECHNOLOGYcalled hotspots comprises an area as small as a few rooms or as large as many square miles.
Coverage in the larger area may depend on a group of access points with overlapping coverage.
Outdoor public Wi-Fi technology has been used successfully in wireless mesh networks in
London, UK.
Wi-Fi provides service in private homes, high street chains and independent businesses,
as well as in public spaces at Wi-Fi hotspots set up either free-of-charge or commercially.
Organizations and businesses, such as airports, hotels, and restaurants, often provide free-use
hotspots to attract customers. Enthusiasts or authorities who wish to provide services or even to
promote business in selected areas sometimes provide free Wi-Fi access.
2.Advantages
Wi-Fi allows cheaper deployment of local area networks (LANs). Also spaces where
cables cannot be run, such as outdoor areas and historical buildings, can host wireless LANs.
Manufacturers are building wireless network adapters into most laptops. The price of chipsets for
Wi-Fi continues to drop, making it an economical networking option included in even more
devices
Different competitive brands of access points and client network-interfaces can inter-operate at a
basic level of service.
Limitations
Spectrum assignments and operational limitations are not consistent worldwide: most of
Europe allows for an additional two channels beyond those permitted in the US for the 2.4 GHz
band (1–13 vs. 1–11), while Japan has one more on top of that (1–14). Europe, as of 2007, was
essentially homogeneous in this respect.
A Wi-Fi signal occupies five channels in the 2.4 GHz band; any two channels whose
channel numbers differ by five or more, such as 2 and 7, do not overlap. The oft-repeated adage
that channels 1, 6, and 11 are the only non-overlapping channels is, therefore, not accurate;
channels 1, 6, and 11 are the only group of three non-overlapping channels in the U.S.
EIRP in the EU is limited to 20dbm (100 mW).
The current 'fastest' norm, 802.11n, uses double the radio spectrum compared to 802.11a
or 802.11g. This means there can only be one 802.11n network on 2.4 GHz band without
interference to other WLAN traffic.
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WI-FI TECHNOLOGY1.Range
Wi-Fi networks have limited range. A typical wireless access point using 802.11b
or 802.11g with a stock antenna might have a range of 32 m (120 ft) indoors and 95 m (300 ft)
outdoors IEEE802.11n, however, can exceed that range by more than two times. Range also
varies with frequency band. Wi-Fi in the 2.4 GHz frequency block has slightly better range than
Wi-Fi in the 5 GHz frequency block which is used by 802.11a. On wireless routers with
detachable antennas, it is possible to improve range by fitting upgraded antennas which have
higher gain in particular directions. Outdoor ranges can be improved to many kilometers through
the use of high gain directional antennas at the router and remote device(s). In general, the
maximum amount of power that a Wi-Fi device can transmit is limited by local regulations, such
as FCC part 15 in the US.
3.2 INTRODUCTION TO WIMAX
A WiMAX system consists of two parts:
A WiMAX tower, similar in concept to a cell-phone tower - A single WiMAX (~8,000
square km).
A WiMAX receiver - The receiver and antenna could be a small box or PCMCIA card, or
they could be built into a laptop the way WiFi access is today.
A WiMAX tower station can connect directly to the Internet using a high-bandwidth,
wired connection (for example, a T3 line). It can also connect to another WiMAX tower using a
line-of-sight, microwave link. This connection to a second tower (often referred to as a
backhaul), along with the ability of a single tower to cover up to 3,000 square miles, is what
allows WiMAX to provide coverage to remote rural areas.
3.2.1 Block Diagram
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WI-FI TECHNOLOGY
Fig: 3.2.1 transmission network
What this points out is that WiMAX actually can provide two forms of wireless service
There is the non-line-of-sight, WiFi sort of service, where a small antenna on your
computer connects to the tower. In this mode, WiMAX uses a lower frequency range --
2 GHz to 11 GHz (similar to WiFi). Lower-wavelength transmissions are not as easily
disrupted by physical obstructions -- they are better able to diffract, or bend, around
obstacles.
There is line-of-sight service, where a fixed dish antenna points straight at the WiMAX
tower from a rooftop or pole. The line-of-sight connection is stronger and more stable, so
it's able to send a lot of data with fewer errors. Line-of-sight transmissions use higher
frequencies, with ranges reaching a possible 66 GHz. At higher frequencies, there is less
interference and lots more bandwidth.
WiFi-style access will be limited to a 4-to-6 mile radius (perhaps 25 square miles or 65
square km of coverage, which is similar in range to a cell-phone zone). Through the
stronger line-of-sight antennas, the WiMAX transmitting station would send data to
WiMAX-enabled computers or routers set up within the transmitter's 30-mile radius
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WI-FI TECHNOLOGY(2,800 square miles or 9,300 square km of coverage). This is what allows WiMAX to
achieve its maximum range.
3.2.2 Global Area Network
The final step in the area network scale is the global area network (GAN). The proposal
for GAN is IEEE 802.20. A true GAN would work a lot like today's cell phone networks, with
users able to travel across the country and still have access to the network the whole time. This
network would have enough bandwidth to offer Internet access comparable to cable modem
service, but it would be accessible to mobile, always-connected devices like laptops or next-
generation cell phones.
Intel will start making their Centrino laptop processors WiMAX enabled in the next two
to three years. This will go a long way toward making WiMAX a success. If everyone's laptop
already has it (which is predicted by 2008), it will be much less risky for companies to set up
WiMAX base stations.
3.2.3 WHAT CAN WIMAX DO
Intel also announced that it would be partnering with a company called Clearwire to
push WiMAX even further ahead. Clearwire plans to send data from WiMAX base stations to
small wireless modems. See Intel,Clearwire to Accelerate Deployment of WiMAX Networks
Worldwide (Oct. 25, 2004).
WiMAX operates on the same general principles as WiFi -- it sends data from one
computer to another via radio signals. A computer (either a desktop or a laptop) equipped with
WiMAX would receive data from the WiMAX transmitting station, probably using encrypted
data keys to prevent unauthorized users from stealing access.
The fastest WiFi connection can transmit up to 54 megabits per second under optimal
conditions. WiMAX should be able to handle up to 70 megabits per second. Even once that 70
megabits is split up between several dozen businesses or a few hundred home users, it will
provide at least the equivalent of cable-modem transfer rates to each user.
The biggest difference isn't speed; it's distance. WiMAX outdistances WiFi by miles.
WiFi's range is about 100 feet (30 m). WiMAX will blanket a radius of 30 miles (50 km) with
wireless access. The increased range is due to the frequencies used and the power of the
transmitter. Of course, at that distance, terrain, weather and large buildings will act to reduce the