What's LGA , BGA ,PGA , DIP Chip Carrieres

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chip carrier

ContentsArticles

Land grid array 1Ball grid array 3Pin grid array 7Dual in-line package 12Chip carrier 18Socket F 21Socket C32 23Socket G34 25

ReferencesArticle Sources and Contributors 27Image Sources, Licenses and Contributors 28

Article LicensesLicense 29

Land grid array 1

Land grid array

Socket 775 on a motherboard.

The land grid array (LGA) is a type of surface-mount packaging forintegrated circuits (ICs) that is notable for having the pins on thesocket rather than the integrated circuit. An LGA can be electricallyconnected to a printed circuit board (PCB) either by the use of a socketor by soldering directly to the board.

Description

The land grid array is a packaging technology with a square grid ofcontacts on the underside of a package. The contacts are to beconnected to a grid of contacts on the PCB. Not all rows and columnsof the grid need to be used. The contacts can either be made by usingan LGA socket, or by using solder paste.

LGA packaging is related to ball grid array (BGA) and pin grid array (PGA) packaging. Unlike pin grid arrays, landgrid array packages are designed to fit both in a socket or be soldered down using surface mount technology. PGApackages cannot be soldered down using surface mount technology. In contrast with a BGA, land grid arraypackages in non socketed configurations have no balls and use a flat contact which is soldered directly to the PCBand BGA packages have balls as their contacts in between the IC and the PCBs.

Use in microprocessors

The LGA 775 package of a Pentium 4 Prescott CPU.

LGA is used as a physical interface for microprocessorsof the Intel Pentium 4 (Prescott), Intel Xeon, Intel Core2, Intel Core (Bloomfield and Lynnfield) and AMDOpteron families. Unlike the pin grid array (PGA)interface found on most AMD and older Intelprocessors, there are no pins on the chip; in place of thepins are pads of bare gold-plated copper that touchprotruding pins on the microprocessor's placeholder onthe motherboard.

While LGA sockets have been in use as early as 1996by the MIPS R10000 and HP PA-8000 processors, theinterface did not gain widespread use until Intelintroduced their LGA platform, starting with the 5x0 and 6x0 sequence Pentium 4 (Prescott) in 2004. All Pentium Dand Core 2 desktop processors currently use an LGA socket. As of Q1 2006, Intel switched the Xeon server platformto LGA, starting with the 5000-series models. AMD introduced their server LGA platform starting with the2000-series Opteron in Q2 2006. AMD offered the Athlon 64 FX series on socket 1207FX through ASUS'sL1N64-SLI WS motherboards. It was the only desktop LGA solution offered by AMD.

The most common Intel desktop LGA socket is dubbed LGA 1155 (Socket H2), which is used with Intel's SandyBridge and Ivy Bridge series Core i3, i5, and i7 families. However, the Sandy Bridge-E Core i7 family uses the LGA2011 (Socket R) socket. The LGA setup provides higher pin densities, allowing more power contacts and thus amore stable power supply to the chip. LGA packaging also has a tertiary benefit of placing pins onto themotherboard; if a pin breaks, the motherboard is often cheaper to replace than the CPU chip (as compared to a PGAchip/socket setup).

Land grid array 2

The AMD server LGA socket is designated Socket G34 (LGA 1944). Like Intel, AMD decided to use LGA socketsfor their higher pin densities, as a 1944-pin PGA would simply be too large for most motherboards.

AMD• Socket F (LGA 1207)• Socket C32 (LGA 1207) (replaces Socket F)• Socket G34 (LGA 1944)

Intel• LGA 775 (Socket T)• LGA 771 (Socket J)• LGA 1366 (Socket B)• LGA 1356 (Socket B2)• LGA 1156 (Socket H)• LGA 1155 (Socket H2)• LGA 1150 (Socket H3)• LGA 2011 (Socket R)

References

External links• theinquirer.net - Socket F to debut in July 2006 (http:/ / www. theinquirer. net/ ?article=31787)• techpowerup.com - Two more pictures of Socket F (http:/ / www. techpowerup. com/ ?12088)

Ball grid array 3

Ball grid array

Bottom view of an Intel Embedded PentiumMMX, showing the blobs of solder

A ball grid array (BGA) is a type of surface-mount packaging usedfor integrated circuits. BGA packages are used to permanently mountdevices such as microprocessors. A BGA can provide moreinterconnection pins than can be put on a dual in-line or flat package.The whole bottom surface of the device can be used, instead of just theperimeter. The leads are also on average shorter than with aperimeter-only type, leading to better performance at high speeds.

Soldering of BGA devices requires precise control and is usually doneby automated processes. A BGA device is never mounted in a socket inuse.

Description

BGA ICs assembled on a PCB

The BGA is descended from the pin grid array (PGA), which is apackage with one face covered (or partly covered) with pins in a gridpattern. These pins conduct electrical signals from the integratedcircuit to the printed circuit board (PCB) on which it is placed. In aBGA, the pins are replaced by balls of solder stuck to the bottom of thepackage. These solder spheres can be placed manually or withautomated equipment. The solder spheres are held in place with a tackyflux until soldering occurs.[1] The device is placed on a PCB withcopper pads in a pattern that matches the solder balls. The assembly isthen heated, either in a reflow oven or by an infrared heater, causingthe solder balls to melt. Surface tension causes the molten solder tohold the package in alignment with the circuit board, at the correctseparation distance, while the solder cools and solidifies.

Advantages

High densityThe BGA is a solution to the problem of producing a miniature package for an integrated circuit with many hundredsof pins. Pin grid arrays and dual-in-line surface mount (SOIC) packages were being produced with more and morepins, and with decreasing spacing between the pins, but this was causing difficulties for the soldering process. Aspackage pins got closer together, the danger of accidentally bridging adjacent pins with solder grew. BGAs do nothave this problem when the solder is factory-applied to the package.

Ball grid array 4

Heat conductionA further advantage of BGA packages over packages with discrete leads (i.e. packages with legs) is the lowerthermal resistance between the package and the PCB. This allows heat generated by the integrated circuit inside thepackage to flow more easily to the PCB, preventing the chip from overheating.

Low-inductance leadsThe shorter an electrical conductor, the lower its inductance, a property which causes unwanted distortion of signalsin high-speed electronic circuits. BGAs, with their very short distance between the package and the PCB, have lowinductances and therefore have far superior electrical performance to leaded devices.

Disadvantages

X-ray of BGA

Noncompliant leads

A disadvantage of BGAs is that the solder balls cannot flex in the way that longerleads can, so they are not mechanically compliant. As with all surface mountdevices, bending due to a difference in coefficient of thermal expansion betweenPCB substrate and BGA (thermal stress) or flexing and vibration (mechanical stress)can cause the solder joints to fracture.

Thermal expansion issues can be overcome by matching the mechanical and thermalcharacteristics of the PCB to those of the package. Typically, plastic BGA devicesmore closely match PCB thermal characteristics than ceramic devices.

The predominant use of RoHS compatible lead-free solder alloy assemblies have presented some further challengesto BGAs including "head in pillow" soldering phenomenon, "pad cratering" problems as well as their decreasedreliability versus lead-based solder BGAs in extreme operating conditions such as high temperature, high thermalshock and high gravitational force environments, in part due to lower ductility of RoHS-compliant solders.[2]

Mechanical stress issues can be overcome by bonding the devices to the board through a process called "underfilling", which injects an epoxy mixture under the device after it is soldered to the PCB, effectively gluing the BGAdevice to the PCB. There are several types of under fill materials in use with differing properties relative toworkability and thermal transfer. An additional advantage of under fill is that it limits tin whisker growth.Another solution to non-compliant leads is to put a "compliant layer" in the package that allows the balls tophysically move in relation to the package. This technique has become standard for packaging DRAMs in BGApackages.

Difficulty of inspectionOnce the package is soldered down, it may be difficult to look for soldering faults. X-ray machines, Industrial CTScanning machines,[3] special microscopes as well as endoscopes to look underneath the soldered package have beendeveloped to overcome this problem. If a BGA is found to be badly soldered, it can be removed in a rework station,which is a jig fitted with infrared lamp (or hot air), a thermocouple and a vacuum device for lifting the package. TheBGA can be replaced with a new one, or the BGA can be refurbished (or reballed) and re-installed on the circuitboard. Pre-configured solder balls matching the array pattern (preforms [4]) can be used to reballing the BGA's whenonly one or a few need to be reworked.Due to cost of X-ray BGA inspection, electrical testing is very often used. Very common is boundary scan testingusing IEEE 1149.1 JTAG port.

Ball grid array 5

Difficulties with BGAs during circuit developmentDuring development it is not practical to solder BGAs into place, and sockets are used instead, but tend to beunreliable. There are two common types of socket: the more reliable type has spring pins that push up under theballs, although it does not allow using BGAs with the balls removed as the spring pins may be too short.The less reliable type is a ZIF socket, with spring pinchers that grab the balls. This does not work well, especially ifthe balls are small.[citation needed]

Cost of equipmentExpensive equipment is required to reliably solder BGA packages; hand-soldering BGA packages is very difficultand unreliable, usable only for the smallest packages in the smallest quantities.

Variants• CABGA: Chip Array Ball Grid Array• CBGA and PBGA denote the Ceramic or Plastic substrate material to which the array is attached.• CTBGA: Thin Chip Array Ball Grid Array• CVBGA: Very Thin Chip Array Ball Grid Array• DSBGA: Die-Size Ball Grid Array• FBGA or Fine Ball Grid Array based on ball grid array technology. It has thinner contacts and is mainly used in

system-on-a-chip designs.• Known as FineLine BGA by Altera.

• FCmBGA: Flip Chip Molded Ball Grid Array• LBGA: Low-profile Ball Grid Array• LFBGA: Low-profile Fine-pitch Ball Grid Array• MBGA: Micro Ball Grid Array• MCM-PBGA: Multi-Chip Module Plastic Ball Grid Array• PBGA: Plastic Ball Grid Array• SuperBGA (SBGA): Super Ball Grid Array• TABGA: Tape Array BGA• TBGA: Thin BGA• TEPBGA: Thermally Enhanced Plastic Ball Grid Array• TFBGA or Thin and Fine Ball Grid Array• UFBGA and UBGA and Ultra Fine Ball Grid Array based on pitch ball grid array.To make it easier to use ball grid array devices, most BGA packages only have balls in the outer rings of thepackage, leaving the innermost square empty.Intel used a package designated BGA1 for their Pentium II and early Celeron mobile processors. BGA2 is Intel'spackage for their Pentium III and some later Celeron mobile processors. BGA2 is also known as FCBGA-479. Itreplaced its predecessor, BGA1.For example, The "Micro-FCBGA" (Flip Chip Ball Grid Array) is Intel's currentWikipedia:Manual of Style/Datesand numbers#Chronological items BGA mounting method for mobile processors that use a flip chip bindingtechnology. It was introduced with the Coppermine Mobile Celeron. Micro-FCBGA has 479 balls that are 0.78 mmin diameter. The processor is affixed to the motherboard by soldering the balls to the motherboard. This is thinnerthan a pin grid array socket arrangement, but is not removable.

Ball grid array 6

Intel Mobile Celeron in a BGA2 package (FCBGA-479)

The 479 balls of the Micro-FCBGA Package(a package almost identical to the 478-pinSocketable Micro-FCPGA Package) arearranged as the 6 outer rings of a 1.27 mmpitch (20 balls per inch pitch) 26x26 squaregrid, with the inner 14x14 regionempty.[5][6]

Procurement

Primary end-users of BGAs are originalequipment manufacturers (OEMs). There isalso a market among electronic hobbyists doit yourself (DIY) such as the increasinglypopular maker movement.[7] While OEMsgenerally source their components from the manufacturer, or the manufacturer's distributor, the hobbyist willtypically obtain BGAs on the aftermarket through electronic component brokers or distributors.

References• "Packaging a 40-Gbps Serial Link Using a Wire-Bonded Plastic Ball Grid Array", White Paper [8]

• "Amkor & Nokia Japan: 0.3mm Pitch CSP / BGA Development for Mobile Terminals”, White Paper [9]

[1] Soldering 101 - A Basic Overview (http:/ / www. indium. com/ _dynamo/ download. php?docid=323)[2] http:/ / teerm. nasa. gov/ NASA_DODLeadFreeElectronics_Proj2. htm[3] "CT Services - Overview." Jesse Garant & Associates. August 17, 2010. http:/ / www. jgarantmc. com/ ct-services. html[4] http:/ / www. solder. net/ products/ ezreball-reballing-performs[5] Intel. "Mobile Intel Celeron Processor (0.13 μ) in Micro-FCBGA and Micro-FCPGA Packages". Datasheet (http:/ / pdf. seekdatasheet. com/

2008715/ 200807151345533917. pdf). 2002.[6] FCBGA-479 (Micro-FCBGA) (http:/ / www. x86-guide. com/ en/ articles/ packages/ FCBGA-479 (Micro-FCBGA)-no56. html)[8] http:/ / www. amkor. com/ index. cfm?objectid=437E349D-5056-AA0A-E21B197FD97E69B4[9] http:/ / www. amkor. com/ index. cfm?objectid=43744A6D-5056-AA0A-E2A3D44CFFBA9C22

Pin grid array 7

Pin grid array

Close up to the pins of a pin grid array

The pin grid array at the bottom of a XC68020, aprototype of the Motorola 68020 microprocessor

The pin grid array on the bottom of an AMDPhenom X4 9750 processor that uses the AMD

AM2+ socket.

A pin grid array, often abbreviatedPGA, is a type of integrated circuitpackaging. In a PGA, the package issquare or roughly square, and the pinsare arranged in a regular array on theunderside of the package. The pins arecommonly spaced 2.54 mm (0.1")apart, and may or may not cover theentire underside of the package.

PGAs are often mounted on printedcircuit boards using the through holemethod or inserted into a socket. PGAsallow for more pins per integratedcircuit than older packages such asdual in-line package (DIP).

PGA variants

Plastic

The topside of a Celeron-400 in a PPGA packing

PPGA: Plastic pin grid array - used by Intel for late model Mendocinocore Celeron processors based on Socket 370. Some pre-Socket 8processors also used a similar form factor, although they were notofficially referred to as PPGA.

Pin grid array 8

Underside of a Pentium 4 in a PGA package

Flip chip

The underside of a FC-PGA package (the die ison the other side)

A flip-chip pin grid array (FC-PGA or FCPGA) is a form of pin gridarray integrated circuit packaging in which the die faces downwards onthe top of the substrate with the back of the die exposed. This allowsthe die to have a more direct contact with the heatsink or other coolingmechanism.

The FCPGA was introduced by Intel with the Coppermine corePentium III and Celeron[1] processors based on Socket 370, and waslater used for Socket 478-based Pentium 4[2] and Celeron processors.FC-PGA processors fit into zero insertion force (ZIF) Socket 370 andSocket 478-based motherboard sockets; similar packages have alsobeen used by AMD. It is still used today for mobile Intel processors.

Pin grid array 9

Staggered pinThe Staggered pin grid array (SPGA) is used by Intel processors based on Socket 5 and Socket 7. Socket 8 used apartial SPGA layout on half the processor.

An example of a socket for a staggered pin grid array package.

View of the socket 7 321-pin connectors of aCPU

It consists of two square arrays of pins,offset in both directions by half theminimum distance between pins in one ofthe arrays. Put differently: within a squareboundary the pins form a diagonal squarelattice. There is generally a section in thecenter of the package without any pins.SPGA packages are usually used by devicesthat require a higher pin density than what aPGA can provide, such as microprocessors.

Ceramic

A ceramic pin grid array (CPGA) is a typeof packaging used by integrated circuits.This type of packaging uses a ceramicsubstrate with pins arranged in a pin gridarray. Some CPUs that use CPGApackaging are the AMD Socket A Athlonsand the Duron.

A CPGA was used by AMD for Athlon andDuron processors based on Socket A, aswell as some AMD processors based onSocket AM2 and Socket AM2+. Whilesimilar form factors have been used by othermanufacturers, they are not officiallyreferred to as CPGA. This type of packaginguses a ceramic substrate with pins arrangedin an array.

Pin grid array 10

microprocessor VIA C3 1,2 GHz Nehemiah C5XL CPGAsocket-370

133 MHz Pentium chip in a ceramic package

OrganicAn organic pin grid array (OPGA) is a type of connection for integrated circuits, and especially CPUs, where thesilicon die is attached to a plate made out of an organic plastic which is pierced by an array of pins which make therequisite connections to the socket.The organic pin grid array was originally introduced for the AMD Athlon XP processors based on Socket A, alsoused for AMD processors using Socket 754, Socket 939, Socket 940, Socket AM2, and Socket AM2+.

The underside of a Celeron-400 in a PPGA An OPGA CPU. Note the brown color - many OPGA partsare colored green. The die is in the center of the device, and

the four gray circles are foam spacers to relieve pressurecaused by the heat sink from the die.

Pin grid array 11

StudA Stud Grid Array (SGA) is a short-pinned pin grid array chip scale package for use in Surface-mount technology.The Polymer Stud Grid Array or Plastic Stud Grid Array was developed jointly by the InteruniversityMicroelectronics Centre (IMEC) and Laboratory for Production Technology, Siemens AG.[3][4]

References[3] (http:/ / www. jsits. com/ bga-socket/ bga_summary. htm)[4] (http:/ / www. atplas. com/ de/ index/ mr_index/ mr_news/ mr_news_business/ mr_news_business-fullpage. htm?printout=1& id=7921)

• Thomas, Andrew (August 4, 2010). "What the Hell is… a flip-chip?" (http:/ / www. theregister. co. uk/ 2000/ 08/04/ what_the_hell/ ). The Register (http:/ / www. theregister. co. uk). Retrieved December 30, 2011.

• "XSERIES 335 XEON DP-2.4G 512MB" (http:/ / reviews. cnet. com/ soho-servers/ xseries-335-xeon-dp/1707-3125_7-20584151. html). CNET (http:/ / reviews. cnet. com). October 26, 2002. Retrieved December 30,2011.

External links• Wikihowto: Guide to IC packages (http:/ / en. howto. wikia. com/ wiki/ Guide_to_IC_packages)• Intel CPU Processor Identification (http:/ / support. intel. com/ support/ processors/ sb/ CS-009863. htm)• Ball Grid Arrays: the High-Pincount Workhorses (http:/ / www. semiconductor. net/ article/

196993-Ball_Grid_Arrays_the_High_Pincount_Workhorses. php), John Baliga, Associate Editor, SemiconductorInternational, 9/1/1999

• Spot on component packaging (http:/ / www. epp-online. de/ epp/ live/ de/ fachartikelarchiv/ ha_artikel/ detail/330473. html), 08/1998, Elektronik, Produktion & Prüftechnik

• Terminology (http:/ / sandbox. cz/ ~covex/ nse/ terminy. html)

Dual in-line package 12

Dual in-line package

Three 14-pin (DIP14) plastic dual in-linepackages containing IC chips.

Sockets for 16-, 14-, and 8-pin packages.

In microelectronics, a dual in-line package (DIP or DIL[1]) is anelectronic device package with a rectangular housing and two parallelrows of electrical connecting pins. The package may be through-holemounted to a printed circuit board or inserted in a socket. Dual-in-linepackages were developed in the 1960s when the restricted number ofleads available on transistor-style packages became a limitation in theuse of integrated circuits. [2] Increasingly complex circuits requiredmore signal and power supply leads ( as observed in Rent's rule);eventually microprocessors and similar complex devices required moreleads than could be put on a DIP package, leading to development ofhigher-density packages.

A DIP is usually referred to as a DIPn, where n is the total number ofpins. For example, a microcircuit package with two rows of sevenvertical leads would be a DIP14. The photograph at the upper rightshows three DIP14 ICs. Common packages have as few as four and asmany as 64 leads. Many analog and digital integrated circuit types areavailable in DIP packages, as are arrays of transistors, switches, lightemitting diodes, and resistors. DIP plugs for ribbon cables can be usedwith standard IC sockets.

DIP packages are usually made from an opaque molded epoxy plasticpressed around a tin-, silver-, or gold-plated lead frame that supportsthe device die and provides connection pins. Some types of IC aremade in ceramic DIP packages, where high temperature or highreliability is required, or where the device has an optical window to theinterior of the package. Most DIP packages are secured to a printedcircuit board by inserting the pins through holes in the board and soldering them in place. Where frequentreplacement of the parts is desired, such as in test fixtures or where programmable devices must be removed forchanges, a DIP socket is used. Some sockets include a zero insertion force mechanism.

Variations of the DIP package include those with only a single row of pins, possibly including a heat sink tab inplace of the second row of pins, and types with four rows of pins, two rows, staggered, on each side of the package.DIP packages have been mostly displaced by surface-mount package types, which avoid the expense of drilling holesin a printed circuit board and which allow higher density of interconnections.

Dual in-line package 13

Applications

Types of devices

An operating prototyped circuit incorporatingfour DIP ICs, a DIP LED bargraph display (upper

left), and a DIP 7-segment LED display (lowerleft).

DIPs are commonly used for integrated circuits (ICs). Other devices inDIP packages include resistor packs, DIP switches, LED segmentedand bargraph displays, and electromechanical relays.

DIP connector plugs for ribbon cables are common in computers andother electronic equipment.Dallas Semiconductor manufactured integrated DIP real-time clock(RTC) modules which contained an IC chip and a non-replaceable10-year lithium battery.DIP header blocks on to which discrete components could be solderedwere used where groups of components needed to be easily removed,for configuration changes, optional features or calibration.

UsesThe original dual-in-line package was invented by Bryant "Buck" Rogers in 1964 while working for FairchildSemiconductor. The first devices had 14 pins and looked much like they do today.[3] The rectangular shape allowedintegrated circuits to be packaged more densely than previous round packages.[4] The package was well-suited toautomated assembly equipment; a printed circuit board could be populated with scores or hundreds of ICs, then allthe components on the circuit board could be soldered at one time on a wave soldering machine and passed on toautomated testing machines, with very little human labor required. DIP packages were still large with respect to theintegrated circuits within them. By the end of the 20th century, surface-mount packages allowed further reduction inthe size and weight of systems. DIP chips are still popular for circuit prototyping on a breadboard because of howeasily they can be inserted and utilized there.DIPs were the mainstream of the microelectronics industry in the 1970s and 80s. Their use has declined in the firstdecade of the 21st century due to the emerging new surface-mount technology (SMT) packages such as plasticleaded chip carrier (PLCC) and small-outline integrated circuit (SOIC), though DIPs continued in extensive usethrough the 1990s, and still continue to be used substantially as the year 2011 passes. Because some modern chipsare available only in surface-mount package types, a number of companies sell various prototyping adapters to allowthose SMT devices to be used like DIP devices with through-hole breadboards and soldered prototyping boards(such as stripboard and perfboard). (SMT can pose quite a problem, at least an inconvenience, for prototyping ingeneral; most of the characteristics of SMT that are advantages for mass production are difficulties for prototyping.)For programmable devices like EPROMs and GALs, DIPs remained popular for many years due to their easyhandling with external programming circuitry (i.e., the DIP devices could be simply plugged into a socket on theprogramming device.) However, with In-System Programming (ISP) technology now state of the art, this advantageof DIPs is rapidly losing importance as well. Through the 1990s, devices with fewer than 20 leads weremanufactured in a DIP format in addition to the newer formats. Since about 2000, newer devices are oftenunavailable in the DIP format.

Dual in-line package 14

MountingDIPs can be mounted either by through-hole soldering or in sockets. Sockets allow easy replacement of a device andeliminates the risk of damage from overheating during soldering. Generally sockets were used for high-value or largeICs, which cost much more than the socket. Where devices would be frequently inserted and removed, such as in testequipment or EPROM programmers, a zero insertion force socket would be used.DIPs are also used with breadboards, a temporary mounting arrangement for education, design development ordevice testing. Some hobbyists, for one-off construction or permanent prototyping, use point-to-point wiring withDIPs, and their appearance when physically inverted as part of this method inspires the informal term "dead bugstyle" for the method.

Construction

Side view of a dual in-line package (DIP) IC.

The body (housing) of a DIP containing an IC chip is usually madefrom molded plastic or ceramic. The hermetic nature of a ceramichousing is preferred for extremely high reliability devices. However,the vast majority of DIPs are manufactured via a thermoset moldingprocess in which an epoxy mold compound is heated and transferredunder pressure to encapsulate the device. Typical cure cycles for theresins are less than 2 minutes and a single cycle may produce hundredsof devices.The leads emerge from the longer sides of the package along the seam,parallel to the top and bottom planes of the package, and are bentdownward approximately 90 degrees (or slightly less, leaving themangled slightly outward from the centerline of the package body.) (The SOIC, the SMT package that most resemblesa typical DIP, appears essentially the same, notwithstanding size scale, except that after being bent down the leadsare bent upward again by an equal angle to become parallel with the bottom plane of the package.) In ceramic(CERDIP) packages, an epoxy or grout is used to hermetically seal the two halves together, providing an air andmoisture tight seal to protect the IC die inside. Plastic DIP (PDIP) packages are usually sealed by fusing orcementing the plastic halves around the leads, but a high degree of hermeticity is not achieved because the plasticitself is usually somewhat porous to moisture and the process cannot ensure a good microscopic seal between theleads and the plastic at all points around the perimeter. However, contaminants are usually still kept out well enoughthat the device can operate reliably for decades with reasonable care in a controlled environment.

Inside the package, the lower half has the leads embedded, and at the center of the package is a rectangular space,chamber, or void into which the IC die is cemented. The leads of the package extend diagonally inside the packagefrom their positions of emergence along the periphery to points along a rectangular perimeter surrounding the die,tapering as they go to become fine contacts at the die. Ultra-fine bond wires (barely visible to the naked human eye)are welded between these die periphery contacts and bond pads on the die itself, connecting one lead to each bondpad, and making the final connection between the microcircuits and the external DIP leads. The bond wires are notusually taut but loop upward slightly to allow slack for thermal expansion and contraction of the materials; if a singlebond wire breaks or detaches, the entire IC may become useless. The top of the package covers all of this delicateassemblage without crushing the bond wires, protecting it from contamination by foreign materials.Usually, a company logo, alphanumeric codes and sometimes words are printed on top of the package to identify itsmanufacturer and type, when it was made (usually as a year and a week number), sometimes where it was made, andother proprietary information (perhaps revision numbers, manufacturing plant codes, or stepping ID codes.)The necessity of laying out all of the leads in a basically radial pattern in a single plane from the die perimeter to tworows on the periphery of the package is the main reason that DIP packages with higher lead counts must have wider

Dual in-line package 15

spacing between the lead rows, and it effectively limits the number of leads which a practical DIP package mayhave. Even for a very small die with many bond pads (e.g. a chip with 15 inverters, requiring 32 leads), a wider DIPwould still be required to accommodate the radiating leads internally. This is one of the reasons that four-sided andmultiple rowed packages, such as PGAs, were introduced (around the early 1980s.)A large DIP package (such as the DIP64 used for the Motorola 68000 CPU) has long leads inside the packagebetween pins and the die, making such a package unsuitable for high speed devices.Some other types of DIP devices are built very differently. Most of these have molded plastic housings and straightleads or leads that extend directly out of the bottom of the package. For some, LED displays particularly, the housingis usually a hollow plastic box with the bottom/back open, filled (around the contained electronic components) witha hard translucent epoxy material from which the leads emerge. Others, such as DIP switches, are composed of two(or more) plastic housing parts snapped, welded, or glued together around a set of contacts and tiny mechanical parts,with the leads emerging through molded-in holes or notches in the plastic.

Variants

Several PDIPs and CERDIPs. The large CERDIPin the foreground is an NEC 8080AF (Intel

8080-compatible) microprocessor.

Several DIP variants for ICs exist, mostly distinguished by packagingmaterial:•• Ceramic Dual In-line Package (CERDIP or CDIP)•• Plastic Dual In-line Package (PDIP)• Shrink Plastic Dual In-line Package (SPDIP) – A denser version

of the PDIP with a 0.07 in. (1.778 mm) lead pitch.• Skinny Dual In-line Package (SDIP or SPDIP[5]) – Sometimes

used to refer to a "narrow" 0.300 in. wide DIP, normally whenclarification is needed e.g. for DIP with 24 pins or more, whichusually come in "wide" 0.600 in. wide DIP package.

For EPROMs, which can be erased by UV light, some DIPs, generallyceramic CERDIPs, were manufactured with a circular window of clearquartz in the center of the top of the package, over the chip die. This enabled the packaged chips to be erased by UVirradiation in an EPROM eraser. Often, the same chips were also sold in less expensive windowless PDIP orCERDIP packages as one-time programmable (OTP) versions. Though these were the same erasable chips, there wasno window for UV radiation to erase them. The same windowed and windowless packages were also used formicrocontrollers, and other devices, containing EPROM memory. In this context, the OTP nature of the windowlessversions was sometimes a requirement of the customer (i.e., to prevent their end users from modifying the storedinformation, which might include access control bits to disable read-out of proprietary code or factory test modeswhich were disabled after final test qualification.) Windowed CERDIP-packaged PROMs were used for the BIOSROM of many early IBM PC clones (which were manufactured in limited enough quantities to make PROM aneconomical choice) often with a foil-backed (or regular paper) adhesive label covering the window to preventinadvertent erasure through exposure to ambient light.

Molded plastic DIPs are much lower in cost than ceramic packages; one 1979 study showed that a plastic 14 pin DIPcost around US 6. 3 cents, and a ceramic package cost 82 cents.[6]

Dual in-line package 16

Single-in-line

Package sample for single in line (SIL) devices

A single in-line package (or SIP)[7] has one row of connecting pins. Itis not as popular as the DIP, but has been used for packaging RAMchips and multiple resistors with a common pin. SIPs group RAMchips together on a small board either by the DIP process or surfacemounting SMD process. The board itself has a single row of pin-leadsthat resembles a comb extending from its bottom edge, which plug intoa special socket on a system or system-expansion board.[8] SIPs arecommonly found in memory modules. As compared to DIPs with atypical maximum I/O count of 64, SIPs have a typical maximum I/Ocount of 24 with lower package costs.[9]

One variant of the single-in-line package uses part of the lead frame fora heat sink tab. This multi-leaded power package is useful for suchapplications as audio power amplifiers, for example.

Quad in-line

A Rockwell 6502 based microcontroller in a QIPpackage

Intel and 3M developed the quadruple in-line package (QIP orQUIP), introduced in 1979, to boost microprocessor density andeconomy.[10]

The QIP, sometimes called a QIL package, has the same dimensions asa DIL package, but the leads on each side are bent into an alternatingzigzag configuration so as to fit 4 lines of solder pads (instead of 2with a DIL). The QIL design increased the spacing between solderpads without increasing package size, for two reasons:

1. First it allowed more reliable soldering. This may seem odd today,given the far closer solder pad spacing in use now, but in the 1970s, the heyday of the QIL, bridging ofneighbouring solder pads on DIL chips was an issue at times,

2. QIL also increased the possibility of running a copper track between 2 solder pads. This was very handy on thethen standard single sided single layer PCBs.

As QILs became obsolete in the 1980s, many hobbyists and small manufacturers simply rebent the pins on old stockQIL chips with pliers to make them fit the standard DIL layout.[citation needed]

Some QIL packaged ICs had added heatsinking tabs, such as the HA1306. [11]

Lead count and spacingCommonly found DIP packages that conform to JEDEC standards use an inter-lead spacing (lead pitch) of 0.1 inch(2.54 mm). Row spacing varies depending on lead counts, with 0.3 in. (7.62 mm)(JEDEC MS001) or 0.6 inch(15.24 mm)(JEDEC MS-010) the most common. Less common standardized row spacings include 0.4 inch(10.16 mm) and 0.9 inch (22.86 mm), as well as a row spacing of 0.3 inch, 0.6 inch or 0.75 inch with a 0.07 inch(1.778 mm) lead pitch.The former Soviet Union and Eastern bloc countries used similar packages, but with a metric inter-lead spacing of2.5 mm rather than 2.54 mm (0.1 inch).The number of leads is always even. For 0.3 inch spacing, typical lead counts are 8 to 24; less common are 4 or 28 lead counts. For 0.6 inch spacing, typical lead counts are 24, 28, 32 or 40; less common are 36, 48 or 52 lead counts. Some microprocessors, such as the Motorola 68000 and Zilog Z180, used lead counts as high as 64; this is typically

Dual in-line package 17

the maximum number of leads for a DIP package.[]

Orientation and lead numbering

Pin numbering is counter-clockwise.

As shown in the diagram, leads are numbered consecutively from Pin1. When the identifying notch in the package is at the top, Pin 1 is thetop left corner of the device. Sometimes Pin 1 is identified with anindent or paint dot mark.For example, for a 14-lead DIP, with the notch at the top, the left leadsare numbered from 1 to 7 (top to bottom) and the right row of leads arenumbered 8 to 14 (bottom to top).Some DIP devices, such as segmented LED displays, or those thatreplace leads with a heat sink fin, skip some leads; the remaining leadsare numbered as if all positions had leads.In addition to providing for human visual identification of theorientation of the package, the notch allows automated chip-insertion machinery to confirm correct orientation of thechip by mechanical sensing.[citation needed]

DescendantsThe SOIC (Small Outline IC), a surface-mount package which is currently very popular, particularly in consumerelectronics and personal computers, is essentially a shrunk version of the standard IC PDIP, the fundamentaldifference which makes it an SMT device being a second bend in the leads to flatten them parallel to the bottomplane of the plastic housing. The SOJ (Small Outline J-lead) and other SMT packages with "SOP" (for "SmallOutline Package") in their names can be considered further relatives of the DIP, their original ancestor. SOICpackages tend to have half the pitch of DIP, and SOP are half that, a fourth of DIP. (0.1"/2.54mm, 0.05"/1.27mm,and 0.025"/0.635mm, respectfully)Pin grid array (PGA) packages may be considered to have evolved from the DIP. PGAs with the same 0.1 inch pincenters as most DIPs were popular for microprocessors from the early-mid 1980s through the 1990s. Owners ofpersonal computers containing Intel 80286 through P5 Pentium processors may be most familiar with these PGApackages, which were often inserted into ZIF sockets on motherboards. The similarity is such that a PGA socket maybe physically compatible with some DIP devices, though the converse is rarely true.

References[1] see for instance (http:/ / www. conitec. com/ xpages/ adapter/ DS210891. pdf)[2] Jackson, Kenneth.A.; Schröter, Wolfgang Handbook of Semiconductor Technology, John Wiley & Sons, 2000 ISBN 3-527-29835-5 page 610[3] Dummer, G.W.A. Electronic Inventions and Discoveries 2nd ed. Pergamon Press ISBN 0-08-022730-9[4] http:/ / www. computerhistory. org/ semiconductor/ timeline/ 1965-Package. html Computer Museum retrieved April 16, 2008[5] For instance, Microchip: http:/ / www. microchip. com/ packaging[6] Rao R. Tummala, Eugene J. Rymaszewski, Alan G. Klopfenstein Microelectronics Packaging Handbook: Semiconductor

packaging,Springer, 1997 ISBN 0-412-08441-4 page 395[8] http:/ / www. birds-eye. net/ definition/ acronym/ ?id=1154212150[9] Pecht, M. (1994). Integrated circuit, hybrid, and multichip module package design guidelines (http:/ / books. google. com/

books?id=hDwX3slSvQ4C& pg=PA48& lpg=PA48& dq=advantages+ disadvantages+ single+ inline+ package& source=bl&ots=wQ4hmEB92V& sig=NTcn1HRGCEUs97PePEUcDnt8PBw& hl=en& ei=BtaPTcfkHeuP0QHBm4ixCw& sa=X& oi=book_result&ct=result& resnum=1& ved=0CBgQ6AEwAA#v=onepage& q=advantages disadvantages single inline package& f=false). Wiley-IEEE.

[10] Intel & 3M Develop Package to Boost Microprocessor Density & Economy (http:/ / books. google. com/ books?id=Hj4EAAAAMBAJ&pg=PA22#v=onepage& q& f=false), Intelligent Machines Journal, March 14, 1979

[11] http:/ / lamson. dnsdojo. com/ LAMSON%20ALL%20PARTS%20PICTURE/ HA%20HITACHI%20IC/ HA1306W. JPG

Dual in-line package 18

Further reading• Intel (1996). Packaging. Mcgraw-hill Inc. ISBN 1-55512-254-X.

External links• Guide to IC packages (http:/ / www. wikia. com/ wiki/ c:en. howto:Guide_to_IC_packages) on Wikihowto, an

external wiki (http:/ / www. wikia. com/ wiki/ c:en. howto)• DIP packages documentation, photos and videos (http:/ / chippackage. tecnoface. com/ ?d=DIP-Dual-in-line&

show=ct& ct=dip)  This article incorporates public domain material from the General Services Administration document "Federal

Standard 1037C" (http:/ / www. its. bldrdoc. gov/ fs-1037/ fs-1037c. htm).

Chip carrier

Micro-controller Motorola MC68HC711E9CFN3in QFJ52 / PLCC52, an example of a plastic

leaded chip carrier

In electronics, a chip carrier is one of several kinds of surface mounttechnology packages for integrated circuits. Connections are made onall four edges of a square package; the internal cavity for mounting theintegrated circuit is large, compared to the package overall size.[1] Chipcarriers may have either J-shaped metal leads for connections by solderor by a socket, or may be lead-less with metal pads for connections. Ifthe leads extend beyond the package, the preferred description is "flatpack".[1] Chip carriers are smaller than dual in-line packages and sincethey use all four edges of the package can have a larger pin count. Chipcarriers may be made of ceramic or plastic. Some forms of chip carrierpackage are standardized in dimensions and registered with tradeindustry associations such as JEDEC. Other forms are proprietary toone or two manufacturers. Sometimes the term "chip carrier" is used torefer generically to any package for an integrated circuit.

Types of chip-carrier package are usually referred to by initialisms and include:• BCC: Bump Chip Carrier []

• CLCC: Ceramic Leadless Chip Carrier []

• Leadless chip carrier (LCC): Leadless Chip Carrier, contacts are recessed vertically.[]

• LCC: Leaded Chip Carrier []

• LCCC: Leaded Ceramic Chip Carrier []

• DLCC: Dual Lead-Less Chip Carrier (Ceramic) []

• PLCC: Plastic Leaded Chip Carrier [][]

Chip carrier 19

Plastic leaded chip carrier

The Harris CS80C286-16 CPU, an application ofthe PLCC68 package, in a CPU socket.

Gigabyte DualBIOS in QFJ32 / PLCC32

A plastic leaded chip carrier (PLCC) has a rectangular plastic housing.It is a reduced cost evolution of the ceramic leadless chip carrier(CLCC).

A premolded PLCC was originally released in 1976, but did not seemuch market adoption. Texas Instruments later released a postmoldedvariant that was soon adopted by most major semiconductorcompanies. The JEDEC trade group started a task force in 1981 tocategorize PLCCs, with the MO-047 standard released in 1984 forsquare packages and the MO-052 standard released in 1985 forrectangular packages.[]

The PLCC utilizes a "J"-lead with pin spacings of 0.05" (1.27 mm).The metal strip forming the lead is wrapped around and under the edgeof the package, resembling the letter J in cross-section. Lead countsrange from 20 to 84.[] PLCC packages can be square or rectangular.Body widths range from 0.35" to 1.15". The PLCC “J” Leadconfiguration requires less board space versus equivalent gull leadedcomponents, which have flat leads that extend out perpendicularly tothe narrow edge of the package. The PLCC is preferred over DIP stylechip carriers when lead counts exceed 40 pins due to the PLCC's moreefficient use of board surface area.

The heatspreader versions are identical in form factor to the standardnon-heatspreader versions. Both versions are JEDEC compliant in all

respects. The heatspreader versions give the system designer greater latitude in thermally enhanced board level and /or system design. RoHs compliant, lead-free & green material sets are now qualified standards.

A PLCC circuit may either be installed in a PLCC socket or surface-mounted. PLCC sockets may in turn be surfacemounted, or use through-hole technology. The motivation for a surface-mount PLCC socket would be when workingwith devices that cannot withstand the heat involved during the reflow process, or to allow for componentreplacement without reworking. Using a PLCC socket may be necessary in situations where the device requiresstand-alone programming, such as some flash memory devices. Some through-hole sockets are designed forprototyping with wire wrapping.

A specialized tool called a PLCC extractor facilitates the removal of a PLCC from a socket.This package is still used for a wide variety of device types, which would include memory, processors, controllers,ASIC, DSP, etc. Applications range from consumer products through automotive and aerospace.

Chip carrier 20

Leadless

Ceramic Leadless package of Intel R80286-8(bottom)[2]

A leadless chip carrier (LCC) has no "leads", but instead has roundedpins through the edges of the ceramic or molded plastic package.

Prototypes and devices intended for extended temperatureenvironments are typically packaged in ceramic, while high-volumeproducts for consumer and commercial markets are typically packagedin plastic.

References[1] Kenneth Jackson, Wolfgang Schroter, (ed), Handbook of Semiconductor Technology

Volume 2,Wiley VCH, 2000, ISBN 3-527-29835-5,page 627[2] http:/ / www. cpu-world. com/ CPUs/ 80286/ Intel-R80286-8. html "Intel R80286-8;

Package 68-pin ceramic LCC"

Socket F 21

Socket F

Socket F

   Type LGA

Chip form factors Flip-chip land grid array

Contacts 1207

FSB frequency 200 MHz System clockup to 2.4 GHz HyperTransport

Processors Opteron 2xxx, 8xxx seriesAthlon 64 FX FX-7x series

This article is part of the CPU socket series

Socket F is a CPU socket designed by AMD for its Opteron line of CPUs released on August 15, 2006.[1] In 2010Socket F was replaced by Socket C32 for entry-level servers and Socket G34 for high-end servers.

Technical specificationsThe socket has 1207 pins on a 1.1mm pitch and employs a land grid array contact mechanism.[2]

Socket F is primarily for use in AMD's server line and is considered to be in the same socket generation as SocketAM2, which is used for the Athlon 64 and Athlon 64 X2; as well as Socket S1, which is used for Turion 64 andTurion 64 X2 microprocessors.

AMD Quad FX platformSocket F is the base for the AMD Quad FX Platform (referred to as "4x4" or "QuadFather" prior to release), unveiledby AMD on November 30, 2006. This modified version of Socket F, named Socket 1207 FX by AMD, and SocketL1 by NVIDIA, allows for dual-socket, dual-core (four effective cores and eight effective cores in the future)processors in desktop PCs for home enthusiasts.

Socket F RevisionsAll revisions except Socket Fr3 require the usage of registered DDR2 SDRAM. All revisions except Socket Fr1require a dual-plane power-supply circuit for the CPU.•• Socket Fr1

•• Three HyperTransport 2.x links with 1 GHz, single-plane power-supply circuit•• Socket Fr2

•• Three HyperTransport 2.x links with 1 GHz, dual-plane power-supply circuit•• Socket Fr3

• Three HyperTransport 2.x links with 1 GHz, unbuffered DDR2 SDRAM (special version for Quad-FX)•• Socket Fr5

Socket F 22

•• CPU: Three HyperTransport 3.x links with 2.2 GHz•• Motherboards: One HyperTransport 3.x link between CPU with 2.2 GHz, two HT 2.x links with 1 GHz for I/O

operations•• Socket Fr6

• Three Hypertransport 3.x links with 2.4 GHz, support for Snoop-Filter (HT-Assist)

References

External links• Tweakers.net: First benchmarks of Socket F Opterons in databasetest (http:/ / tweakers. net/ reviews/ 638)• Tweakers.net: Pictures of the socket (http:/ / tweakers. net/ nieuws/ 39753) (Dutch)

• Dailytech: AMD's Next-gen Socket F Revealed (http:/ / www. dailytech. com/ article. aspx?newsid=958)• PCstats: Socket F Near Term Roadmap (http:/ / www. pcstats. com/ NewsView. cfm?NewsID=46731)

Socket C32 23

Socket C32

Socket C32

Socket C32 on a Supermicro H8DCL-6Fmotherboard

Type LGA

Chip form factors Flip-chip land grid array

Contacts 1207

FSB protocol Two HyperTransport 3.1 links operating 6.40 GT/s or two HT 1.1 links operating at 800 MHz

Processors AMD Opteron 4000 series

This article is part of the CPU socket series

The AMD Socket C32 is the server processor socket for AMD's current single-CPU and dual-CPU Opteron 4000series CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for lower-enddual-CPU servers. (High-end dual-CPU servers will use Socket G34 with 8 and 12-core Magny-Cours OpteronCPUs.) Socket C32 supports two DDR3 SDRAM channels. It is based on the current Socket F and uses a similar1207-land LGA socket but is not physically or electrically compatible with Socket F due to the use of DDR3SDRAM instead of the DDR2 SDRAM that Socket F platforms use.Socket C32 was launched June 23, 2010 as part of the San Marino platform with the four and six-core Opteron 4100"Lisbon" processors. Like Socket G34, it also uses the AMD SR5690, SR5670, and SR5650 chipsets. Socket C32 isalso being used in the ultra-low-power Adelaide platform with the SR5650 chipset and HT1 interconnects instead ofHT3.1. Socket C32 also supports the Bulldozer-based six- and eight-core "Valencia" Opterons introduced inNovember of 2011.

Socket C32 24

References

External links• http:/ / phx. corporate-ir. net/ External.

File?item=UGFyZW50SUQ9MjAzMzJ8Q2hpbGRJRD0tMXxUeXBlPTM=& t=1• http:/ / www. amdzone. com/ phpbb3/ viewtopic. php?f=52& t=137051& st=0& sk=t& sd=a• http:/ / blogs. amd. com/ work/ 2009/ 07/ 29/ playing-20-questions-part-1/• http:/ / anandtech. com/ cpuchipsets/ showdoc. aspx?i=3673& p=5• http:/ / www. amd. com/ us/ Documents/ 48410B_Opteron4000_QRG_FINAL. pdf

Socket G34 25

Socket G34

Socket G34

Socket G34 on a Tyan S8812 motherboard

Type LGA

Contacts 1974 (Socket)1944 (CPU)

FSB protocol HyperTransport 3.1

FSB frequency 200 MHz System clockHyperTransport up to 3.2 GHz

Processors AMD Opteron 6000 series server CPUs

This article is part of the CPU socket series

Socket G34 is a land grid array CPU socket designed by AMD to support AMD's multi-chip module Opteron6000-series server processors. G34 was launched on March 29, 2010, alongside the initial grouping of Opteron 6100processors designed for it. Socket G34 supports four DDR3 SDRAM channels, two for each die in the 1944 pin CPUpackage. Socket G34 is available in up to four-socket arrangements, which is a change from the current Socket FCPUs supporting up to eight-socket arrangements. However, four Socket G34 CPUs have eight dies, which isidentical to what eight Socket F CPUs have. AMD declined to extend Socket G34 to eight-way operation citingshrinking demand of the >4-socket market. AMD is targeting Socket G34 at the high-end two-socket market and thefour-socket market. The lower-end two-socket market will be serviced by monolithic-die Socket C32 CPUs with halfthe core count as the equivalent Socket G34 CPUs.

DevelopmentSocket G34 originally started out as Socket G3, which used the G3MX to expand memory capacity. Socket G3 andG3MX were canceled altogether, and replaced with Socket G34.[1]

Supported CPUsSocket G34 was introduced in March of 2010 with the K10-based 8-core and 12-core "Magny-Cours" Opteron 6100series CPUs. Socket G34 also supports the current Bulldozer-based 4-core, 8-core, 12-core and 16-core Opteron6200 "Interlagos" CPUs and the recently released Piledriver-based 4-core, 8-core, 12-core and 16-core Opteron 6300"Abu Dhabi" CPUs.

Socket G34 26

External links• Daily tech: Hello AMD Socket G34 [2]

• AMD Analyst Day 2009 Slideshow [3]

• AMD outs Socket G34 [4]

• AMD Analyst Day 2010 Slideshow [5]

References[1] PC Watch report (http:/ / pc. watch. impress. co. jp/ docs/ 2008/ 0520/ kaigai440. htm), retrieved August 20, 2008[2] http:/ / www. dailytech. com/ Hello+ AMD+ Socket+ G34/ article12400. htm[3] http:/ / phx. corporate-ir. net/ External. File?item=UGFyZW50SUQ9MjAzMzJ8Q2hpbGRJRD0tMXxUeXBlPTM=& t=1[4] http:/ / www. semiaccurate. com/ 2009/ 08/ 24/ amd-outs-socket-g34/[5] http:/ / phx. corporate-ir. net/ External. File?item=UGFyZW50SUQ9Njk3NDJ8Q2hpbGRJRD0tMXxUeXBlPTM=& t=1

Article Sources and Contributors 27

Article Sources and ContributorsLand grid array  Source: http://en.wikipedia.org/w/index.php?oldid=540527975  Contributors: AdamWeeden, Andros 1337, Andy.gock, Arminius, Berat556, Blitterbug, Bobo192, CesarB,Chris S, ChrisGualtieri, Ciphergoth, CryptWizard, Cybercobra, DavidGrayson, Diberri, Dstary, Electron9, Hadal, Hellbus, Henk.muller, Heron, Iridescent, Jch dtu, Jesse Viviano, Jgp, Jncraton,Karn, Kvyas, Luweixian, Mathias-S, Michael Hardy, Mtekk, Nihiltres, Plugwash, Plutor, QTCaptain, Questionlp, R1ngu, Rchandra, Rilak, Salam32, ShadowHntr, TexasDex, Thief12, Tsman,Txuspe, Underjack, VoxLuna, W.F.Galway, William Allen Simpson, 89 anonymous edits

Ball grid array  Source: http://en.wikipedia.org/w/index.php?oldid=557224988  Contributors: Adrger, Alan Liefting, Alvis, Andy.gock, Anna Lincoln, AvicAWB, Berkut, Cburnett, CesarB,Coresoftwares, DJGB, David spector, DavidCary, Dsajga, EAi, Efa, Electron9, Fuzheado, Geummo, Glenn, Guanaco, Hankwang, Heron, Hooperbloob, Imroy, Ixfd64, Jarble, KA5BOU,KaiAdin, Laurasmithhp, Linear77, Magioladitis, Massestephanie, Michael Hardy, MichaelFrey, Mikeblas, Mortense, Nmesisgeek, Obersachse, Oleg Alexandrov, Patrick0Moran, Pearle,Peripitus, Petri Krohn, Pfagerburg, Plr4ever, Pol098, Pot, ProhibitOnions, Requestion, RevRagnarok, Rfqmaster, Richmeister, Rilak, Romanski, Ronz, Rundquist, Salam32, Sbmeirow, Sheinv,Shelbyroot, Spinningspark, Thumperward, Uberdude85, Vsood 007, Wangyiliu99, Welsh, Wingman4l7, Winterst, Wtshymanski, ZoidPod, ZyMOS, 107 anonymous edits

Pin grid array  Source: http://en.wikipedia.org/w/index.php?oldid=553472452  Contributors: AeonHun, AnOddName, Andros 1337, Anthony Appleyard, Asterion, Blue Em, Brucevdk, Cst17,D-Kuru, Davhorn, David.Monniaux, Dirk P Broer, Echosmoke, Edward, Efa, EugeneKay, Gadfium, Gene Nygaard, Gogo Dodo, Heron, Hooperbloob, Jarfil, LiamMCSHERRY,MarkusHagenlocher, McSherry, NavyPunk426, Northamerica1000, Pale blue dot, Petri Krohn, Rada, Radiojon, Ralesk, Rchandra, Richardcavell, Rilak, Salam32, SarahEmm, Savabore,TimBentley, Wtshymanski, Zippanova, ZyMOS, 45 anonymous edits

Dual in-line package  Source: http://en.wikipedia.org/w/index.php?oldid=551229718  Contributors: Adamantios, Alan Liefting, Alves, Andrewman327, Arch dude, Arndbergmann, Avlukashin,Azhyd, Biscuittin, Bobmilkman, Bryce, CLipka, Cburnett, Chryzler, CyrilB, Damian Yerrick, Daniel20AT, David.Monniaux, DavidCary, Davidelit, Dinjiin, DisillusionedBitterAndKnackered,Doug butler, Efa, Flowersofnight, Giftiger wunsch, Giftlite, Hooperbloob, Inductiveload, KD5TVI, Kms, Krótki, Laned130, Michael Hardy, MinimanDragon32, Mirror Vax, Omegatron, Orweb,OuphesAplenty, PHenry, Pengo, Plugwash, RoySmith, RuslanBer, Sangwine, Scottmeltzer, Special Cases, Spinningspark, Tattoosoo, TheAllSeeingEye, Thumperward, Tomy9510, Val42,Vanessaezekowitz, Vgandhi, Wbm1058, Wderousse, Wernher, Widders, Worm141, Wtshymanski, ZyMOS, 책읽는달팽, 80 anonymous edits

Chip carrier  Source: http://en.wikipedia.org/w/index.php?oldid=540388711  Contributors: Anthony Appleyard, Bearcat, Northamerica1000, Thumperward, Wtshymanski, 3 anonymous edits

Socket F  Source: http://en.wikipedia.org/w/index.php?oldid=540777024  Contributors: (:Julien:), AMD64, Aae, Angr, Bjrice, Brouhaha, Cburnett, Ceros, Cquarksnow, Crazytales, Denniss,DmitTrix, Dolda2000, Dr unix, Eleuther, GregorB, Grundig, Götz, Helicoprion, Help plz, Letowskie, Locos epraix, M1ss1ontomars2k4, Olegos, Olmsfam, Quadell, Robhu, Salam32, Sam Staton,SimonArlott, Skorp, Soumyasch, Superchad, The1physicist, Togtog, Vossanova, WBardwin, Wderousse, Where, Xajel, Ziggurat, Олександр Кравчук, 42 anonymous edits

Socket C32  Source: http://en.wikipedia.org/w/index.php?oldid=545781170  Contributors: Locos epraix, Pgk1, Shem1805, Smial, Zac67, 1 anonymous edits

Socket G34  Source: http://en.wikipedia.org/w/index.php?oldid=540769949  Contributors: Denniss, James086, LilHelpa, Locos epraix, Marcperkel, Mecanismo, Pgk1, Philforrest, Salam32,TYelliot, Wderousse, Wdwd, Олександр Кравчук, 20 anonymous edits

Image Sources, Licenses and Contributors 28

Image Sources, Licenses and ContributorsImage:Sockel 775.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Sockel_775.jpg  License: Creative Commons Attribution-Sharealike 2.0  Contributors: User Smial on de.wikipediaFile:Intel CPU Pentium 4 640 Prescott bottom.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Intel_CPU_Pentium_4_640_Prescott_bottom.jpg  License: Creative CommonsAttribution-Sharealike 3.0  Contributors: Eric Gaba (Sting - fr:Sting)File:Kl Intel Pentium MMX embedded BGA Bottom.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Kl_Intel_Pentium_MMX_embedded_BGA_Bottom.jpg  License: GNU FreeDocumentation License  Contributors: Konstantin LanzetImage:BGA RAM.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:BGA_RAM.jpg  License: GNU Free Documentation License  Contributors: User Smial on de.wikipediaImage:BGA joint xray.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:BGA_joint_xray.jpg  License: Public Domain  Contributors: DJGB, Inductiveload, Tothwolf, ZedhImage:Celeron mobile.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Celeron_mobile.jpg  License: Creative Commons Attribution-Sharealike 3.0  Contributors: AlecvFile:AMD Phenom II X6 1090T (HDT90ZFBK6DGR) CPU-pins PNr°0295.jpg  Source:http://en.wikipedia.org/w/index.php?title=File:AMD_Phenom_II_X6_1090T_(HDT90ZFBK6DGR)_CPU-pins_PNr°0295.jpg  License: unknown  Contributors: D-KuruImage:XC68020 bottom p1160085.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:XC68020_bottom_p1160085.jpg  License: Creative Commons Attribution-ShareAlike 3.0Unported  Contributors: User:David.MonniauxFile:AMD Phenom X4 9750 (Underside).JPG  Source: http://en.wikipedia.org/w/index.php?title=File:AMD_Phenom_X4_9750_(Underside).JPG  License: Creative CommonsAttribution-Sharealike 3.0  Contributors: User:LiamMCSHERRYImage:UpSL3A2.JPG  Source: http://en.wikipedia.org/w/index.php?title=File:UpSL3A2.JPG  License: Public Domain  Contributors: AHTOXAZZImage:Pentium 4 Underside Demonstrating PGA Socket.JPG  Source: http://en.wikipedia.org/w/index.php?title=File:Pentium_4_Underside_Demonstrating_PGA_Socket.JPG  License:Creative Commons Attribution-Sharealike 3.0  Contributors: User:LiamMCSHERRYImage:Ppga.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Ppga.jpg  License: Creative Commons Attribution-Sharealike 2.5  Contributors: alnImage:Socket 7.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Socket_7.jpg  License: GNU Free Documentation License  Contributors: AppaloosaFile:Cyrix_IBM_CPU_6x86MX_PR200_bottom.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Cyrix_IBM_CPU_6x86MX_PR200_bottom.jpg  License: Creative CommonsAttribution-Sharealike 3.0  Contributors: Eric Gaba (Sting - fr:Sting)File:VIA C3 C5XL CPGA.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:VIA_C3_C5XL_CPGA.jpg  License: Creative Commons Attribution-Sharealike 2.5  Contributors:EndorphinFile:Pentium P54 Socket7 PGA.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Pentium_P54_Socket7_PGA.jpg  License: Creative Commons Attribution-Sharealike 3.0 Contributors: AppaloosaFile:SL3A2down.JPG  Source: http://en.wikipedia.org/w/index.php?title=File:SL3A2down.JPG  License: Public Domain  Contributors: AHTOXAZZFile:AMD Athlon XP 2000 - Socket A - OPGA.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:AMD_Athlon_XP_2000_-_Socket_A_-_OPGA.jpg  License: Public Domain Contributors: Excession (talk). Original uploader was Excession at en.wikipediaFile:Three IC circuit chips.JPG  Source: http://en.wikipedia.org/w/index.php?title=File:Three_IC_circuit_chips.JPG  License: Public Domain  Contributors: Kimmo PalosaariImage:DIP sockets.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:DIP_sockets.jpg  License: GNU Free Documentation License  Contributors: Omegatron, WikipediaMasterFile:Breadboard counter.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Breadboard_counter.jpg  License: Copyrighted free use  Contributors: en:User:FulladderFile:DIP Cross-section.svg  Source: http://en.wikipedia.org/w/index.php?title=File:DIP_Cross-section.svg  License: Public Domain  Contributors: InductiveloadImage:Nec8080.png  Source: http://en.wikipedia.org/w/index.php?title=File:Nec8080.png  License: Public domain  Contributors: WdwdImage:SIL9 ST TDA4601.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:SIL9_ST_TDA4601.jpg  License: Creative Commons Attribution-ShareAlike 3.0 Unported  Contributors:NobbiPFile:R6511.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:R6511.jpg  License: GNU Free Documentation License  Contributors: Guido Körber (TheBug at de.wikipedia), contrastenhanced by Smial at de.wikipedia.Image:Pin numbering 01 Pengo.svg  Source: http://en.wikipedia.org/w/index.php?title=File:Pin_numbering_01_Pengo.svg  License: unknown  Contributors: Pengo, TothwolfFile:PD-icon.svg  Source: http://en.wikipedia.org/w/index.php?title=File:PD-icon.svg  License: Public Domain  Contributors: Alex.muller, Anomie, Anonymous Dissident, CBM, MBisanz, PBS,Quadell, Rocket000, Strangerer, Timotheus Canens, 1 anonymous editsImage:Qfj52.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Qfj52.jpg  License: Public Domain  Contributors: DLKSImage:80286 plcc.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:80286_plcc.jpg  License: Creative Commons Attribution-Sharealike 2.0  Contributors: User Smial on de.wikipediaImage:Qfj32gelötet.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Qfj32gelötet.jpg  License: GNU Free Documentation License  Contributors: DLKSFile:KL Intel 80286 CLCC.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:KL_Intel_80286_CLCC.jpg  License: Creative Commons Attribution-ShareAlike 3.0 Unported Contributors: Konstantin Lanzetimage:Socket F open R0027169.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Socket_F_open_R0027169.jpg  License: Creative Commons Attribution-Sharealike 2.0 Contributors: de:Benutzer:Smialimage:Socket F closed R0027170.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Socket_F_closed_R0027170.jpg  License: Creative Commons Attribution-Sharealike 2.0 Contributors: de:Benutzer:SmialFile:Supermicro dual opteron server board cpu socket IMGP7338 wp.jpg  Source:http://en.wikipedia.org/w/index.php?title=File:Supermicro_dual_opteron_server_board_cpu_socket_IMGP7338_wp.jpg  License: GNU Free Documentation License  Contributors: smial (talk)File:Socket G34.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Socket_G34.jpg  License: Creative Commons Attribution-Sharealike 3.0  Contributors: User:Philforrest

License 29

LicenseCreative Commons Attribution-Share Alike 3.0 Unported//creativecommons.org/licenses/by-sa/3.0/