WFI Consortium Meeting PRESENTATION OF OUR ACTIVITIES FOR X-RAY ASTROPHYSICS AND INTERESTS FOR ATHENA / WFI Garching – January 28, 2014 Aline Meuris On behalf of the Astrophysics division [email protected]| PAGE 1 Institute of Research into the Fundamental Laws of the Universe Astrophysics Division CEA Saclay, France
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WFI Consortium Meeting P RESENTATION OF OUR ACTIVITIES FOR X- RAY ASTROPHYSICS AND INTERESTS FOR A THENA / WFI Garching – January 28, 2014 Aline Meuris.
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CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
IMPLICATION IN ATHENA
Strong involvement in next X-ray large mission since 2001
XEUSMember of the steering group and ESA Science Advisory group (M. Arnaud)
IXOMember of the ESA Science Definition Team (M. Arnaud)
Members of instrument working group (O. Limousin for WFI/HXI, C. Pigot for calorimeter)
Athena(+)Member of the Athena Study Team (A. Decourchelle)
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CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
STRONG INTEREST IN ATHENA THEMES
The Hot Universe: How does ordinary matter assemble into the large scale structures that we see today?• "The Astrophysics of galaxy groups and clusters with Athena+"
Support paper by S.Ettori, G. Pratt et al.
The Energetic Universe: how do black holes grow and influence the Universe?• The physics of accretion
• Luminous extragalactic transients
Athena+ observatory capabilities• "The astrophysics of supernova remnants and the interstellar
medium" Support paper by A. Decourchelle, E. Costantini et al.
• "End points of stellar evolution" Support paper by C. Motch, J. Wilms et al. (J. Rodriguez)
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CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
REALIZATIONS FOR X-RAY ASTROPHYSICS
XMM-Newton (1999): 0.2-12 keV• Development of the EPIC MOS CCD Controller and Recognition Unit• Involvement in MOS CCD cameras calibration at Orsay• Contribution to the Science Survey Center
INTEGRAL / ISGRI (2001): 15-200 keV• Development of the ISGRI instrument (1024 cm2 CdTe)
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Polycell = ceramic with CdTe crystals and ASIC
CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
REALIZATIONS FOR X-RAY ASTROPHYSICS
SIMBOL-X: French-Italian hard X-ray telescope (2009)
CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
SPACE PROJECTS IN IMPLEMENTATION PHASE
Astro-H (JAXA)• Radiation damage study on CdTe detectors and ASICs
SVOM: GRB mission with China (PI institute)• MXT (0.2 – 10 keV): PI, Development of the camera • ECLAIRs (4 - 250 keV): Thermal design of the telescope,
Design and qualification of front-end ASIC IDeF-X ECLAIRs• Ground segment
Solar Orbiter (ESA M1)• Development of the X-ray spectrometers for STIX
Euclid (ESA M2)• Consortium lead (Y. Mellier IAP/CEA) and lead supports• Control electronics and AIV of the VIS focal plane
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Caliste-SO prototypes
CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
SKILLS DEVELOPED ALONG 20-YEAR EXPERIENCE
• Radiation hard low power low noise front-end ASIC• (ESA) Space qualification of ASIC and hybrid components• System (thermal, mechanical, electrical) architecture and design• Instrument modeling, integration, calibration
Microelectronics• Collaboration on very front-end electronics design• Parallel analog-to-digital conversion ASIC• Fabrication management and space qualification
Tests and qualification• Space qualification of full-custom components• Detector and electronics radiation damage studies
OWB-1 chip: R&D funded in 2012-2014 by CNES
can be the basis for a specific development
Wilkinson architecture with delay-locked loop add 4-5 bit precision with the same conversion time
Chip test: 32 channel converted in parallel in 2.7 µsto get 13-bit resolution
1.5 mW per channel
CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
POSSIBLE CONTRIBUTIONS TO ATHENA+ WFI
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Hybridization• Chip and EEE assembly and ceramic hybridization, interconnects• Hybridization qualification
System and architecture• Mechanical design, thermal design and modeling of the focal plane• Background simulation
Example:
MXT detector board prototype
Collaboration with MPE
Layout by CEA, fabrication by a French space-certified company
Mounting of ASIC and pnCCD by MPE
CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
POSSIBLE CONTRIBUTIONS TO ATHENA+ WFI
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Warm front-end electronics
• Real-time processing in interface with the cold front-end electronics to
guarantee system performance
Similar challenges experienced with Herschel/PACS.
Example:
MXT front-end electronics prototype
« Pixel sequencer » and « frame sequencer » based on space grade FPGA
CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
CONCLUSION
CEA-Irfu highly interested in taking part in WFI consortium• Astrophysics groups defending Athena+ science case• Experience in detection system design and realization at different
levels to serve the instrument performance
THANK YOU FOR YOUR ATTENTION.
CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
THANK YOU FOR YOUR ATTENTION
BACK-UP SLIDES
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CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
THE OWB-1 ADC : GLOBAL ARCHITECTURE
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Architecture Wilnkinson with DLL (delay-locked loop)
The conversion time of this N+M bits ADC is :
𝑇 𝐶=2𝑁
𝐹𝐶𝐿𝐾
=2𝑁+𝑀
𝐹𝐷𝐿𝐿
Adding conversion bits for a same time compared to a conventional 𝑴Wilkinson architecture
CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
THE OWB-1 ADC : MAIN FEATURES
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FEATURE (OWB-1)
Technology CMOS AMS 0.35µm (C35B4C3)
Number of Channel 32
Resolution 12-13 bits (7-8 for the counter and 5 for the DLL)
Input voltage 2 V (from 0.8 to 2.8 typical)
Conversion time 1,5 - 2,7 µs (12-13 bits)
Output 11 bits parallel or 2 bits LVDS (Low Voltage Differential Signaling)
Consumption Typical condition : 1.5 mW per channel (see details next slides)
Clock input 100 MHz for counter
Input PADs pitch 150 µm
Channel with 50 µm
Radiation hardness SEL free : LET>110 MeV/(mg/cm²)
SEU Flag for slow control.
ASIC OWB-1 : analog to digital conversion optimized for the readout of self-triggered ASIC for CdTe detectors. Design for low count rate applications.
CEA/Irfu | WFI Consortium meeting Garching | January 28, 2014
THE OWB-1 ADC : MODES OF OPERATION
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Data format : Channel (5 bits) + Code (14 bits)
Data transfer during conversion:
Two modes of DATA (code) transfer : // and serial
MODE // Serial Mode
Number of digital output PAD/ASIC 11 (CMOS) 2 (LVDS)