WEBINAR: Digital Power Management, Power Integrity, and Power Rail Sequence Analysis & Testing March 2 nd , 2017 Thank you for joining us. We will begin at 1:00pm EST. NOTE: This presentation includes Q&A. We will be taking questions during the presentation with answers at the end using the questions section of your control panel. March 2, 2017 1
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Webinar Slides: Digital Power Management and Power Integrity Analysis and Testing
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WEBINAR: Digital Power Management, Power Integrity, and Power Rail SequenceAnalysis & TestingMarch 2nd, 2017Thank you for joining us. We will begin at 1:00pm EST. NOTE: This presentation includes Q&A. We will be taking questions during the presentation with answers at the end using the questions section of your control panel.
March 2, 2017 1
Teledyne LeCroy Overview
March 2, 2017 2
LeCroy was founded in 1964 by Walter LeCroy Original products were high-speed digitizers
for particle physics research Corporate headquarters is in Chestnut Ridge,
NY Long history of innovation in digital
oscilloscopes First digital storage oscilloscope Highest bandwidth real-time oscilloscope
(100 GHz) LeCroy became the world leader in protocol
analysis with the purchase of CATC and Catalyst Frontline Test Equipment and Quantum
Data were also recently acquired (2016) In 2012, LeCroy was acquired by Teledyne
Technologies and renamed Teledyne LeCroy
• Product Manager with Teledyne LeCroy for over 15 years
• B.S., Electrical Engineering from Rensselaer Polytechnic Institute
• Awarded three U.S. patents for in the field of simultaneous physical layer and protocol analysis
Ken JohnsonDirector of Marketing, Product ArchitectTeledyne [email protected]
March 2, 2017 3
About the Presenter
Digital Power Management, Power Integrity, and Power Rail SequenceAnalysis & Testing
Test single or multi-phase digital power management ICs (PMICs), voltage regulator modules (VRMs), point-of-load (POLs) switching regulators, low-dropout (LDO) regulators or other DC-DC converter operations under transient load conditions, and test complete embedded systems that contain these devices.
March 2, 2017 4
Agenda
Overview Acquiring DC Voltage/Power Rails Transient Rail Response Analysis
Single Rail Multiple Rails
Multi-phase PMIC DC-DC Converter Current Sharing/Tracking Analysis Voltage/Power Rail Sequence Testing Power Integrity Measurement and Debug Examples Summary Questions
March 2, 2017 5
Overview
March 2, 2017 6
Power Electronics Designs are Used Everywhere…
March 2, 2017 7
This Webinar’s Focus is on the Following
Digital Power Management The control of various DC-DC converter voltages to
ensure appropriate and prompt delivery of current (power) over one or more DC power/voltage rails to various CPU, memory, or other devices in a motherboard or embedded computing system.
Power Integrity The analysis to determine whether expected voltage
and current requirements are met from regulated DC output to the power consuming device.
Voltage/Power Rail Sequence Testing The control of the ramp times and sequence of the
various DC power/voltage rails in a motherboard or embedded computing system.
March 2, 2017 8
Digital Power Management Overview
An embedded computing system requires one or more different “rails” (e.g., 3.3, 1.8, 1.5, 1.1Vdc) to provide voltage and current to the CPU and other on-board devices.
Bulk power is supplied to an embedded computing system through a high voltage (e.g., 12Vdc) bus/supply.
To provide high efficiency, each DC-DC converter power supply is actually several DC-DC converters in parallel.
In this example, there are four parallel DC-DC converters (called “phases” or “channels”) that each supply 25% of the total output current to the 1.1Vdc rail.
A Power Management IC (PMIC) turns the phases on and off as load power requirements change, and time interleaves the PWM outputs into one output.
The PMIC and CPU are both located on a motherboard of some type. The motherboard may be part of a larger stand-alone embedded system, or it could be used in a server, laptop, tablet, mobile phone, gaming system, consumer device, etc.
4 “phase” or “channel”
outputs from one DC-DC converter
1 DC power / voltage rail
March 2, 2017 9
PMIC
The CPU issues serial data commands to the PMIC so as to ensure proper current supply to all devices
Digital Power Management and Power IntegrityHalf-bridge output
The half-bridge output current is commonly called the “inductor current” because it flows through the output inductor (filter). It increases (ramps up)
when PWM signals are “ON” and ramps down when PWM signals are “OFF”
Additional load capacitance will filter this further
March 2, 2017 10
Digital Power Management and Power IntegrityIdeal operation of multiple PMIC phases
Ideally, each PMIC phase under steady-state load condition is balanced Same amplitude (voltage PWM) Phase relationship to other
phases of (1/fs)/N fs is the power semiconductor
device switching frequency N is the number of phases
Example - these are the phase currents under steady-state operating conditions after filtering by the inductor
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Digital Power Management and Power IntegrityNon-ideal operation of multiple phases
If there are amplitude errors between the different phases, output ripple will result
If there are amplitude and phase errors between the different phases, more complicated distortion patterns will be introduced
March 2, 2017 12
First Polling Question (choose one or more)
What products are you designing and testing? Multi-phase Digital Power Management ICs (PMICs) VRM, POL or LDO regulators Unregulated DC supplies Embedded Systems using one or more of the above None of the above
March 2, 2017 13
Acquiring DC Power/Voltage Rails
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Acquiring DC Power/Voltage Rails There are three methods (but only one very good method)1. 50Ω Coaxial Cable Terminated at
Oscilloscope Input with DC 1MΩCoupling Reasonable noise performance, but… Requires high offset capability in the
oscilloscope…. or requires use of a DC block (not ideal)
(good for larger circuit boards – attach and leave in place for quick and easy connection to cable)
MCX Solder-in Lead (4 GHz)(can be soldered-in and left in circuit)
SMA to MCX short cable
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MCX to U.FL Lead (3 GHz)(attaches to compact U.FL PCB
Mounts).
MCX to SMA Adapter
U.FL PCB Mounts(compact size for dense, mobile or
handheld systems)
RP4030 Equivalent Circuit DiagramThe RP4030 probe is shaded in gray, and the cable and oscilloscope are not shaded
March 2, 2017 22
High Bandwidth SMA Connector
MCX Termination Provides Flexibility for DUT Connection
High DC Input Impedance (Low DUT Loading) with Low
High Frequency Input Impedance
High precision, high dynamic range offset DAC
(16-bit, 30V)
Auto Zero of Probe Can be Done While Connected to DUT
RP4030 U.FL Solution for Compact PCBs
Hirose U.FL ultra-miniature PCB mounts can be designed in to make probing easy 3mm x 3mm Functionally equivalent to IPX
and UMCC connectors 3 GHz Low cost
March 2, 2017 23
Removal is simple with a widely available special-purpose extraction tool
RP4030 Solder-in Lead
Solder-in Lead Provides Optimum Performance 4 GHz Reasonable cost
Multiple Leads Can be Soldered-in and Left in Place
March 2, 2017 24
RP4030 Optional Browser
SMA to SMA Cable
(for connecting to the RP4030 ProBus
compatible amplifier)
SMA to BNC Adapter
(for connecting directly to a scope BNC input if used as
a PP066 Transmission Line Probe)
Browser Tip with 0Ω Resistor
(for low attenuation, good noise performance)
450Ω and 950ΩResistors
(for use as 10x or 20x PP066 equivalent)
March 2, 2017 25
Other Teledyne LeCroy Voltage and Current ProbesThat are commonly used in Digital Power Management and Power Integrity Testing
Differential Amplifiers (DA1855A) and Probes (AP033) with 10x Gain Ideal for shunt/series resistor
measurements Up to 100 dB CMRR
High Sensitivity Current Probes 50 or 100 MHz
Low-cost 1 GHz Active FET Probe Great for general probing or
power sequence testing
March 2, 2017 26
10x Gain Differential Voltage Probe for Series/Shunt ResistorTop is a conventional diff probe, bottom is a CMRR optimized probe amplifier with 10x gain
March 2, 2017 27
Second Polling Question (choose one or more)
What types of probes do you use today to probe DC power/voltage rails? Coaxial cables (50Ω input coupled to oscilloscope) Coaxial cables (1MΩ input coupled to oscilloscope) Conventional 10x passive probes Conventional single-ended active voltage probes Active voltage rail probe (power rail probe)
March 2, 2017 28
Transient Rail Response AnalysisOf a single voltage/power rail
March 2, 2017 29
Typical Digital Power Management and Power Integrity TestsFor One PMIC (One DC Voltage/Power Rail) PMIC Transient DC Rail Response
Addition or release (subtraction) of load Dynamic test Long capture time is very useful Correlate activity to other signals
Serial data commands Clocks / Strobes Enable lines
Measure DC Rail and Ensure that Tolerances are Met Mean voltage value Ripple Ringing Peak+ and Peak- Settling Time Droop
DC Rail
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Example of Commonly Measured Voltage/Power Rail Parameters
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7 mV/div993 mV offset
DroopRipple
(Periodic and Random Disturbances)
Settling
RippleCurrent
Transient
Peak -
Recovery Time
PMIC Transient Rail Response TestingAcquiring and Viewing the Transient Response of a Single DC Rail
Load increased from ~0 to 20A
DC Rail voltage transient response is monitored
7 mV/div gain setting with 1Vdc offset
March 2, 2017 32
20A
No-load (near 0A)
Mean DC = 999.67mVMean DC = 1003mV
Load current
1.0V multi-phase railAcquired using the
RP4030 Active Voltage Rail Probe
Acquired using the CP030A High-sensitivity
Current Probe
PMIC Transient Rail Response Testing, cont’dQuantifying the Transient Response of a Single DC Rail with Measurement Parameters Measurement
Parameters with Gates can be used to measure VdcRAIL before and after load. 999.67 mV before 1003.00 mV after
Zooms and measurement parameters can be used to understand high-frequency behaviors Z1 = VMIN at step
(967.70 mV) Z5 = VMAX before
step (1012.21 mV) Z7 = VMAX after step
(1016.38 mV) Measure Parameter can
be used to measure step load change 20.436 A
March 2, 2017 33
DC Rail Current
DC Rail Voltage
Mean DC = 999.67mVMean DC = 1003mV
12-bit Resolution
PMIC Transient Rail Response Testing, cont’dPer-cycle Waveforms and Numerics to understand rail behaviors (DIG-PWR-MGMT option)
March 2, 2017 34
Load current
Mean Value Numerics Table of 1V Rail
Acquired Waveforms
Per-cycle Calculated WaveformsThese waveforms have one calculated
Potential variables: DC load current DC input voltage DC output voltage Temperature AC excitation current
Impedance magnitude [Ohm]
Output Impedance vs. DC Load Current (Light Load)
March 2, 2017 45
Output voltage transient
Current-sense voltage Sum of inductor
currents
Three inductor currents
Transient Current Step
March 2, 2017 46
Current Sharing vs. Frequency
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Voltage/Power Rail Sequence Testing
March 2, 2017 48
What is Sequence Testing? For the computing system to
“boot-up” correctly, the DC rails must turn ON in a specific order with specific “wait times” between each turn ON.
For example, First 3.3Vdc goes high Then, 200-500ms later, 1.8Vdc
goes high Then 200-500ms later, 1.5Vdc
goes high Lastly, 500ms-800ms later,
1.1Vdc goes high
March 2, 2017 49
What are Sequencing Tests? Acquire as many DC rail signals as
possible More is better – great 8ch application
Acquire other signals, e.g.: Clocks PMIC enable Strobes Serial data command signals to PMIC
Measure timing between signals Usually with cursors Serial TDME options could be useful to
some customers Long capture times with high SR are
common 250 Mpts of memory is very useful Capture a lot of time at high sample
rate in many different start-up scenarios, and zoom for details
The image above is a start-up sequencing requirement (timing details are omitted) for a TI embedded ARM microprocessor (http://www.ti.com.cn/product/cn/AM3358-EP/datasheet/6_ZHCSE24A
Note the many different rail voltages (5 different) and multiple 1.8Vdc rails – this is very common Important reason why 8ch is very, very useful
Transient Load Response Jitter AnalysisThe POL output voltage droop to the clock causes large clock jitter
March 2, 2017 71
TIE Jitter Overlay of 10 MHz clock acquisitionThis persistence overlay of the clock cycles shows very little
jitter with a small number of clock edges having significant jitter
TIE Jitter vs. time for the 10 MHz clockJitter can be seen to vary significantly during voltage droop
200ps TIE Jitter per vertical
division
POL Output Voltage to 10 MHz clock vs. time100mV droop occurs during step load
Jitter is quantified with Time Interval Error measurement. Peak to peak jitter is 1ns which is 1/8 of a period
Transient Load Response – Power Switched on to a Second ClockLoad of second clock causes POL voltage droop and impacts 10 MHz clock functioning
March 2, 2017 72
POL Output Voltage to 10 MHz clock vs. time
Zoom of above trace
10 MHz Clock Voltage vs. time
Zoom of above trace
Third Polling Question (choose one or more)
What types of testing do you do? Analysis of a single or multiple voltage/power rail(s) Multi-phase current tracking/sharing Power rail sequence testing and timing Embedded system debug for some/all of the above None of the above
March 2, 2017 73
Summary
March 2, 2017 74
Teledyne LeCroy Equipment for Digital Power Management, Power Integrity, and Power Sequencing Test and Analysis
March 2, 2017 75
4 or 8 channel, 12 bit, 1 GHz Oscilloscopes
Comprehensive Probe Offering
DIG-PWR-MGMT Digital Power Management Analysis Software Option
Serial Trigger, Decode, Measure/Graph and Eye Diagram